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  8 bit microcontroller tlcs-870/c1 series tmp89fw20a
? 2012 toshiba corporation all rights reserved
revision history date revision comment 2012/5/18 1 first release

table of contents tmp89fw20a 1.1 features......................................................................................................................................1 1.2 pin assignment..........................................................................................................................4 1.3 block diagram........................................................................................................................... 5 1.4 pin names and functions..........................................................................................................6 2. cpu core 2.1 configuration........................................................................................................................... 11 2.2 memory space......................................................................................................................... 11 2.2.1 code area........................................................................................................................................................................... 11 2.2.1.1 ram 2.2.1.2 bootrom 2.2.1.3 flash 2.2.2 data area............................................................................................................................................................................ 15 2.2.2.1 sfr 2.2.2.2 ram 2.2.2.3 bootrom 2.2.2.4 flash 2.3 system clock controller........................................................................................................... 17 2.3.1 configuration..................................................................................................................................................................... 17 2.3.2 control............................................................................................................................................................................... 17 2.3.3 functions............................................................................................................................................................................ 20 2.3.3.1 clock generator 2.3.3.2 clock gear 2.3.3.3 timing generator 2.3.4 warm-up counter ............................................................................................................................................................... 27 2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software 2.3.5 operation mode control circuit......................................................................................................................................... 29 2.3.5.1 single-clock mode 2.3.5.2 dual-clock mode 2.3.5.3 stop mode 2.3.5.4 transition of operation modes 2.3.6 operation mode control................................................................................................................................................... 35 2.3.6.1 stop mode 2.3.6.2 idle1/2 and sleep1 modes 2.3.6.3 idle0 and sleep0 modes 2.3.6.4 slow mode 2.4 reset control circuit............................................................................................................... 47 2.4.1 configuration..................................................................................................................................................................... 47 2.4.2 control............................................................................................................................................................................... 47 2.4.3 functions............................................................................................................................................................................ 49 2.4.4 reset signal enerating factors....................................................................................................................................... 51 2.4.4.1 power-on reset 2.4.4.2 external reset input (reset pin input) 2.4.4.3 voltage detection reset 2.4.4.4 watchdog timer reset 2.4.4.5 system clock reset 2.4.4.6 internal factor reset detection status register 2.4.4.7 how to use the external reset input pin as a port i
3. interrupt control circuit 3.1 configuration........................................................................................................................... 57 3.2 interrupt latches ( il30 to il3)............................................................................................... 58 3.3 interrupt enable register ( eir).............................................................................................. 59 3.3.1 interrupt master enable flag ( imf)................................................................................................................................... 59 3.3.2 individual interrupt enable flags (ef30 to ef4) .............................................................................................................. 59 3.4 maskable interrupt priority change function........................................................................ 62 3.5 interrupt sequence................................................................................................................... 64 3.5.1 initial setting..................................................................................................................................................................... 64 3.5.2 interrupt acceptance processing........................................................................................................................................ 64 3.5.3 saving/restoring general-purpose registers ....................................................................................................................... 66 3.5.3.1 using push and pop instructions 3.5.3.2 using data transfer instructions 3.5.3.3 using a register bank to save/restore general-purpose registers 3.5.4 interrupt return ...................................................................................................................................................................68 3.6 software interrupt ( intsw)................................................................................................... 69 3.6.1 address error detection..................................................................................................................................................... 69 3.6.2 debugging..........................................................................................................................................................................69 3.7 undefined instruction interrupt ( intundef)....................................................................... 69 4. external interrupt control circuit 4.1 configuration........................................................................................................................... 71 4.2 control..................................................................................................................................... 71 4.3 function................................................................................................................................... 75 4.3.1 low power consumption function.................................................................................................................................... 76 4.3.2 external interrupt 0 ............................................................................................................................................................ 76 4.3.3 external interrupts 1/2/3.................................................................................................................................................... 77 4.3.3.1 interrupt request signal generating condition detection function 4.3.3.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.3.3 noise cancel time selection function 4.3.4 external interrupt 4............................................................................................................................................................78 4.3.4.1 interrupt request signal generating condition detection function 4.3.4.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.4.3 noise cancel time selection function 4.3.5 external interrupt 5............................................................................................................................................................80 5. watchdog timer ( wdt) 5.1 configuration........................................................................................................................... 81 5.2 control..................................................................................................................................... 82 5.3 functions.................................................................................................................................. 84 5.3.1 setting of enabling/disabling the watchdog timer operation............................................................................................ 84 5.3.2 setting the clear time of the 8-bit up counter................................................................................................................... 84 5.3.3 setting the overflow time of the 8-bit up counter............................................................................................................ 85 5.3.4 setting an overflow detection signal of the 8-bit up counter...........................................................................................85 5.3.5 writing the watchdog timer control codes....................................................................................................................... 86 5.3.6 reading the 8-bit up counter.............................................................................................................................................86 5.3.7 reading the watchdog timer status................................................................................................................................... 86 6. power-on reset circuit 6.1 configuration........................................................................................................................... 89 ii
6.2 function................................................................................................................................... 89 7. voltage detection circuit 7.1 configuration........................................................................................................................... 91 7.2 control..................................................................................................................................... 92 7.3 function................................................................................................................................... 93 7.3.1 enabling/disabling the voltage detection operation.......................................................................................................... 93 7.3.2 selecting the voltage detection operation mode ............................................................................................................... 93 7.3.3 selecting the detection voltage level................................................................................................................................ 94 7.3.4 voltage detection flag and voltage detection status flag.................................................................................................. 94 7.4 register settings...................................................................................................................... 96 7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals............................. 96 7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals..................................... 96 7.5 caution in the using voltage detevtion circuit........................................................................ 97 8. io ports 8.1 i/o port control registers.....................................................................................................101 8.2 list of i/o port settings........................................................................................................ 102 8.3 i/o port registers.................................................................................................................. 105 8.3.1 port p0 ( p03 ~ p00) ....................................................................................................................................................... 105 8.3.2 p1 ( p13 ~ p10) ............................................................................................................................................................... 109 8.3.3 port p2 ( p25 ~ p20)........................................................................................................................................................ 113 8.3.4 port p4 ( p47 ~ p40)........................................................................................................................................................ 118 8.3.5 port p5 ( p57 ~ p50)........................................................................................................................................................ 121 8.3.6 port p6 ( p67 ~ p60) ....................................................................................................................................................... 124 8.3.7 port p7 ( p77 ~ p70)........................................................................................................................................................ 126 8.3.8 port p9 ( p97 ~ p90)........................................................................................................................................................ 128 8.4 peripheral input/output select function................................................................................. 130 9. special function registers 9.1 sfr1 ( 0x00000 to 0x0003f).................................................................................................135 9.2 sfr2 ( 0x00f00 to 0x00fff)................................................................................................ 136 9.3 sfr3 ( 0x00e40 to 0x00eff)................................................................................................ 138 10. low power consumption function for peripherals 10.1 control................................................................................................................................. 142 11. divider output ( dvo) 11.1 configuration....................................................................................................................... 145 11.2 control ................................................................................................................................. 146 11.3 function............................................................................................................................... 147 iii
12. time base timer (tbt) 12.1 time base timer................................................................................................................. 149 12.1.1 configuration................................................................................................................................................................. 149 12.1.2 control........................................................................................................................................................................... 149 12.1.3 functions........................................................................................................................................................................ 150 13. 16-bit timer counter ( tca) 13.1 configuration....................................................................................................................... 154 13.2 control................................................................................................................................. 155 13.3 low power consumption function.................................................................................... 160 13.4 timer function.................................................................................................................... 161 13.4.1 timer mode.................................................................................................................................................................... 161 13.4.1.1 setting 13.4.1.2 operation 13.4.1.3 auto capture 13.4.1.4 register buffer configuration 13.4.2 external trigger timer mode.......................................................................................................................................... 165 13.4.2.1 setting 13.4.2.2 operation 13.4.2.3 auto capture 13.4.2.4 register buffer configuration 13.4.3 event counter mode....................................................................................................................................................... 167 13.4.3.1 setting 13.4.3.2 operation 13.4.3.3 auto capture 13.4.3.4 register buffer configuration 13.4.4 window mode................................................................................................................................................................ 169 13.4.4.1 setting 13.4.4.2 operation 13.4.4.3 auto capture 13.4.4.4 register buffer configuration 13.4.5 pulse width measurement mode.................................................................................................................................... 171 13.4.5.1 setting 13.4.5.2 operation 13.4.5.3 capture process 13.4.6 programmable pulse generate ( ppg) mode.................................................................................................................. 174 13.4.6.1 setting 13.4.6.2 operation 13.4.6.3 register buffer configuration 13.5 noise canceller................................................................................................................... 177 13.5.1 setting............................................................................................................................................................................ 177 14. 16-bit timer counter ( tcb) 14.1 configuration....................................................................................................................... 180 14.2 control................................................................................................................................. 181 14.3 low power consumption function.................................................................................... 185 14.4 timer function.................................................................................................................... 186 14.4.1 timer mode.................................................................................................................................................................... 186 14.4.1.1 setting 14.4.1.2 operation 14.4.1.3 auto capture 14.4.1.4 register buffer configuration 14.4.2 external trigger timer mode.......................................................................................................................................... 190 14.4.2.1 setting 14.4.2.2 operation 14.4.2.3 auto capture 14.4.2.4 register buffer configuration iv
14.4.3 event counter mode....................................................................................................................................................... 192 14.4.3.1 setting 14.4.3.2 operation 14.4.3.3 auto capture 14.4.3.4 register buffer configuration 14.4.4 window mode................................................................................................................................................................ 194 14.4.4.1 setting 14.4.4.2 operation 14.4.4.3 auto capture 14.4.4.4 register buffer configuration 14.4.5 pulse width measurement mode....................................................................................................................................196 14.4.5.1 setting 14.4.5.2 operation 14.4.5.3 capture process 14.4.6 programmable pulse generate ( ppg) mode..................................................................................................................199 14.4.6.1 setting 14.4.6.2 operation 14.4.6.3 register buffer configuration 14.5 noise canceller................................................................................................................... 202 14.5.1 setting............................................................................................................................................................................202 15. 10-bit timer/counter ( tcc) 15.1 configuration....................................................................................................................... 204 15.2 control................................................................................................................................. 205 15.3 low power consumption function.................................................................................... 211 15.4 configuring control and data registers............................................................................. 212 15.5 features ................................................................................................................................ 214 15.5.1 programmable pulse generator output ( ppg output)....................................................................................................214 15.5.1.1 50% duty mode 15.5.1.2 variable duty mode 15.5.1.3 ppgc01/ppgc02 independent mode 15.5.2 starting a count.............................................................................................................................................................. 218 15.5.2.1 command start and capture mode(tc0cr2="00") 15.5.2.2 command start and trigger start mode(tc0cr2="01") 15.5.2.3 trigger start mode(tc0cr2="10") 15.5.3 trigger capture.............................................................................................................................................................. 221 15.5.3.1 description 15.5.3.2 register settings 15.5.4 trigger start/stop acceptance mode............................................................................................................................... 222 15.5.4.1 selecting an input signal logic for the tcc0 pin (trigger input) 15.5.4.2 specifying whether triggers are always accepted or ignored when ppg outputs are active 15.5.4.3 ignoring triggers when ppg outputs are active 15.5.5 configuring how the timer stops.................................................................................................................................. 224 15.5.5.1 counting stopped with the outputs initialized 15.5.5.2 counting stopped with the outputs maintained 15.5.5.3 counting stopped with the outputs initialized at the end of the period 15.5.6 one - time/continuous output mode............................................................................................................................ 225 15.5.6.1 one-time output mode 15.5.6.2 continuous output mode 15.5.7 ppg output control ( initial value/output logic, enabling/disabling output)................................................................. 227 15.5.7.1 specifying initial values and output logic for ppg outputs 15.5.7.2 enabling or disabling ppg outputs 15.5.7.3 using the tcc0 as a normal timer/counter 15.5.8 eliminating noise from the tcc0 pin input................................................................................................................. 228 15.5.9 interrupts........................................................................................................................................................................229 15.5.9.1 inttcc0t (trigger start interrupt) 15.5.9.2 inttcc0p (period interrupt) 15.5.9.3 intemg0 (emergency output stop interrupt) 15.5.10 emergency ppg output stop feature........................................................................................................................... 231 15.5.10.1 enabling/disabling input on the emg0 pin 15.5.10.2 monitoring the emergency ppg output stop state 15.5.10.3 emg interrupt 15.5.10.4 canceling the emergency ppg output stop state 15.5.10.5 restarting the timer after canceling the emergency ppg output stop state 15.5.10.6 response time between emg0 pin input and ppg outputs being initialized 15.5.11 tcc0 operation and microcontroller operating mode ................................................................................................232 15.5.12 considerations for using the development tools of tcc0........................................................................................ 233 v
16. 8-bit timer counter ( tc0) 16.1 configuration....................................................................................................................... 236 16.2 control................................................................................................................................. 237 16.2.1 timer counter 00 ........................................................................................................................................................... 237 16.2.2 timer counter 01 ........................................................................................................................................................... 239 16.2.3 common to timer counters 00 and 01 .......................................................................................................................... 241 16.2.4 operation modes and usable source clocks.................................................................................................................. 243 16.3 low power consumption function.................................................................................... 244 16.4 functions.............................................................................................................................. 245 16.4.1 8-bit timer mode............................................................................................................................................................ 245 16.4.1.1 setting 16.4.1.2 operation 16.4.1.3 double buffer 16.4.2 8-bit event counter mode............................................................................................................................................... 248 16.4.2.1 setting 16.4.2.2 operation 16.4.2.3 double buffer 16.4.3 8-bit pulse width modulation ( pwm) output mode..................................................................................................... 250 16.4.3.1 setting 16.4.3.2 operations 16.4.3.3 double buffer 16.4.4 8-bit programmable pulse generate ( ppg) output mode.............................................................................................. 255 16.4.4.1 setting 16.4.4.2 operation 16.4.4.3 double buffer 16.4.5 16-bit timer mode.......................................................................................................................................................... 259 16.4.5.1 setting 16.4.5.2 operations 16.4.5.3 double buffer 16.4.6 16-bit event counter mode............................................................................................................................................. 263 16.4.6.1 setting 16.4.6.2 operations 16.4.6.3 double buffer 16.4.7 12-bit pulse width modulation ( pwm) output mode................................................................................................... 265 16.4.7.1 setting 16.4.7.2 operations 16.4.7.3 double buffer 16.4.8 16-bit programmable pulse generate ( ppg) output mode............................................................................................ 271 16.4.8.1 setting 16.4.8.2 operations 16.4.8.3 double buffer 17. real time clock ( rtc) 17.1 configuration....................................................................................................................... 275 17.2 control................................................................................................................................. 275 17.3 function............................................................................................................................... 276 17.3.1 low power consumption function .............................................................................................................................. 276 17.3.2 enabling/disabling the real time clock operation......................................................................................................... 276 17.3.3 selecting the interrupt generation interval.................................................................................................................... 276 17.4 real time clock operation................................................................................................ 277 17.4.1 enabling the real time clock operation......................................................................................................................... 277 17.4.2 disabling the real time clock operation........................................................................................................................ 277 18. asynchronous serial interface ( uart) 18.1 configuration....................................................................................................................... 280 18.2 control................................................................................................................................. 281 vi
18.3 low power consumption function.................................................................................... 285 18.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed .... 286 18.5 activation of stop, idle0 or sleep0 mode..................................................................287 18.5.1 transition of register status........................................................................................................................................... 287 18.5.2 transition of txd pin status........................................................................................................................................ 287 18.6 transfer data format.......................................................................................................... 288 18.7 infrared data format transfer mode..................................................................................288 18.8 transfer baud rate..............................................................................................................289 18.8.1 transfer baud rate calculation method.......................................................................................................................... 290 18.8.1.1 bit width adjustment using uart0cr2 18.8.1.2 calculation of set values of uart0cr2 and uart0dr 18.9 data sampling method........................................................................................................ 293 18.10 received data noise rejection.........................................................................................295 18.11 transmit/receive operation..............................................................................................296 18.11.1 data transmit operation............................................................................................................................................... 296 18.11.2 data receive operation.................................................................................................................................................296 18.12 status flag......................................................................................................................... 297 18.12.1 parity error................................................................................................................................................................... 297 18.12.2 framing error.............................................................................................................................................................. 298 18.12.3 overrun error...............................................................................................................................................................299 18.12.4 receive data buffer full............................................................................................................................................ 302 18.12.5 transmit busy flag..................................................................................................................................................... 303 18.12.6 transmit buffer full.................................................................................................................................................... 303 18.13 receiving process..............................................................................................................304 18.14 ac properties.................................................................................................................... 306 18.14.1 irda properties............................................................................................................................................................306 19. synchronous serial interface ( sio) 19.1 configuration....................................................................................................................... 308 19.2 control................................................................................................................................. 309 19.3 low power consumption function.................................................................................... 312 19.4 functions.............................................................................................................................. 313 19.4.1 transfer format.............................................................................................................................................................. 313 19.4.2 serial clock....................................................................................................................................................................313 19.4.3 transfer edge selection.................................................................................................................................................. 313 19.5 transfer modes....................................................................................................................315 19.5.1 8-bit transmit mode....................................................................................................................................................... 315 19.5.1.1 setting 19.5.1.2 starting the transmit operation 19.5.1.3 transmit buffer and shift operation 19.5.1.4 operation on completion of transmission 19.5.1.5 stopping the transmit operation 19.5.2 8-bit receive mode....................................................................................................................................................... 320 19.5.2.1 setting 19.5.2.2 starting the receive operation 19.5.2.3 operation on completion of reception 19.5.2.4 stopping the receive operation 19.5.3 8-bit transmit/receive mode...........................................................................................................................................324 19.5.3.1 setting 19.5.3.2 starting the transmit/receive operation 19.5.3.3 transmit buffer and shift operation 19.5.3.4 operation on completion of transmission/reception 19.5.3.5 stopping the transmit/receive operation 19.6 ac characteristics............................................................................................................... 329 vii
20. serial bus interface ( sbi) 20.1 communication format....................................................................................................... 332 20.1.1 i2c bus........................................................................................................................................................................... 332 20.1.2 free data format............................................................................................................................................................. 333 20.2 configuration....................................................................................................................... 334 20.3 control................................................................................................................................. 335 20.4 functions.............................................................................................................................. 338 20.4.1 low power consumption function .............................................................................................................................. 338 20.4.2 selecting the slave address match detection and the general call detection.................................................... 338 20.4.3 selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode ....................................................................................................................................................................................... 338 20.4.3.1 number of clocks for data transfer 20.4.3.2 output of an acknowledge signal 20.4.4 serial clock....................................................................................................................................................................340 20.4.4.1 clock source 20.4.4.2 clock synchronization 20.4.5 master/slave selection.................................................................................................................................................... 342 20.4.6 transmitter/receiver selection....................................................................................................................................... 342 20.4.7 start/stop condition generation ...................................................................................................................................... 343 20.4.8 interrupt service request and release.............................................................................................................................343 20.4.9 setting of serial bus interface mode............................................................................................................................. 344 20.4.10 software reset.............................................................................................................................................................. 344 20.4.11 arbitration lost detection monitor...............................................................................................................................344 20.4.12 slave address match detection monitor...................................................................................................................... 346 20.4.13 general call detection monitor......................................................................................................................... 346 20.4.14 last received bit monitor............................................................................................................................................ 347 20.4.15 slave address and address recognition mode specification........................................................................................ 347 20.5 data transfer of i2c bus.................................................................................................... 348 20.5.1 device initialization.......................................................................................................................................................348 20.5.2 start condition and slave address generation................................................................................................................348 20.5.3 1-word data transfer....................................................................................................................................................... 349 20.5.3.1 when sbi0sr2 is "1" (master mode) 20.5.3.2 when sbi0sr2 is "0" (slave mode) 20.5.4 stop condition generation .............................................................................................................................................. 353 20.5.5 restart............................................................................................................................................................................ 353 20.6 ac specifications................................................................................................................ 355 21. key-on wakeup (kwu) 21.1 configuration....................................................................................................................... 357 21.2 control................................................................................................................................. 358 21.3 functions.............................................................................................................................. 359 22. 10-bit ad converter ( adc) 22.1 configuration....................................................................................................................... 361 22.2 control................................................................................................................................. 362 22.3 functions............................................................................................................................ 366 22.3.1 single mode...................................................................................................................................................................366 22.3.2 repeat mode.................................................................................................................................................................. 366 22.3.3 ad operation disable and forced stop of ad operation.............................................................................................. 367 22.4 register setting.................................................................................................................. 368 22.5 starting stop/idle0/slow modes................................................................................. 368 22.6 analog input voltage and ad conversion result............................................................. 369 viii
22.7 precautions about the ad converter.................................................................................. 370 22.7.1 analog input pin voltage range..................................................................................................................................... 370 22.7.2 analog input pins used as input/output ports ............................................................................................................... 370 22.7.3 noise countermeasure.................................................................................................................................................... 370 23. lcd driver 23.1 configuration....................................................................................................................... 372 23.2 control................................................................................................................................. 373 23.3 low power consumption function.................................................................................... 376 23.4 functions.............................................................................................................................. 377 23.4.1 lcd display control ( lcdcr1)................................................................................................................... 377 23.4.1.1 operation at reset 23.4.1.2 operation in idle0, sleep0 and stop modes 23.4.1.3 operation in slow mode 23.4.1.4 display operation according to the base frequency setting (lcdcr1) (fail-safe) 23.4.1.5 display operation according to the low power consumption register (fail-safe) 23.4.2 lcd drive methods ( lcdcr1)................................................................................................................... 379 23.4.3 frame frequency (lcdcr1) ............................................................................................................................ 380 23.4.4 internal/external bleeder resistance switching control ............................................................................................ 381 23.4.5 low internal bleeder resistance connection time selection ( lcdcr2)................................................... 381 23.4.6 high internal bleeder resistance selection (lcdcr2)..................................................................................384 23.5 lcd display operation....................................................................................................... 385 23.6 display data setting............................................................................................................ 386 23.7 examples of how to control the lcd driver.................................................................. 387 23.7.1 initialization................................................................................................................................................................... 387 23.7.2 display data setting ...................................................................................................................................................... 387 23.7.3 drive output examples................................................................................................................................................. 390 24. flash memory 24.1 flash memory control........................................................................................................ 396 24.2 functions.............................................................................................................................. 399 24.2.1 flash memory command sequence execution ( flscr1).......................................................................... 399 24.2.2 flash memory area switching ( flscr1).................................................................................................... 400 24.2.3 ram area switching ( syscr3)................................................................................................................. 402 24.2.4 bootrom area switching ( flscr1)....................................................................................................... 402 24.2.5 monitoring a ready / busy state of the flash memory ( flscrm)............................................................. 404 24.2.6 port input control register ( spcr)......................................................................................................... 404 24.3 command sequence............................................................................................................ 405 24.3.1 page program................................................................................................................................................................. 407 24.3.2 sector erase ( partial erase in units of a sector)........................................................................................................... 410 24.3.3 chip erase ( all erase).................................................................................................................................................... 410 24.3.4 security program........................................................................................................................................................... 411 24.3.5 security erase ................................................................................................................................................................ 411 24.3.6 product id entry........................................................................................................................................................... 413 24.3.7 product id exit.............................................................................................................................................................. 413 24.4 access to the flash memory area...................................................................................... 414 24.4.1 flash memory control in serial prom mode............................................................................................................... 414 24.4.1.1 how to transfer and write a control program to the ram area in ram loader mode of the serial prom mode 24.4.2 flash memory control in mcu mode........................................................................................................................... 418 24.4.2.1 how to write to the flash memory by transferring a control program to the ram area 24.4.2.2 how to write to the flash memory by using a support program (api) of bootrom 24.4.2.3 how to set the security program by using a support program (api) of bootrom 24.4.2.4 how to rewrite the program itself by using the shadow ram and the support program (api) of the bootrom 24.4.2.5 how to read data from flash memory 24.5 api ( application programming interface).......................................................................... 429 24.5.1 . btwrite........................................................................................................................................................................ 430 24.5.2 . btread......................................................................................................................................................................... 430 24.5.3 . bterasesec................................................................................................................................................................... 431 ix
24.5.4 . bterasechip................................................................................................................................................................. 431 24.5.5 .btgetsp.......................................................................................................................................................................431 24.5.6 .btsetsp ........................................................................................................................................................................431 24.5.7 . bterssp........................................................................................................................................................................ 432 24.5.8 .btconvadr ..................................................................................................................................................................432 24.5.9 . btcalcuart............................................................................................................................................................... 433 24.5.10 . btupdsd................................................................................................................................................................... 434 25. shadow ram 25.1 configuration....................................................................................................................... 437 25.2 control................................................................................................................................. 438 25.3 memory map....................................................................................................................... 440 25.4 functions.............................................................................................................................. 441 25.4.1 copying the flash memory........................................................................................................................................... 441 25.4.2 powering off the flash memory ( sdwcr1).............................................................................................444 25.4.3 shadow ram mapping control in the data area ( sdwcr1)..................................................................... 445 25.4.4 shadow ram mapping control ( sdwcr1)............................................................................................ 445 25.4.5 shadow ram write control in the data area ( sdwcr1)...................................................................... 445 25.4.6 data ram mapping control ( sdwcr1)................................................................................................ 445 26. serial prom mode 26.1 outline................................................................................................................................. 447 26.2 security................................................................................................................................ 447 26.3 serial prom mode setting ............................................................................................... 448 26.3.1 serial prom mode control pins................................................................................................................................... 448 26.4 examples of connections for on-board programming...................................................... 450 26.5 starting in serial prom mode...........................................................................................451 26.6 interface specifications....................................................................................................... 452 26.6.1 sio communication...................................................................................................................................................... 452 26.6.2 uart communication.................................................................................................................................................. 452 26.7 memory mapping................................................................................................................ 454 26.8 operation commands.......................................................................................................... 455 26.8.1 flash memory erase command ( 0xf0).......................................................................................................................... 457 26.8.1.1 specifying the erase area 26.8.2 flash memory write command ( operation command: 0x30)..................................................................................... 460 26.8.3 flash memory read command ( operation command: 0x40)......................................................................................... 462 26.8.4 ram loader command ( operation command: 0x60)....................................................................................................464 26.8.5 flash memory sum output command ( operation command: 0x90)........................................................................... 466 26.8.6 product id code output command ( operation command: 0xc0) ................................................................................. 467 26.8.7 flash memory status output command (0xc3) .............................................................................................................469 26.8.7.1 flash memory status code 26.8.8 flash memory security setting command ( 0xfa)........................................................................................................ 472 26.8.9 clock change command ( operation command: 0xa0)................................................................................................. 474 26.9 error codes..........................................................................................................................475 26.10 checksum ( sum).............................................................................................................. 476 26.10.1 calculation method...................................................................................................................................................... 476 26.10.2 calculation data .......................................................................................................................................................... 476 26.11 intel hex format ( binary).................................................................................................477 26.12 security.............................................................................................................................. 479 26.12.1 password...................................................................................................................................................................... 479 26.12.1.1 how a password can be specified 26.12.1.2 password structure 26.12.1.3 password setting, clearance and authentication 26.12.1.4 password values and setting range 26.12.2 security program.........................................................................................................................................................483 26.12.2.1 how security program works x
26.12.2.2 enabling or disabling security program 26.12.3 option codes ................................................................................................................................................................ 484 26.12.4 recommended settings................................................................................................................................................ 486 26.13 flowchart........................................................................................................................... 487 26.14 ac characteristics ( uart) .............................................................................................. 488 26.14.1 reset timing................................................................................................................................................................. 490 26.14.2 flash memory erase command ( 0xf0)........................................................................................................................ 490 26.14.3 flash memory write command (0x30) ........................................................................................................................ 491 26.14.4 flash memory read command (0x40) ......................................................................................................................... 491 26.14.5 ram loader command (0x60) .................................................................................................................................... 492 26.14.6 flash memory sum output command (0x90) ............................................................................................................ 492 26.14.7 product id code output command (0xc0)..................................................................................................................492 26.14.8 flash memory status output command (0xc3) ........................................................................................................... 493 26.14.9 flash memory security setting command ( 0xfa)...................................................................................................... 493 26.14.10 clock change command ( 0xa0)............................................................................................................................... 493 26.15 ac characteristics ( sio)................................................................................................... 494 26.15.1 sio transfer timing...................................................................................................................................................... 496 26.15.2 reset timing................................................................................................................................................................. 496 26.15.3 flash memory erase command ( 0xf0)........................................................................................................................ 497 26.15.4 flash memory write command (0x30) ........................................................................................................................ 498 26.15.5 flash memory read command (0x40) ......................................................................................................................... 499 26.15.6 ram loader command (0x60) .................................................................................................................................. 500 26.15.7 flash memory sum output command (0x90) ............................................................................................................ 501 26.15.8 product id code output command (0xc0)..................................................................................................................501 26.15.9 flash memory status output command (0xc3) ........................................................................................................... 501 26.15.10 flash memory security setting command ( 0xfa).................................................................................................... 502 27. on-chip debug function ( ocd) 27.1 features................................................................................................................................ 503 27.2 control pins......................................................................................................................... 503 27.3 how to connect the on-chip debug emulator to a target system ...................................505 27.4 security................................................................................................................................ 505 28. input/output circuit 28.1 control pins......................................................................................................................... 507 29. electrical characteristics 29.1 absolute maximum ratings................................................................................................ 509 29.2 operating conditions........................................................................................................... 510 29.2.1 mcu mode (flash programming or erasing)............................................................................................................... 510 29.2.2 mcu mode ( except flash programming or erasing)................................................................................................... 511 29.2.3 serial prom mode....................................................................................................................................................... 512 29.3 dc characteristics .............................................................................................................. 513 29.4 ad conversion characteristics .......................................................................................... 515 29.5 power-on reset circuit characteristics.............................................................................. 516 29.6 voltage detecting circuit characteristics........................................................................... 517 29.7 16-bit timer counter(tcb) characteristics....................................................................... 518 29.8 lcd characteristics............................................................................................................ 518 29.9 ac characteristics............................................................................................................... 519 29.9.1 mcu mode (flash programming or erasing)............................................................................................................... 519 29.9.2 mcu mode ( except flash programming or erasing)................................................................................................... 519 29.9.3 serial prom mode....................................................................................................................................................... 520 xi
29.10 flash characteristics ......................................................................................................... 520 29.10.1 write characteristics.. ..................................................................................................................................................520 29.11 recommended oscillating condition ...............................................................................521 29.12 handling precaution ..........................................................................................................522 30. package dimensions xii
cmos 8-bit microcontroller tmp89fw20a the tmp89fw20a is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 126976 bytes of flash memory. product no. rom (flash) ram package emulation chip TMP89FW20AUG 126976 bytes 3072 bytes lqfp64-p-1010-0.50e - 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c1 series - instruction execution time : 62.5 ns (at 16 mhz) 122 s (at 32.768 khz) - 133 types & 732 basic instructions 2. 30 interrupt sources (external : 5 internal : 25 , except reset) 3. input / output ports (52 pins) - large current output: 7 pins (typ. 10ma) 4. input ports (1) 5. watchdog timer - interrupt or reset can be selected by the program. 6. power-on reset circuit 7. voltage detection circuit 8. divider output function 9. time base timer 10. 16-bit timer counter (tca) : 1 ch - timer, external trigger, event counter, window, pulse width measurement, ppg output modes 11. 16-bit timer counter (tcb) : 1 ch - timer, external trigger, event counter, window, pulse width measurement, ppg output modes 12. 10-bit timer counter (tcc) : 1 ch (2 output pins) - 2ports output ppg (programmed pulse generator) - variable duty output mode - 50%duty output mode - external-triggered start and stop tmp89fw20a page 1 2012/5/18 ra000
- emargency stop pin 13. 8-bit timer counter (tc0) : 4 ch - timer, event counter, pwm, ppg output modes - usable as a 16-bit timer, 12-bit pwm output and 16-bit ppg output by the cascade connection of two channels. 14. real time clock 15. uart : 3ch 16. sio : 1ch note : two sio channels can be used at the same time. 17. i 2 c/sio : 1ch 18. key-on wake-up : 3 ch 19. 10-bit successive approximation type ad converter - analog input : 8ch 20. lcd driver / controller - lcd direct drive capability (32 seg 4 com) - 1/4, 1/3, 1/2 duties or static drive are programmably selectable - internal bleeder resistance for lcd bias voltage (usable as an external bleeder resistance by exter- nal bleeder resistance connection pins) 21. shadow ram 22. on-chip debug function - break/event - trace - ram monitor - flash memory writing 23. internal high-frequency clock oscillation circuit (typ. 10 mhz) system clock is started by internal high frequency after reset. 24. clock operation mode control circuit : 2 circuit single clock mode / dual clock mode 25. low power consumption operation (8 mode) - stop mode: oscillation stops. (battery/capacitor back-up.) - slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) - slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock oscillate.) - idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high frequency clock. released when the reference time set to tbt has elapsed. - idle1 mode: tmp89fw20a 1.1 features page 2 2012/5/18 ra000
the cpu stops, and peripherals operate using high frequency clock. release by interruputs(cpu re- starts). - idle2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruputs. (cpu restarts). - sleep0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using low frequency clock. released when the reference time set to tbt has elapsed. - sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interruput.(cpu restarts). 26. wide operation voltage: 2.7 v to 5.5 v at 16mhz /32.768 khz 1.8 v to 5.5 v at 8 mhz /32.768 khz tmp89fw20a page 3 2012/5/18 ra000
1.2 pin assignment p73 (seg4) p72 (seg5) p71 (seg6) p70 (seg7) p67 (seg8) p66 (seg9) p65 (seg10) p64 (seg11) p63 (seg12) p62 (seg13) p61 (seg14) p60 (seg15) p57 (seg16) p56 (seg17) p55 (seg18) p54 (seg19/sclk0/int3) (seg3) p74 p53 (seg20/si0/rxd0/int2) (seg2) p75 p52 (seg21/so0/txd0/int1) (seg1) p76 p51 (seg22/rxd1/rxd0) (seg0) p77 p50 (seg23/txd1/txd0) com0 p25 (seg24/si1) com1 p24 (seg25/so1/scl0) com2 p23 (seg26/sclk1/sda0) com3 p22 (seg27/sclk0/tcb0/ ppgb0) (rxd2/tca0/tcc0) p90 p21 (seg28/rxd0/si0/ocdio) (txd2/ ppga0/ ppgc01) p91 p20 (seg29/txd0/so0/ocdck) (txd1/ ppgc02) p92 p13 (seg30/lv1) (rxd1/ emg0) p93 p12 (seg31/lv2) (int1/ pwm00/ ppg00/tc00) p94 vlc (int2/ pwm01/ ppg01/tc01) p95 p47 (ain7/ stop/ int5) ( dvo/ pwm02/ ppg02/tc02) p96 p46 (ain6/kwi2) (int3/ pwm03/ ppg03/tc03) p97 p45 (ain5/kwi1/rxd2) vdd (xin) p00 vss (xout) p01 ( reset) p10 (xtin) p02 (xtout) p03 mode avss avdd varef (ain0) p40 (tcb0/ain1) p41 ( ppgb0/ain2) p42 ( int0/ain3) p43 (txd2/kwi0/ain4) p44 figure 1-1 pin assignment tmp89fw20a 1.2 pin assignment page 4 2012/5/18 ra000
1.3 block diagram figure 1-2 block diagram tmp89fw20a page 5 2012/5/18 ra000
1.4 pin names and functions the tmp89fw20a has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin func- tions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions (1/5) pin name input/output functions p03 xtout io o port03 low frequency osc output p02 xtin io i port02 low frequency osc input p01 xout io o port01 high frequency osc output p00 xin io i port00 high frequency osc input p13 seg30 lv1 io o i port13 lcd segment output 30 external bleeder resistance connection pins. p12 seg31 lv2 io o i port12 lcd segment output 31 external bleeder resistance connection pins. p10 reset io i port10 reset signal input p25 seg24 si1 io o i port25 lcd segment output 24 serial data input 1 p24 seg25 so1 scl0 io o o io port24 lcd segment output 25 serial data output 1 i2c bus clock input/output 0 p23 seg26 sclk1 sda0 io o io io port23 lcd segment output 26 serial clock input/output 1 i2c bus data input/output 0 p22 seg27 sclk0 tcb0 ppgb0 io o io i o port22 lcd segment output 27 serial clock input/output 0 tcb0 input ppgb0 output p21 seg28 rxd0 si0 ocdio io o i i io port21 lcd segment output 28 uart data input 0 serial data input 0 ocd data input/output tmp89fw20a 1.4 pin names and functions page 6 2012/5/18 ra000
table 1-2 pin names and functions (2/5) pin name input/output functions p20 seg29 txd0 so0 ocdck io o o o i port20 lcd segment output 29 uart data output 0 serial data output 0 ocd clock input p47 ain7 stop int5 io i i i port47 analog input 7 stop mode release input external interrupt 5 input p46 ain6 kwi2 io i i port46 analog input 6 key-on wake-up input 2 p45 ain5 kwi1 rxd2 io i i i port45 analog input 5 key-on wake-up input 1 uart data input 2 p44 ain4 kwi0 txd2 io i i o port44 analog input 4 key-on wake-up input 0 uart data output 2 p43 ain3 int0 io i i port43 analog input 3 external interrupt 0 input p42 ain2 ppgb0 io i o port42 analog input 2 ppgb0 output p41 ain1 tcb0 io i i port41 analog input 1 tcb0 input p40 ain0 io i port40 analog input 0 p57 seg16 io o port57 lcd segment output 16 p56 seg17 io o port56 lcd segment output 17 p55 seg18 io o port55 lcd segment output 18 p54 seg19 sclk0 int3 io o io i port54 lcd segment output 19 serial clock input/output 0 external interrupt 3 input tmp89fw20a page 7 2012/5/18 ra000
table 1-2 pin names and functions (3/5) pin name input/output functions p53 seg20 si0 rxd0 int2 io o i i i port53 lcd segment output 20 serial data input 0 uart data input 0 external interrupt 2 input p52 seg21 so0 txd0 int1 io o o o i port52 lcd segment output 21 serial data output 0 uart data output 0 external interrupt 1 input p51 seg22 rxd1 rxd0 io o i i port51 lcd segment output 22 uart data input 1 uart data input 0 p50 seg23 txd1 txd0 io o o o port50 lcd segment output 23 uart data output 1 uart data output 0 p67 seg8 io o port67 lcd segment output 8 p66 seg9 io o port66 lcd segment output 9 p65 seg10 io o port65 lcd segment output 10 p64 seg11 io o port64 lcd segment output 11 p63 seg12 io o port63 lcd segment output 12 p62 seg13 io o port62 lcd segment output 13 p61 seg14 io o port61 lcd segment output 14 p60 seg15 io o port60 lcd segment output 15 p77 seg0 io o port77 lcd segment output 0 p76 seg1 io o port76 lcd segment output 1 p75 seg2 io o port75 lcd segment output 2 p74 seg3 io o port74 lcd segment output 3 p73 seg4 io o port73 lcd segment output 4 tmp89fw20a 1.4 pin names and functions page 8 2012/5/18 ra000
table 1-2 pin names and functions (4/5) pin name input/output functions p72 seg5 io o port72 lcd segment output 5 p71 seg6 io o port71 lcd segment output 6 p70 seg7 io o port70 lcd segment output 7 p97 tc03 ppg03 pwm03 int3 io i o o i port97 tc03 input ppg03 output pwm03 output external interrupt 3 input p96 tc02 ppg02 pwm02 dvo io i o o o port96 tc02 input ppg02 output pwm02 output divider output p95 tc01 ppg01 pwm01 int2 io i o o i port95 tc01 input ppg01 output pwm01 output external interrupt 2 input p94 tc00 ppg00 pwm00 int1 io i o o i port94 tc00 input ppg00 output pwm00 output external interrupt 1 input p93 emg0 rxd1 i i i port93 emergency stop input0 uart data input 1 p92 ppgc02 txd1 io o o port92 ppgc02 output uart data output 1 p91 ppgc01 ppga0 txd2 io o o o port91 ppgc01 output ppga0 output uart data output 2 p90 tcc0 tca0 rxd2 io i i i port90 tcc0 input tca0 input uart data input 2 com3 o lcd common output 3 tmp89fw20a page 9 2012/5/18 ra000
table 1-2 pin names and functions (5/5) pin name input/output functions com2 o lcd common output 2 com1 o lcd common output 1 com0 o lcd common output 0 mode i test pin for out-going test (fix to low level). varef i analog reference voltage input pin for a/d conversion. avdd i analog power supply pin. vlc i power supply pin for lcd driver. avss i analog gnd pin vdd i vdd pin vss i gnd pin tmp89fw20a 1.4 pin names and functions page 10 2012/5/18 ra000
2. cpu core 2.1 configuration the cpu core consists of a cpu, a system clock controller and a reset circuit. this chapter describes the cpu core address space, the system clock controller and the reset circuit. 2.2 memory space the 870/c1 cpu memory space consists of a code area to be accessed as instruction operation codes and oper- ands and a data area to be accessed as sources and destinations of transfer and calculation instructions. both the code and data areas have independent 64-kbyte address spaces. 2.2.1 code area the code area stores operation codes, operands, vector tables for vector call instructions and interrupt vec- tor tables. the ram, the bootrom and the flash are mapped in the code area. 0x10000 flash (64 bytes) flash (4096 bytes) flash (64 bytes) 0x1003f 0x10040 ram (3072 bytes) ram (3072 bytes) 0x10c3f flash (65536 bytes) flash (62400 bytes) flash (960 bytes) 0x11000 bootrom (2048 bytes) bootrom (2048 bytes) 0x117ff 0x11800 flash (59392 bytes) flash (59392 bytes) 0x1ffa0 vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) 0x1ffbf 0x1ffc2 interrupt vector ta- ble (62 bytes) interrupt vector ta- ble (62 bytes) interrupt vector ta- ble (62 bytes) interrupt vector ta- ble (62 bytes) 0x1ffff immediately after reset release when the ram is mapped in the code area when the boot- rom is mapped in the code area when the ram and the bootrom are mapped in the code area figure 2-1 memory map in the code area note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. tmp89fw20a page 11 2012/5/18 ra000
2.2.1.1 ram the ram is mapped in the data area immediately after reset release. by setting syscr3 to "1" and writing 0xd4 to syscr4, ram can be mapped to 0x10040to 0x10c3f in the code area to execute the program. at this time, by setting syscr to "1" and writing 0xd4 to syscr4, vector table for vector call instructions and interrupt except reset can be mapped to ram. in the serial prom mode, the ram is mapped to 0x10040 to 0x10c3f in the code area, regardless of the value of syscr3. the program can be executed on the ram using the ram loader function. note1: the contents of the ram become unstable when the power is turned on and immediately after a re- set is released. to execute the program by using the ram, transfer the program to be executed in the initialization routine. system control register 3 syscr3 (0x00fde) 7 6 5 4 3 2 1 0 bit symbol - - - - - rvctr rarea (rstdis) read/write r r r r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 rarea specifies mapping of the ram in the code area 0 : the ram is not mapped from 0x10040 to 0x10c3f in the code area. 1 : the ram is mapped from 0x10040 to 0x10c3f in the code area. rvctr specifies mapping of the vector ta- ble for vector call instructions and interrupts vector table for vector call instruc- tions vector table for interrupt 0 : 0x1ffa0 to 0x1ffbf in the code area 0x1ffc2 to 0x1ffff in the code area 1 : 0x101a0 to 0x101bf in the code area 0x101c2 to 0x101fd in the code area note 1: the value of syscr3 is invalid until 0xd4 is written into syscr4. note 2: to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". note 3: do not set syscr3 to "0" by using the ram loader program. if an interrupt occurs with syscr3 set to "0", the bootrom area is referenced as a vector address and, therefore, the program will not function properly. note 4: bits 7 to 3 of syscr3 are read as "0". system control register 4 syscr4 (0x00fdf) 7 6 5 4 3 2 1 0 bit symbol syscr4 read/write w after reset 0 0 0 0 0 0 0 0 syscr4 writes the syscr3 data control code. 0xb2 : 0xd4 : 0x71 : enables the contents of syscr3. enables the contents of syscr3 and syscr3 . enables the contents of irstsr others : invalid note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit op- eration. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in nor- mal mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpec- ted timing. tmp89fw20a 2. cpu core 2.2 memory space page 12 2012/5/18 ra000
note 3: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. system control status register 4 syssr4 (0x00fdf) 7 6 5 4 3 2 1 0 bit symbol - - - - - rvctrs rareas (rstdis) read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 rareas status of mapping of the ram in the code area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". rvctrs status of mapping of the vector ad- dress in the area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". note:bits 7 to 3 of syssr4 are read as "0". example: program transfer (transfer the program saved in the data area to the ram.) ld hl, transfer_start_address ;destination ram address ld de, program_start_address ;source rom address ld bc, byte_of_program ;number of bytes of the program to be executed -1 trans_ram: ld a, (de) ;reading the program to be transferred ld (hl), a ;writing the program to be transferred inc hl ;destination address increment inc de ;source address increment dec bc ;have all the programs been transferred? j f, code_addr(trans_ram) 2.2.1.2 bootrom the bootrom is not mapped in the code area or the data area after reset release. setting flscr1 to "1" and writing 0xd5 to flscr2 maps the bootrom to 0x11000 to 0x117ff in the code area and to 0x01000 to 0x017ff in the data area. flash memory can be easily pro- grammed by using the api (application programming interface) contained in the bootrom. note 1: when the bootrom is not mapped in the code area, an instruction is fetched from the flash or an swi in- struction is fetched, depending on the capacity of the internal flash. note 2: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. flash memory control register 1 flscr1 (0x00fd0) 7 6 5 4 3 2 1 0 bit symbol (flsmd) barea (farea) (romsel) read/write r/w r/w r/w r/w after reset 0 1 0 0 0 0 0 0 barea specifies mapping of the boot- rom in the code and data areas 0 : the bootrom is not mapped to 0x11000 to 0x117ff in the code area and to 0x01000 to 0x017ff in the data area. 1 : the bootrom is mapped to 0x11000 to 0x117ff in the code area and to 0x01000 to 0x017ff in the data area. tmp89fw20a page 13 2012/5/18 ra000
note:the flash memory control register 1 has a double-buffer structure comprised of the register flscr1 and a shift register. writing "0xd5" to the register flscr2 allows a register setting to be reflected and take effect in the shift register. this means that a register setting value does not take effect until "0xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. flash memory control register 2 flscr2 7 6 5 4 3 2 1 0 (0x00fd1) bit symbol cr1en read/write w after reset * * * * * * * * cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved 2.2.1.3 flash the flash is mapped to 0x10000 to 0x1ffff in the code area after reset release. tmp89fw20a 2. cpu core 2.2 memory space page 14 2012/5/18 ra000
2.2.2 data area the data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. the sfr, the ram, the bootrom and the flash are mapped in the data area. 0x00000 sfr1 (64 bytes) sfr1 (64 bytes) 0x0003f 0x00040 ram (3072 bytes) ram (3072 bytes) 0x00c3f 0xff is read 0xff is read 0x00e40 sfr3 (192 bytes) sfr3 (192 bytes) 0x00eff 0x00f00 sfr2 (256 bytes) sfr2 (256 bytes) 0x00fff 0x01000 bootrom (2048 bytes) 0x017ff 0x01800 flash (61440 bytes) flash (59392 bytes) 0x0ffff immediately after re- set release when the boot- rom is mapped in the data area figure 2-2 memory map in the data area note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. 2.2.2.1 sfr the sfr is mapped to 0x00000 to 0x0003f (sfr1), 0x00f00 to 0x00fff (sfr2) and 0x00e40 to 0x00eff (sfr3) in the data area after reset release. note:don't access the reserved sfr. 2.2.2.2 ram the ram is mapped to 0x00040 to 0x00c3f in the data area after reset release. note:the contents of the ram become unstable when the power is turned on and immediately after a re- set is released. to execute the program by using the ram, transfer the program to be executed in the initialization routine. tmp89fw20a page 15 2012/5/18 ra000
example: ram initialization program ld hl, ram_top_address ;head of address of the ram to be initialized ld a, 0x00 ;initialization data ld bc, byte_of_clear_bytes ;number of bytes of ram to be initialized -1 clr_ram: ld (hl), a ;initialization of the ram inc hl ;initialization address increment dec bc ;have all the rams been initialized? j f, code_addr(clr_ram) 2.2.2.3 bootrom the bootrom is not mapped in the code area or the data area after reset release. setting flscr1 to "1" and writing 0xd5 to flscr2 maps the bootrom to 0x01000 to 0x017ff in the code area and to 0x01000 to 0x017ff in the data area. flash memory can be easily pro- grammed by using the api (application programming interface) contained in the bootrom. note1: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. flash memory control register 1 flscr1 (0x00fd0) 7 6 5 4 3 2 1 0 bit symbol (flsmd) barea (farea) (romsel) read/write r/w r/w r/w r/w after reset 0 1 0 0 0 0 0 0 barea specifies mapping of the boot- rom in the code and data areas 0 : the bootrom is not mapped to 0x11000 to 0x117ff in the code area and to 0x01000 to 0x017ff in the data area. 1 : the bootrom is mapped to 0x11000 to 0x117ff in the code area and to 0x01000 to 0x017ff in the data area. note:the flash memory control register 1 has a double-buffer structure comprised of the register flscr1 and a shift register. writing "0xd5" to the register flscr2 allows a register setting to be reflected and take effect in the shift register. this means that a register setting value does not take effect until "0xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. flash memory control register 2 flscr2 7 6 5 4 3 2 1 0 (0x00fd1) bit symbol cr1en read/write w after reset * * * * * * * * cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved 2.2.2.4 flash the flash is mapped to 0x01000 to 0x0ffff in the data area after reset release. tmp89fw20a 2. cpu core 2.2 memory space page 16 2012/5/18 ra000
2.3 system clock controller 2.3.1 configuration the system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up coun- ter and an operation mode control circuit. figure 2-3 system clock controller 2.3.2 control the system clock controller is controlled by system control register 1 (syscr1), system control register 2 (syscr2), the warm-up counter control register (wuccr), the warm-up counter data register (wucdr) and the clock gear control register (cgcr). tmp89fw20a page 17 2012/5/18 ra000 external high-frequency clock oscillation circuit clock gear ( 1/4, 1/2, 1) warm-up counter fcgck dv9ck fcgcksel oscsel intwuc interrupt request xen/xten/oscen stop system clock oscillation/stop control clock generator xin xout xtin xtout fc fh fosc fs fs/4 1/4 timing generator operation mode control circuit syscr1 tbtcr cgcr 0 1y s syscr2 wuccr wucdr external low-frequency clock oscillation circuit internal bus internal bus internal high-frequency clock oscillation circuit
system control register 1 syscr1 (0x00fdc) 7 6 5 4 3 2 1 0 bit symbol stop relm outen dv9ck oscsel - - - read/write r/w r/w r/w r/w r/w r r r after reset 0 0 0 0 0 0 0 0 stop activates the stop mode 0 : 1 : operate the cpu and the peripheral circuits stop the cpu and the peripheral circuits (activate the stop mode) relm selects the stop mode release method 0 : edge-sensitive release mode (release the stop mode at the rising edge of the stop mode release signal) 1 : level-sensitive release mode (release the stop mode at the "h" level of the stop mode release signal) outen selects the port output state in the stop mode 0 : 1 : high impedance output hold dv9ck selects the input clock to stage 9 of the divider 0 : 1 : fcgck/2 9 fs/4 oscsel selects the high-frequency refer- ence clock (fh) 0 : 1 : internal high-frequency clock (fosc) external high-frequency clock (fc) note 1: fosc: internal high-frequency clock [hz], fc: external high-frequency clock [hz], fcgck: gear clock [hz], fs: external low- frequency clock [hz] note 2: bits 2, 1 and 0 of syscr1 are read as "0". note 3: if the stop mode is activated with syscr1 set at "0", the port internal input is fixed to "0". therefore, an ex- ternal interrupt may be set at the falling edge, depending on the pin state when the stop mode is activated. note 4: the p47 pin is also used as the stop pin. when the stop mode is activated, the pin reverts to high impedance state and is put in input mode, regardless of the state of syscr1. note 5: writing of the second byte data will be executed improperly if the operation is switched to the stop state by an instruc- tion, such as ldw, which executes 2-byte data transfer at a time. note 6: don't set sysck1 to "1" before the oscillation of the external low-frequency clock oscillation circuit be- comes stable. note 7: in the slow1/2 or sleep1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of syscr1< dv9ck >. note 8: syscr1 should be set while syscr2 is "0" (during the normal1 or normal2 mode). writ- ing to syscr1 while syscr2 = "1" (during the slow1 or slow2 mode) has no effect. system control register 2 syscr2 (0x00fdd) 7 6 5 4 3 2 1 0 bit symbol oscen xen xten sysck idle tghalt - - read/write r/w r/w r/w r/w r/w r/w r r after reset 1 0 0 0 0 0 0 0 oscen controls the internal high-frequen- cy clock (fosc) 0 : 1 : stop oscillation continue or start oscillation xen controls the external high-frequen- cy clock (fc) 0 : 1 : stop oscillation continue or start oscillation xten controls the external low-frequen- cy clock (fs) 0 : 1 : stop oscillation continue or start oscillation sysck selects a system clock 0 : 1 : gear clock (fcgck) (normal1/2 or idle1/2 mode) external low-frequency clock (fs/4) (slow1/2 or sleep1 mode) idle cpu and wdt control (idle1/2 or sleep1 mode) 0 : 1 : operate the cpu and the wdt stop the cpu and the wdt (activate idle1/2 or sleep1 mode) tghalt tg control (idle0 or sleep0 mode) 0 : 1 : enable the clock supply from the tg to all the peripheral circuits disable the clock supply from the tg to the peripheral circuits except the tbt (activate idle0 or sleep0 mode) tmp89fw20a 2. cpu core 2.3 system clock controller page 18 2012/5/18 ra000
note 1: fosc: internal high-frequency clock [hz], fc: external high-frequency clock [hz], fcgck: gear clock [hz], fs: external low- frequency clock [hz] note 2: wdt: watchdog timer, tg: timing generator note 3: don't set both syscr2 and syscr2 to "1" simultaneously. note 4: writing of the second byte data will be executed improperly if the operation is switched to the idle state by an instruc- tion, such as ldw, which executes 2-byte data transfer at a time. note 5: when the idle1/2 or sleep1 mode is released, syscr2 is cleared to "0" automatically. note 6: when the idle0 or sleep0 mode is released, syscr2 is cleared to "0" automatically. note 7: bits 1 and 0 of syscr2 are read as "0". note 8: do not set both syscr2 and syscr2 to "1" simultaneously except when switching the high-frequen- cy reference clock (fh). ( when the switching of the reference clock (fh) is complete, one of the two high-frequency clocks not to be used should be stopped.) warm-up counter control register wuccr (0x00fcd) 7 6 5 4 3 2 1 0 bit symbol wucrst - - - wucdiv wucsel read/write w r r r r/w r/w after reset 0 0 0 0 1 1 0 0 wucrst resets and stops the warm-up counter 0 : 1 : - clear and stop the counter wucdiv selects the frequency division of the warm-up counter source clock 00 : 01 : 10 : 11 : source clock source clock / 2 source clock / 2 2 source clock / 2 3 wucsel selects the warm-up counter source clock 00 : 01 : 10 : 11 : select the internal high-frequency clock (fosc) select the external high-frequency clock (fc) select the external low-frequency clock (fs) reserved note 1: fosc : internal high-frequency clock [hz], fc: external high-frequency clock [hz], fcgck: gear clock [hz], fs: external low- frequency clock [hz] note 2: wuccr is cleared to "0" automatically, and need not be cleared to "0" after being set to "1". note 3: bits 7 to 4 of wuccr are read as "0". note 4: before starting the warm-up counter operation, set the source clock and the frequency division rate at wuccr and set the warm-up time at wucdr. warm-up counter data register wucdr (0x00fce) 7 6 5 4 3 2 1 0 bit symbol wucdr read/write r/w after reset 0 1 1 0 0 1 1 0 wucdr warm-up time setting note 1: don't start the warm-up counter operation with wucdr set at "0x00". tmp89fw20a page 19 2012/5/18 ra000
clock gear control register cgcr (0x00fcf) 7 6 5 4 3 2 1 0 bit symbol - - - - - - fcgcksel read/write r r r r r r r/w after reset 0 0 0 0 0 0 0 0 fcgcksel clock gear setting 00 : 01 : 10 : 11 : fcgck = fh / 4 fcgck = fh / 2 fcgck = fh reserved note 1: fh: high-frequency reference clock [hz], fcgck: gear clock [hz] note 2: don't change cgcr in the slow mode. note 3: bits 7 to 2 of cgcr are read as "0". 2.3.3 functions 2.3.3.1 clock generator the clock generator generates the basic clock for the system clocks to be supplied to the cpu core and peripheral circuits. it contains three oscillation circuits: one for the internal high-frequency clock, one for the external high- frequency clock and one for the external low-frequency clock. the oscillation circuit pins are also used as ports p0. for the setting to use them as ports, refer to the chap- ter of i/o ports. to use ports p00 and p01 for the external high-frequency clock oscillation circuit (as the xin and xout pins), set p0fc0 to "1" and then set syscr2 to "1". to use ports p02 and p03 for the external low-frequency clock oscillation circuit (as the xtin and xtout pins), set p0fc2 to "1" and then set syscr2 to "1". the external high-frequency (fc) clock and the external low-frequency (fs) clock can easily be obtained by connecting an oscillator between the xin and xout pins and between the xtin and xtout pins, re- spectively. enabling/disabling the oscillation of the external high-frequency clock oscillation circuit and the exter- nal low-frequency clock oscillation circuit and switching the pin function to ports are controlled by the soft- ware and hardware. the software control is executed by syscr2, syscr2 and the p0 port function con- trol register p0fc. the hardware control is executed by reset release and the operation mode control circuit when the oper- ation is switched to the stop mode as described in "2.3.5 operation mode control circuit". note:no hardware function is available for external direct monitoring of the basic clock. the oscillation fre- quency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog timer disabled and mon- itoring the output. an adjustment program must be created in advance for a system that requires ad- justment of the oscillation frequency. to prevent the dead lock of the cpu core due to the software-controlled enabling/disabling of the oscil- lation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, syscr2 and the p0 port function control register p0fc0. tmp89fw20a 2. cpu core 2.3 system clock controller page 20 2012/5/18 ra000
table 2-1 prohibited combinations of oscillation enable register conditions p0fc0 syscr2 syscr2 syscr1 syscr2 syscr2 state don't care 0 0 dont care 0 dont care all the oscillation circuits are stopped. don't care dont care dont care dont care 0 1 the external low-frequency clock (fs) is selected as the main system clock, but the external low-frequen- cy clock oscillation circuit is stopped. dont care 0 dont care 0 dont care 0 the high-frequency reference clock (fh) is selected as the main system clock, but the internal high-fre- quency clock oscillation circuit (fosc) selected as fh is stopped. dont care dont care 0 1 dont care 0 the high-frequency reference clock (fh) is selected as the main system clock, but the external high-fre- quency clock oscillation circuit (fc) selected as fh is stopped. 0 dont care 1 dont care dont care dont care the external high-frequency clock oscillation circuit (fc) is enabled, but the relevant port pins are set as general-purpose ports. note:it takes a certain period of time after syscr1 and syscr2 are changed be- fore the main system clock is switched. if the currently operating oscillation circuit is stopped be- fore the main system clock is switched, the internal condition becomes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". figure 2-4 examples of oscillator connection (1) high-frequency reference clock (fh) the high-frequency reference clock (fh) is used to operate the tmp89fw20a at high speed. when syscr1 = "1", the external high-frequency clock (fc) is used as the reference clock (fh). when syscr1 = "0", the internal high-frequency clock (fosc) is used as the reference clock (fh). upon reset release, syscr1 is cleared to "0" and the internal high- frequency clock (fosc) is used as the reference clock (fh). when the high-frequency reference clock (fh) is switched, both the external high-frequency clock (fc) and the internal high-frequency clock (fosc) need to be oscillating. to switch the high-frequen- cy reference clock (fh), be sure to follow the steps explained below. in the process of switching the high-frequency reference clock (fh), there is a time when both the external high-frequency clock (fc) and the internal high-frequency clock (fosc) are enabled simultane- ously. mode transitions, as explained in "1.3.5 operation mode control circuit", must not be made in this state. once the reference clock has been switched, be sure to stop either of the high-frequen- cy clocks not to be used. ? switching from fosc to fc with the relevant bits in the p0fc0 register set to "1", set syscr2 to "1" to ena- ble the external high-frequency clock (fc). tmp89fw20a page 21 2012/5/18 ra000 xin high-frequency clock xout xtin low-frequency clock xtout
after making sure that the external high-frequency clock (fc) has achieved stable oscilla- tion by using the warm-up counter, set syscr1 to "1". a maximum of 2/fosc + 2.5/fc [s] after syscr1 is set to "1", the high-frequen- cy reference clock (fh) changes to the external high-frequency clock (fc). after the reference clock (fh) has been switched, wait for at least 2 machine cycles, and then clear syscr2 to "0" to stop the internal high-frequency clock (fosc). if syscr2 is cleared to "0" while the reference clock (fh) is being switched, a sys- tem clock reset is generated. note 1: when the high-frequency reference clock (fh) is switched, the hardware synchronizes the exter- nal high-frequency clock (fc) and the internal high-frequency clock (fosc). while this is done, fh stops for a maximum of 2.5/fc [s]. note 2: after changing syscr1, be sure to wait for at least 2 machine cycles before clear- ing syscr2 to "0". if syscr2 is cleared to "0" without waiting for at least 2 machine cycles, a system clock reset is generated. note 3: syscr1 must be set while syscr2 = "0" (during the normal1 or nor- mal2 mode). writing to syscr1 while syscr2 = "1" (during the slow1 or slow2 mode) has no effect. note 4: setting syscr2 to "1" while p0fc0 = "0" generates a system clock reset. note 5: if syscr2 is set to "1" while syscr2 = "1", the warm-up counter does not start counting the source clock. figure 2-5 switching the high-frequency reference clock (fh) (foscfc) table 2-2 steps for switching the high-frequency reference clock (fh) from fosc to fc step p0fc0 syscr2 syscr2 syscr1 main sys- tem clock state 1 0 1 0 0 fosc the high-frequency reference clock is fosc, and ports p00 and p01 are used as i/o ports. 2 1 1 0 0 fosc ports p00 and p01 are set as oscillation pins. 3 1 1 1 0 fosc the high-frequency clock oscillation circuit is warm- ing up. 4 1 1 1 1 foscfc the high-frequency reference clock is being switch- ed to fc. 5 1 0 1 1 fc the high-frequency reference clock has been switch- ed to fc. note:be sure to follow the above steps when switching the high-frequency reference clock. tmp89fw20a 2. cpu core 2.3 system clock controller page 22 2012/5/18 ra000 external high-frequency clock (fc) internal high-frequency clock (fosc) high-frequency reference clock (fh) syscr1 2.5 / fc (max.)
example: setting ports p00 and p01 as oscillation pins and switching the high-frequency reference clock from fosc to fc (warm-up time: approx. 300 s at fc = 8 mhz) ld (wuccr), 0y00000001 ;wuccr"00" (no division) ;wuccr"01" (selects fc as the source clock) ld (wucdr), 0x26 ;sets the warm-up time ;(determine the time depending on the oscillator characteristics) ;300s / 8 s =37.5 round up to 0x26 set (eirl).4 ;enables intwuc interrupts set (p0fc).0 ;p0fc0"1" (set p00 and p01 as oscillation pins) set (syscr2). 6 ;syscr2"1" ;(starts the external high-frequency clock oscillation and starts the : : ;warm-up counter) pintwuc: set (syscr1). 3 ;syscr1"1" ;(switches the high-frequency reference clock from fosc to fc) nop ;waits for 2 machine cycles nop ;waits for 2 machine cycles clr (syscr2). 7 ;syscr2"0" (stops fosc) reti tmp89fw20a page 23 2012/5/18 ra000
? switching from fc to fosc set syscr1 to "1" to enable the internal high-frequency clock (fosc). after making sure that the internal high-frequency clock (fosc) has achieved stable oscil- lation by using the warm-up counter, clear syscr1 to "0". a maximum of 2/fc + 2.5/fosc [s] after syscr1 is cleared to "0", the high-fre- quency reference clock (fh) changes to the internal high-frequency clock (fosc). after the reference clock (fh) has been switched, wait for at least 2 machine cycles, and then clear syscr2 to "0" to stop the external high-frequency clock (fc). if syscr2 is cleared to "0" while the reference clock (fh) is being switched, a sys- tem clock reset is generated. note 1: when the high-frequency reference clock (fh) is switched, the hardware synchronizes the exter- nal high-frequency clock (fc) and the internal high-frequency clock (fosc). while this is done, fh stops for a maximum of 2.5/fosc [s]. note 2: after changing syscr1, be sure to wait for at least 2 machine cycles before clear- ing syscr2 to "0". if syscr2 is cleared to "0" without waiting for at least 2 ma- chine cycles, a system clock reset is generated. note 3: syscr1 must be set while syscr2 = "0" (during the normal1 or nor- mal2 mode). writing to syscr1 while syscr2 = "1" (during the slow1 or slow2 mode) has no effect. note 4: setting syscr2 to "1" while p0fc0 = "0" generates a system clock reset. note 5: if syscr2 is set to "1" while syscr2 = "1", the warm-up counter does not start counting the source clock. figure 2-6 switching the high-frequency reference clock (fh) (fcfosc) table 2-3 steps for switching the high-frequency reference clock (fh) from fc to fosc step p0fc0 syscr2 syscr2 syscr1 main sys- tem clock state 1 1 0 1 1 fc the high-frequency reference clock is fc. 2 1 1 1 1 fc the high-frequency clock oscillation circuit is warm- ing up. 3 1 1 1 0 fcfosc the high-frequency reference clock is being switch- ed to fosc. 4 1 1 0 0 fosc the high-frequency reference clock has been switch- ed to fosc. note:be sure to follow the above steps when switching the high-frequency reference clock. tmp89fw20a 2. cpu core 2.3 system clock controller page 24 2012/5/18 ra000 2.5 / fosc (max.) external high-frequency clock (fc) internal high-frequency clock (fosc) high-frequency reference clock (fh) syscr1
example: switching the high-frequency reference clock from fc to fosc (warm-up time: approx. 100 s = at fosc = 5 mhz) ld (wuccr), 0y00000000 ;wuccr"00" (no division) ;wuccr"01" (selects fosc as the source clock) ld (wucdr), 0x08 ;sets the warm-up time ;(determine the time depending on the oscillator characteristics) ;100s / 12.8 s = 7.8 round up to 0x08 set (eirl).4 ;enables intwuc interrupts set (syscr2). 7 ;syscr2"1" ;(starts the internal high-frequency clock oscillation and starts the : : warm-up counter) pintwuc: clr (syscr1). 3 syscr1"0" (switches the high-frequency reference clock from fc to fosc) nop waits for 2 machine cycles nop waits for 2 machine cycles clr (syscr2). 6 syscr2"0" (stops fc) reti (2) low-frequency reference clock (fs) the low-frequency reference clock (fs) is used to operate the tmp89fw20a at low speed. pow- er consumption can be reduced. 2.3.3.2 clock gear the clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency ref- erence clock (fh) and inputs it to the timing generator. selects a divided clock at cgcr. two machine cycles are needed after cgcr is changed before the gear clock (fcgck) is changed. the gear clock (fcgck) may be longer than the set clock width, immediately after cgcr is changed. immediately after reset release, the gear clock (fcgck) is set as fh/4, which is obtained by dividing the high-frequency reference clock (fh) by 4. table 2-4 gear clock (fcgck) cgcr fcgck 00 fh / 4 01 fh / 2 10 fh 11 reserved note:don't change cgcr in the slow mode. this may stop the gear clock (fcgck) from be- ing changed. tmp89fw20a page 25 2012/5/18 ra000
2.3.3.3 timing generator the timing generator is a circuit that generates system clocks to be supplied to the cpu core and the pe- ripheral circuits from the gear clock (fcgck) or the clock that is a quarter of the external low-frequency clock (fs). the timing generator has the following functions: 1. generation of the main system clock (fm) 2. generation of clocks for the timer counter, the time base timer and other peripheral circuits figure 2-7 configuration of timing generator (1) configuration of timing generator the timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and a machine cycle counter. 1. main system clock generator this circuit selects the gear clock (fcgck) or the clock that is a quarter of the external low- frequency clock (fs) for the main system clock (fm) to operate the cpu core. clearing syscr2 to "0" selects the gear clock (fcgck). setting it to "1" se- lects the clock that is a quarter of the external low-frequency clock (fs). it takes a certain period of time after syscr2 is changed before the main sys- tem clock is switched. if the currently operating oscillation circuit is stopped before the main system clock is switched, the internal condition becomes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". 2. prescaler and divider these circuits divide fcgck. the divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. when both syscr1 and syscr2 are "0", the input clock to stage 9 of the divider becomes the output of stage 8 of the divider. when syscr1 or syscr2 is "1", the input clock to stage 9 of the divider becomes fs/4. when syscr2 is "1", the outputs of stages 1 to 8 of the divider and prescaler are stopped. the prescaler and divider are cleared to "0" at a reset and at the end of the warm-up oper- ation that follows the release of stop mode. tmp89fw20a 2. cpu core 2.3 system clock controller page 26 2012/5/18 ra000 main system clock generator machine cycle counter syscr2 syscr1 gear clock fcgck prescaler divider multiplexer a timer counter, time base timer and other peripheral circuits divider b s y main system clock fm a quarter of the basic clock for the low-frequency clock
3. machine cycle instruction execution is synchronized with the main system clock (fm). the minimum instruction execution unit is called a "machine cycle". one machine cycle corresponds to one main system clock. there are a total of 11 different types of instructions for the tlcs-870/c1 series: 10 types ranging from 1-cycle instructions, which require one machine cycle for execution, to 10-cycle instructions, which require 10 machine cycles for execution, and 13-cycle instruc- tions, which require 13 machine cycles for execution. 2.3.4 warm-up counter the warm-up counter is a circuit that counts the internal high-frequency clock (fosc), the external high-fre- quency clock (fc) and the external low-frequency clock (fs), and it consists of a source clock selection cir- cuit, a 3-stage frequency division circuit and a 14-stage counter. the warm-up counter is used to secure the time after a power-on reset is released before the supply volt- age becomes stable and secure the time after the stop mode is released or the operation mode is changed be- fore the oscillation by the oscillation circuit becomes stable. figure 2-8 warm-up counter circuit 2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware (1) when a power-on reset is released or a reset is released the warm-up counter serves to secure the time after a power-on reset is released before the sup- ply voltage becomes stable and the time after a reset is released before the oscillation by the high-fre- quency clock oscillation circuit becomes stable. when the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset signal is released. at this time, the cpu and the peripheral circuits are held in the reset state. a reset signal initializes wuccr to "00" and wuccr to "11", which se- lects the internal high-frequency clock (fosc) as the input clock to the warm-up counter. tmp89fw20a page 27 2012/5/18 ra000 s z d c b a s z a b c 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 external high-frequency clock (fc) internal high-frequency clock (fosc) external low-frequency clock (fs) comp- arator wucdr syscr2 syscr1 wuccr enable/disable counting up xen xten stop intwuc interrupt request enable cpu operation wucsel 2 wucdiv wucrst warm-up counter controller oscen 2 2
when a reset is released for the warm-up counter, the internal high-frequency clock (fosc) is in- put to the warm-up counter, and the 14-stage counter starts counting the internal high-frequency clock (fosc). when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and a reset is released for the cpu and the peripheral circuits. wucdr is initialized to 0x66 after reset release, which makes the warm-up time 0x66 2 9 /fosc [s]. note:the clock output from the oscillation circuit is used as the input clock to the warm-up coun- ter. the warm-up time contains errors because the oscillation frequency is unstable until the os- cillation circuit becomes stable. (2) when the stop mode is released the warm-up counter serves to secure the time after the oscillation is enabled by the hardware be- fore the oscillation becomes stable at the release of the stop mode. the clock that was used to generate the main system clock when stop mode was activated is se- lected as the input clock for the frequency division circuit, regardless of wuccr. before the stop mode is activated, select the division rate of the input clock to the warm-up coun- ter at wuccr and set the warm-up time at wucdr. when the stop mode is released, the 14-stage counter starts counting the input clock selected in the frequency division circuit. when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and the operation is restarted by an instruction that follows the stop mode activation instruction. clock that generated the main system clock when the stop mode was activated wuccr wuccr counter input clock warm-up time fosc dont care 00 fosc 2 6 / fosc to 255 2 6 / fosc 01 fosc / 2 2 7 / fosc to 255 2 7 / fosc 10 fosc / 2 2 2 8 / fosc to 255 2 8 / fosc 11 fosc / 2 3 2 9 / fosc to 255 2 9 / fosc fc dont care 00 fc 2 6 / fc to 255 2 6 / fc 01 fc / 2 2 7 / fc to 255 2 6 / fc 10 fc / 2 2 2 8 / fc to 255 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 2 9 / fc fs don't care 00 fs 2 6 / fs to 255 2 6 / fs 01 fs / 2 2 7 / fs to 255 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 2 9 / fs note 1: when the operation is switched to the stop mode during the warm-up for the oscillation enabled by the software, the warm-up counter holds the value at the time, and restarts counting after the stop mode is released. in this case, the warm-up time at the release of the stop mode becomes insufficient. don't switch the operation to the stop mode during the warm-up for the oscillation enabled by the software. note 2: the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time con- tains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. set the sufficient time for the oscillation start property of the oscillator. tmp89fw20a 2. cpu core 2.3 system clock controller page 28 2012/5/18 ra000
2.3.4.2 warm-up counter operation when the oscillation is enabled by the software the warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from normal1 to normal2 or from slow1 to slow2. select the input clock to the frequency division circuit at wuccr. select the input clock to the 14-stage counter at wuccr. after the warm-up time is set at wucdr, setting syscr2, syscr2 or syscr2 to "1" allows the stopped oscillation circuit to start oscillation and the 14-stage coun- ter to start counting the selected input clock. when the upper 8 bits of the counter become equal to wucdr, an intwuc interrupt occurs, count- ing is stopped and the counter is cleared. set wuccr to "1" to discontinue the warm-up operation. by setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and wuccr is cleared to "0". syscr2, syscr2 and syscr2 hold the values when wuccr is set to "1". to restart the warm-up operation, syscr2 or syscr2 must be cleared to "0". note:the warm-up counter starts counting when syscr2, syscr2 or syscr2 is changed from "0" to "1". the counter will not start counting by writing "1" to syscr2 or syscr2 when it is in the state of "1". wuccr wuccr counter input clock warm-up time 00 00 fosc 2 6 / fosc to 255 x 2 6 / fosc 01 fosc / 2 2 7 / fosc to 255 x 2 7 / fosc 10 fosc / 2 2 2 8 / fosc to 255 x 2 8 / fosc 11 fosc / 2 3 2 9 / fosc to 255 x 2 9 / fosc 01 00 fc 2 6 / fc to 255 x 2 6 / fc 01 fc / 2 2 7 / fc to 255 x 2 7 / fc 10 fc / 2 2 2 8 / fc to 255 x 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 x 2 9 / fc 10 00 fs 2 6 / fs to 255 x 2 6 / fs 01 fs / 2 2 7 / fs to 255 x 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 x 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 x 2 9 / fs note:the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors because the oscillation frequency is unstable until the oscillation cir- cuit becomes stable. set the sufficient time for the oscillation start property of the oscillator. 2.3.5 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the internal high-frequency, ex- ternal high-frequency and external low-frequency clocks, and switches the main system clock (fm). there are three operating modes: the single-clock mode, the dual-clock mode and the stop mode. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-9 shows the operating mode transition diagram. tmp89fw20a page 29 2012/5/18 ra000
2.3.5.1 single-clock mode only the gear clock (fcgck) is used for the operation in the single-clock mode. the main system clock (fm) is generated from the gear clock (fcgck). therefore, the machine cycle time is 1/fcgck [s]. the gear clock (fcgck) is generated from the high-frequency reference clock (fh). the high-frequency reference clock (fh) can be selected from the external high-frequency clock (fc) and the internal high-frequency clock (fosc). when the internal high-frequency clock (fosc) is used as the high-frequency reference clock (fh), pins p00 (xin) and p01 (xout) of the external high-frequency clock oscillation circuit can be used as general- purpose i/o ports. before switching the operating mode, be sure to select either the external high-frequency clock (fc) or the internal high-frequency clock (fosc) and then stop either of the high-frequency clocks not to be used. if a mode transition is made with both the external and internal high-frequency clocks enabled, the transi- tion may not be performed properly. for how to switch the high-frequency reference clock (fh), refer to "(1) high-frequency reference clock (fh)". in the single-clock mode, pins p02 (xtin) and p03 (xtout) of the external low-frequency clock oscil- lation circuit can be used as general-purpose i/o ports. (1) normal1 mode in this mode, the cpu core and the peripheral circuits operate using the gear clock (fcgck). after reset release, the normal1 mode becomes active and the internal high-frequency clock (fosc) is used as the high-frequency reference clock (fh). (2) idle1 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). the idle1 mode is activated by setting syscr2 to "1" in the normal1 mode. when the idle1 mode is activated, the cpu and the watchdog timer stop. when the interrupt latch enabled by the interrupt enable register efr becomes "1", the idle1 mode is released to the normal1 mode. when the imf (interrupt master enable flag) is "1" (interrupts enabled), the operation returns nor- mal after the interrupt processing is completed. when the imf is "0" (interrupts disabled), the operation is restarted by the instruction that fol- lows the idle1 mode activation instruction. (3) idle0 mode in this mode, the cpu and the peripheral circuits stop, except the oscillation circuits and the time base timer. in the idle0 mode, the peripheral circuits stop in the states when the idle0 mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the idle0 mode, refer to the section of each peripheral circuit. the idle0 mode is activated by setting syscr2 to "1" in the normal1 mode. tmp89fw20a 2. cpu core 2.3 system clock controller page 30 2012/5/18 ra000
when the idle0 mode is activated, the cpu stops and the timing generator stops the clock sup- ply to the peripheral circuits except the time base timer. when the falling edge of the source clock selected at tbtcr is detected, the idle0 mode is released, the timing generator starts the clock supply to all the peripheral circuits and the nor- mal1 mode is restored. note that the idle0 mode is activated and restarted, regardless of the setting of tbtcr. when the idle0 mode is activated with tbtcr set at "1", the inttbt interrupt latch is set after the normal mode is restored. when the imf is "1" and the ef5 (the individual interrupt enable flag for the time base timer) is "1", the operation returns normal after the interrupt processing is completed. when the imf is "0" or when the imf is "1" and the ef5 (the individual interrupt enable flag for the time base timer) is "0", the operation is restarted by the instruction that follows the idle0 mode activation instruction. 2.3.5.2 dual-clock mode the gear clock (fcgck) and the external low-frequency clock (fs) are used for the operation in the dual- clock mode. the main system clock (fm) is generated from the gear clock (fcgck) in the normal2 or idle2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the slow1/2 or sleep0/1 mode. therefore, the machine cycle time is 1/fcgck [s] in the normal2 or idle2 mode and is 4/fs [s] in the slow1/2 or sleep0/1 mode. pins p02 (xtin) and p03 (xtout) are used for the low-frequency clock oscillation circuit. (these pins cannot be used as i/o ports in the dual-clock mode.) the gear clock (fcgck) is generated from the high-frequency reference clock (fh). the high-frequency reference clock (fh) can be selected from the external high-frequency clock (fc) and the internal high-frequency clock (fosc). when the internal high-frequency clock (fosc) is used as the high-frequency reference clock (fh), pins p00 (xin) and p01(xout) of the external high-frequency clock oscillation circuit can be used as general- purpose i/o ports. before switching the operating mode, be sure to select either the external high-frequency cock (fc) or the internal high-frequency clock (fosc) and then stop either of the high-frequency clocks not to be used. if a mode transition is made with both the external and internal high-frequency clocks enabled, the transi- tion may not be performed properly. for how to switch the high-frequency reference clock (fh), refer to "(1) high-frequency reference clock (fh)". syscr1 cannot be changed when syscr1 is "1". therefore, when switching be- tween the slow1 and slow2 modes, the high-frequency reference clock (fh) must be set in advance in the normal1 or normal2 mode. tlcs-870/c1 series devices start up in the single-clock mode after reset release. to use the dual- clock mode, activate the low-frequency clock by software. (1) normal2 mode in this mode, the cpu core operates using the gear clock (fcgck), and the peripheral circuits oper- ate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). tmp89fw20a page 31 2012/5/18 ra000
(2) slow2 mode in this mode, the cpu core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). in the slow mode, some peripheral circuits become the same as the states when a reset is re- leased. for operations of the peripheral circuits in the slow mode, refer to the section of each periph- eral circuit. set syscr2 to switch the operation mode from normal2 to slow2 or from slow2 to normal2. in the slow2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (3) slow1 mode in this mode, the high-frequency clock oscillation circuit stops operation and the cpu core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). this mode requires less power to operate the high-frequency clock oscillation circuit than in the slow2 mode. in the slow mode, some peripheral circuits become the same as the states when a reset is re- leased. for operations of the peripheral circuits in the slow mode, refer to the section of each periph- eral circuit. set syscr2 to switch the operation between the slow1 and slow2 modes. in the slow1 or sleep1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (4) idle2 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). the idle2 mode can be activated and released in the same way as for the idle1 mode. the oper- ation returns to the normal2 mode after this mode is released. (5) sleep1 mode in this mode, the high-frequency clock oscillation circuit stops operation, the cpu and the watch- dog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequen- cy clock (fs). in the sleep1 mode, some peripheral circuits become the same as the states when a reset is re- leased. for operations of the peripheral circuits in the sleep1 mode, refer to the section of each pe- ripheral circuit. the sleep1 mode can be activated and released in the same way as for the idle1 mode. the op- eration returns to the slow1 mode after this mode is released. in the slow1 or sleep1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (6) sleep0 mode in this mode, the high-frequency clock oscillation circuit stops operation, the time base timer oper- ates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits stop. tmp89fw20a 2. cpu core 2.3 system clock controller page 32 2012/5/18 ra000
in the sleep0 mode, the peripheral circuits stop in the states when the sleep0 mode is activa- ted or become the same as the states when a reset is released. for operations of the peripheral cir- cuits in the sleep0 mode, refer to the section of each peripheral circuit. the sleep0 mode can be activated and released in the same way as for the idle0 mode. the op- eration returns to the slow1 mode after this mode is released. in the sleep0 mode, the cpu stops and the timing generator stops the clock supply to the periph- eral circuits except the time base timer. 2.3.5.3 stop mode in this mode, all the operations in the system, including the oscillation circuits, are stopped and the inter- nal states in effect before the system was stopped are held with low power consumption. in the stop mode, the peripheral circuits stop in the states when the stop mode is activated or be- come the same as the states when a reset is released. for operations of the peripheral circuits in the stop mode, refer to the section of each peripheral circuit. the stop mode is activated by setting syscr1 to "1". the stop mode is released by the stop mode release signals. after the warm-up time has elapsed, the operation returns to the mode that was active before the stop mode, and the operation is restarted by the instruction that follows the stop mode activation instruction. tmp89fw20a page 33 2012/5/18 ra000
2.3.5.4 transition of operation modes note 1: the normal1 and normal2 modes are generically called the normal mode; the slow1 and slow2 modes are called the slow mode; the idle0, idle1 and idle2 modes are called the idle mode; and the sleep0 and sleep1 are called the sleep mode. note 2: the mode is released by the falling edge of the source clock selected at tbtcr. note 3: switching between the internal high-frequency clock and the external high-frequency clock must be done during the normal1 or normal2 mode. for details, refer to "(1) high-frequency reference clock (fh)". figure 2-9 operation mode transition diagram tmp89fw20a 2. cpu core 2.3 system clock controller page 34 2012/5/18 ra000 idle0 mode reset warm-up that follows reset release normal1 mode stop mode normal2 mode slow2 mode slow1 mode idle1 mode idle2 mode sleep1 mode sleep0 mode single-clock mode dual-clock mode syscr2 = "1" syscr2 = "1" syscr1 = ?1? syscr1 = ?1? syscr2 = "1" syscr1 =?1? interrupt interrupt stop mode release signal stop mode release signal stop mode release signal interrupt (note 2) (note 3) (note 3) (note 2) syscr2=?1? syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "1" syscr2 = ?1? reset release warm-up completed syscr2 = "1" or syscr2 = "1" external high-frequency clock operation external high-frequency clock operation internal high-frequency clock operation internal high-frequency clock operation syscr2 = "0" or syscr2 = "0"
table 2-5 operation modes and conditions operation mode oscillation circuit cpu core watchdog timer time base timer ad converter other pe- ripheral cir- cuits machine cy- cle time high- frequency reference clock (fh) low-fre- quency clock (fs) single clock reset oscillation stop reset reset reset reset reset 1 / fcgck [s] normal1 operate operate operate operate operate idle1 stop stop idle0 stop stop stop stop stop ? dual clock normal2 oscillation oscillation operate with the high fre- quency operate with the high / low frequen- cy operate operate operate 1 / fcgck [s] idle2 stop stop slow2 operate with the low fre- quency operate with the low fre- quency stop 4/ fs [s] slow1 stop operate with the low fre- quency operate with the low fre- quency sleep1 stop stop sleep0 stop stop stop stop ? 2.3.6 operation mode control 2.3.6.1 stop mode the stop mode is controlled by system control register 1 (syscr1) and the stop mode release signals. (1) start the stop mode the stop mode is started by setting syscr1 to "1". in the stop mode, the following states are maintained: 1. both the internal (or external) high-frequency and external low-frequency clock oscillation circuits stop oscillation and all internal operations are stopped. 2. the data memory, the registers and the program status word are all held in the states in ef- fect before stop mode was started. the port output latch is determined by the value of syscr1. 3. the prescaler and the divider of the timing generator are cleared to "0". 4. the program counter holds the address of the instruction 2 ahead of the instruction (e.g., [set (syscr1).7]) which started the stop mode. tmp89fw20a page 35 2012/5/18 ra000
(2) release the stop mode the stop mode is released by the following stop mode release signals. it is also released by a re- set by the reset pin, a power-on reset and a reset by the voltage detection circuits. when a reset is released, the warm-up starts. after the warm-up operation and copying of the shadow ram are com- pleted, the normal1 mode becomes active. 1. release by the stop pin 2. release by key-on wakeup 3. release by the voltage detection circuits note:during the stop period (from the start of the stop mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and inter- rupts may be accepted immediately after the stop mode is released. before starting the stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is released, clear unnecessary interrupt latches. 1. release by the stop pin release the stop mode by using the stop pin. the stop mode release by the stop pin includes the level-sensitive release mode and the edge-sensitive release mode, either of which can be selected at syscr1. the stop pin is also used as the p47 port and the int5 (external interrupt input 5) pin. - level-sensitive release mode the stop mode is released by setting the stop pin high. setting syscr1 to "1" selects the level-sensitive release mode. this mode is used for the capacitor backup when the main power supply is cut off and the long term battery backup. even if an instruction for starting the stop mode is executed while the stop pin in- put is high, the stop mode does not start. thus, to start the stop mode in the level-sen- sitive release mode, it is necessary for the program to first confirm that the stop pin input is low. this can be confirmed by testing the port by the software or using interrupts note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was star- ted, regardless of wuccr. example: starting the stop mode from normal mode after testing port. (warm-up time at release of the stop mode is about 300s at fc= 10mhz.) ld (syscr1), 0x40 ;sets up the level-sensitive release mode sstoph: test (p4prd). 7 ;wait until stop pin becomes l level. j f, code_addr(sstoph) ld (wuccr), 0x01 ;wuccr = 00 (no division) (note) ld (wucdr),0x2f ;sets the warm-up time ;300s / 6.4s = 46.9 round up to 0x2f di ;imf = 0 set (syscr1).7 ;starts the stop mode note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. tmp89fw20a 2. cpu core 2.3 system clock controller page 36 2012/5/18 ra000
example: starting the stop mode from the slow mode with an int5 interrupt (warm-up time at release of the stop mode is about 450ms at fs=32.768 khz.) pint5: test (p4prd). 7 ;to reject noise, the stop mode does not start j f, code_addr(sint5) ;if the stop pin input is high. ld (syscr1), 0x40 ;sets up the level-sensitive release mode ld (wuccr), 0x03 ;wuccr = 00 (no division) (note) ld (wucdr),0xe8 ;sets the warm-up time ;450 ms/1.953 ms = 230.4 round up to 0xe8 di ;imf = 0 set (syscr1).7 ;starts the stop mode sint5: reti note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. note: even if the stop pin input returns to low after the warm-up starts, the stop mode is not restarted. figure 2-10 level-sensitive release mode (example when the high-frequency clock oscilla- tion circuit is selected) - edge-sensitive release mode in this mode, the stop mode is released at the rising edge of the stop pin input. setting syscr1 to "0" selects the edge-sensitive release mode. this is used in applications where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power con- sumption oscillator) is input to the stop pin. in the edge-sensitive release mode, the stop mode is started even when the stop pin input is high example: starting the stop mode from the normal mode (warm-up time at release of the stop mode is about 200s at fc=10 mhz.) ld (wuccr),0x01 ;wuccr = 00 (no division) (note) ld (wucdr),0x20 ;sets the warm-up time ;200s / 6.4s = 31.25 round up to 0x20 di ;imf = 0 ld (syscr1) , 0x80 ;starts the stop mode with the edge-sensitive release mode selected note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. tmp89fw20a page 37 2012/5/18 ra000 stop pin xout pin normal mode the stop mode is released by the hardware. normal mode v ih warm-up stop mode confirm by program that the stop pin input is low and start the stop mode. always released if the stop pin input is high.
note: if the rising edge is input to the stop pin within 1 machine cycle after syscr1 is set to "1", the stop mode will not be released. figure 2-11 edge-sensitive release mode (example when the high-frequency clock oscilla- tion circuit is selected) 2. release by the key-on wakeup the stop mode is released by inputting the prescribed level to the key-on wakeup pin. the level to release the stop mode can be selected from "h" and "l". for release by the key-on wakeup, refer to section "key-on wakeup". note: if the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the stop mode is not restarted. 3. release by the voltage detection circuits the stop mode is released by the supply voltage detection by the voltage detection cir- cuits. if the voltage detection operation mode of the voltage detection circuits is set to "gener- ates a voltage detection reset signal", the stop mode is released and a reset is applied as soon as the supply voltage becomes lower than the detection voltage. when the supply voltage becomes equal to or higher than the detection voltage of the volt- age detection circuits, the reset is released and the warm-up starts. after the warm-up is com- pleted, the normal1 mode becomes active. for details, refer to the chapter on the voltage detection circuit. note: if the supply voltage becomes equal to or higher than the detection voltage within 1 ma- chine cycle after syscr1 is set to "1", the stop mode will not be released. (3) stop mode release operation the stop mode is released in the following sequence: 1. oscillation starts. for the oscillation start operation in each mode, refer to "table 2-6 oscil- lation start operation at release of the stop mode". 2. warm-up is executed to secure the time required to stabilize oscillation. the internal opera- tions remain stopped during warm-up. the warm-up time is set by the warm-up counter, de- pending on the oscillator characteristics. 3. after the warm-up time has elapsed, the normal operation is restarted by the instruction that follows the stop mode start instruction. at this time, the prescaler and the divider of the timing generator are cleared to "0". tmp89fw20a 2. cpu core 2.3 system clock controller page 38 2012/5/18 ra000 stop pin xout pin normal mode v ih warm-up stop mode stop mode the stop mode is started by the program. the stop mode is released by the hardware at the rising edge of the stop pin input. normal mode
note:when the stop mode is released with a low hold voltage, the following cautions must be ob- served. the supply voltage must be at the operating voltage level before releasing the stop mode. the reset pin input must also be "h" level, rising together with the supply voltage. in this case, if an external time constant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if the input voltage level of the reset pin drops below the non-invert- ing high-level input voltage (hysteresis input). table 2-6 oscillation start operation at release of the stop mode operation mode before the stop mode is started high-frequency ref- erence clock low-frequency reference clock oscillation start operation after release single-clock mode normal1 internal high-frequency clock - the internal high-frequency clock oscillation circuit starts oscillation. the external high-frequency clock oscillation circuit is inactive. the external low-frequency clock oscillation circuit is inactive. external high-frequency clock - the internal high-frequency clock oscillation circuit is inactive. the external high-frequency clock oscillation circuit starts oscillation. the external low-frequency clock oscillation circuit is inactive. dual-clock mode normal2 internal high-frequency clock external low-frequency clock the internal high-frequency clock oscillation circuit starts oscillation. the external high-frequency clock oscillation circuit is inactive. the external low-frequency clock oscillation circuit starts oscillation. external high-frequency clock external low-frequency clock the internal high-frequency clock oscillation circuit is inactive. the external high-frequency clock oscillation circuit starts oscillation. the external low-frequency clock oscillation circuit starts oscillation. slow1 - external low-frequency clock the internal high-frequency clock oscillation circuit is inactive. the external high-frequency clock oscillation circuit is inactive. the external low-frequency clock oscillation circuit starts oscillation. 2.3.6.2 idle1/2 and sleep1 modes the idle1/2 and sleep1 modes are controlled by the system control register 2 (syscr2) and maska- ble interrupts. the following states are maintained during these modes. 1. the cpu and the watchdog timer stop their operations. the peripheral circuits continue to oper- ate. 2. the data memory, the registers, the program status word and the port output latches are all held in the status in effect before idle1/2 or sleep1 mode was started. 3. the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle1/2 or sleep1 mode. tmp89fw20a page 39 2012/5/18 ra000
figure 2-12 idle1/2 and sleep 1 modes tmp89fw20a 2. cpu core 2.3 system clock controller page 40 2012/5/18 ra000 cpu and wdt stop interrupt processing reset yes no no no no imf = "1" reset input yes yes (interrupt release mode) (normal release mode) interrupt request starting idle1/2 mode or sleep1 mode by an instruction execution of the instruction which follows the idle1/2 mode or sleep1 mode start instruction
(1) start the idle1/2 and sleep1 modes after the interrupt master enable flag (imf) is set to "0", set the individual interrupt enable flag (ef) to "1", which releases idle1/2 and sleep1 modes. to start the idle1/2 or sleep1 mode, set syscr2 to "1". if the release condition is satisfied when it is attempted to start the idle1/2 or sleep1 mode, syscr2 remains cleared and the idle1/2 or sleep1 mode will not be started. note 1: when a watchdog timer interrupt is generated immediately before the idle1/2 or sleep1 mode is started, the watchdog timer interrupt will be processed but the idle1/2 or sleep1 mode will not be started. note 2: before starting the idle1/2 or sleep1 mode, enable the interrupt request signals to be gener- ated to release the idle1/2 or sleep1 mode and set the individual interrupt enable flag. (2) release the idle1/2 and sleep1 modes the idle1/2 and sleep1 modes include a normal release mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf). after releasing idle1/2 or sleep1 mode, syscr2 is automatically cleared to "0" and the operation mode is returned to the mode preceding the idle1/2 or sleep1 mode. the idle1/2 and sleep1 modes are also released by a reset by the reset pin. after releasing the reset, the warm-up starts. after the warm-up operation and copying of the shadow ram are com- pleted, the normal1 mode becomes active. ? normal release mode (imf = "0") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individ- ual interrupt enable flag (ef) is "1". the operation is restarted by the instruction that fol- lows the idle1/2 or sleep1 mode start instruction. normally, the interrupt latch (il) of the interrupt source used for releasing must be cleared to "0" by load instructions. ? interrupt release mode (imf = "1") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individ- ual interrupt enable flag (ef) is "1". after the interrupt is processed, the operation is restar- ted by the instruction that follows the idle1/2 or sleep1 mode start instruction. 2.3.6.3 idle0 and sleep0 modes the idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following states are maintained during the idle0 and sleep0 modes: ? the timing generator stops the clock supply to the peripheral circuits except the time base timer. ? the data memory, the registers, the program status word and the port output latches are all held in the states in effect before the idle0 or sleep0 mode was started. ? the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle0 or sleep0 mode. tmp89fw20a page 41 2012/5/18 ra000
figure 2-13 idle0 and sleep0 modes ? start the idle0 and sleep0 modes stop (disable) the peripherals such as a timer counter. to start the idle0 or sleep0 mode, set syscr2 to "1". ? release the idle0 and sleep0 modes the idle0 and sleep0 modes include a normal release mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf), the individual inter- rupt enable flag (ef5) for the time base timer and tbtcr. after releasing the idle0 or sleep0 mode, syscr2 is automatically cleared to "0" and the opera- tion mode is returned to the mode preceding the idle0 or sleep0 mode. if tbtcr has been set at "1", the inttbt interrupt latch is set. the idle0 and sleep0 modes are also released by a reset by the reset pin. when a re- set is released, the warm-up starts. after the warm-up operation and copying of the shadow ram are completed, the normal1 mode becomes active. tmp89fw20a 2. cpu core 2.3 system clock controller page 42 2012/5/18 ra000 reset yes no no "0" yes yes (interrupt release mode) (normal release mode) yes "1" no no stopping peripherals by instructions cpu and wdt stop interrupt processing reset input tbt source clock falling edge tbtcr tbt interrupt enabled imf = "1" starting idle0 or sleep0 mode by an instruction execution of the instruction which follows the idle0 or sleep0 mode start instruction
(1) normal release mode (imf, ef5, tbtcr = "0") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the idle0 or sleep0 mode is released, the operation is restar- ted by the instruction that follows the idle0 or sleep0 mode start instruction. when tbtcr is "1", the time base timer interrupt latch is set. (2) interrupt release mode (imf, ef5, tbtcr = "1") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the release, the inttbt interrupt processing is started. note 1: the idle0 or sleep0 mode is released to the normal1 or slow1 mode by the asynchro- nous internal clock selected at tbtcr. therefore, the period from the start to the re- lease of the mode may be shorter than the time specified at tbtcr. note 2: when a watchdog timer interrupt is generated immediately before the idle0 or sleep0 mode is started, the watchdog timer interrupt will be processed but the idle0 or sleep0 mode will not be started. 2.3.6.4 slow mode the slow mode is controlled by system control register 2 (syscr2). (1) switching from the normal2 mode to the slow1 mode set syscr2 to "1". when a maximum of 2/fcgck + 10/fs [s] has elapsed since syscr2 is set to "1", the main system clock (fm) is switched to fs/4. after switching, wait for 2 machine cycles or longer, and then clear syscr2 to "0" to turn off the high-frequency clock oscillator. if the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the warm-up counter before implementing the procedure described above. note 1: be sure to follow this procedure to switch the operation from the normal2 mode to the slow1 mode. note 2: it is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to return to normal2 mode. however, be sure to turn off the oscillation of the basic clock for the high-frequency clock when the stop mode is started from the slow mode. note 3: after switching syscr2, be sure to wait for 2 machine cycles or longer before clear- ing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 4: when the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchroniza- tion, fm is stopped for a period of 10/fs or shorter. tmp89fw20a page 43 2012/5/18 ra000
figure 2-14 switching of the main system clock (fm) (switching from fcgck to fs/4) example 1: switching from the normal2 mode to the slow1 mode (when fc is used as the basic clock for the high-fre- quency clock) set (syscr2).4 ;syscr2 = 1 ;(switches the main system clock to the basic clock for the ;low-frequency clock for the slow2 mode) nop ;waits for 2 machine cycles nop clr (syscr2).6 ;syscr2 = 0 ;(turns off the high-frequency clock oscillation circuit) example 2: while operating with the external high-frequency clock, switching to the slow1 mode after the stable oscilla- tion of the external low-frequency clock oscillation circuit is confirmed at the warm-up counter (fs=32.768khz, warm-up time = about 100 ms) ; #### initialize routine #### set (p0fc).2 ;p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x02 ;wuccr = 00 (no division) ;wuccr = 1 (selects fs as the source clock) ld (wucdr), 0x33 ;sets the warm-up time ;(determines the time depending on the oscillator characteristics) ;100 ms/1.95 ms = 51.2 round up to 0x33 set (eirl).4 ;enables intwuc interrupts set (syscr2).5 ;syscr2 = 1 ;(starts the low-frequency clock oscillation and starts the warm-up ;counter) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: set (syscr2).4 ;syscr2 = 1 ;(switches the main system clock to the low-frequency clock) nop ;waits for 2 machine cycles nop clr (syscr2).6 ;syscr2 = 0 ;(turns off the high-frequency clock oscillation circuit) reti | tmp89fw20a 2. cpu core 2.3 system clock controller page 44 2012/5/18 ra000 gear clock (fcgck) when the rising edge of fcgck is detected twice after syscr2 is changed from 0 to 1, f is stopped for synchronization. when the rising edge of fs/4 is detected twice after fm is stopped, fm is switched to fs. quarter of the low-frequency clock (fs/4) main system clock syscr2 10/fs (max.)
vintwuc: dw code_addr(pintwuc) ;intwuc vector table (2) switching from the slow1 mode to the normal1 mode set syscr2 or syscr2 to "1" to enable the high-frequency reference clock (fh). confirm at the warm-up counter that the oscillation of the reference clock for the high-frequen- cy clock has stabilized, and then clear syscr2 to "0". when a maximum of 8/fs + 2.5/fcgck [s] has elapsed since syscr2 is cleared to "0", the main system clock (fm) is switched to fcgck. after switching, wait for 2 machine cycles or longer, and then clear syscr2 to "0" to turn off the external low-frequency clock oscillator. the slow mode is also released by a reset by the reset pin. when a reset is released, the warm- up starts. after the warm-up operation and copying of the shadow ram are completed, the nor- mal1 mode becomes active. note 1: be sure to follow this procedure to switch the operation from the slow1 mode to the nor- mal1 mode. note 2: after switching syscr2, be sure to wait for 2 machine cycles or longer before clear- ing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 3: when the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchroniza- tion, fm is stopped for a period of 2.5/fcgck [s] or shorter. note 4: syscr1 should be set while syscr2 is "0" (during the normal1 or normal 2 mode). writing to syscr1 while syscr2 is "1" (during the slow1 or slow2 mode) has no effect. note 5: when p0fc0 is "0", setting syscr2 to "1" causes a system clock reset. note 6: when syscr2 is set at "1", writing "1" to syscr2 does not cause the warm- up counter to start counting the source clock. figure 2-15 switching the main system clock (fm) (switching from fs/4 to fcgck) example : switching from the slow1 mode to the normal1 mode after the stability of the external high-frequency clock oscillation circuit is confirmed at the warm-up counter (fc = 10 mhz, warm-up time = 4.0 ms) ; #### initialize routine #### set (p0fc).2 ;p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x09 ;wuccr = 10 (divided by 2) ;wuccr = 0 (selects fc as the source clock) ld (wucdr), 0x9d ;sets the warm-up time ;(determine the time depending on the frequency and the oscillator tmp89fw20a page 45 2012/5/18 ra000 gear clock (fcgck) when the rising edge of fs/4 is detected twice after syscr2 is changed from 1 to 0, f is stopped for synchronization. when the rising edge of fcgck is detected twice after fm is stopped, fm is switched to fcgck. quarter of the low-frequency clock (fs/4) main system clock syscr2 2.5/fcgck(max.)
;characteristics) ;4ms / 25.6us = 156.25 round up to 0x9d set (eirl). 4 ;enables intwuc interrupts set (syscr2) .6 ;syscr2 = 1 ;(starts the oscillation of the high-frequency clock oscillation circuit) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: clr (syscr2). 4 ;syscr2 = 0 ;(switches the main system clock to the gear clock) nop ;waits for 2 machine cycles nop clr (syscr2). 5 ;syscr2 = 0 ;(turns off the external low-frequency clock oscillation circuit) reti | vintwuc: dw code_addr(pintwuc) ;intwuc vector table tmp89fw20a 2. cpu core 2.3 system clock controller page 46 2012/5/18 ra000
2.4 reset control circuit the reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 configuration the reset control circuit consists of the following reset signal generation circuits: 1. external reset input (external factor) 2. power-on reset (internal factor) 3. voltage detection reset (internal factor) 4. watchdog timer reset (internal factor) 5. system clock reset (internal factor) figure 2-16 reset control circuit 2.4.2 control the reset control circuit is controlled by system control register 3 (syscr3), system control register 4 (syscr4), system control status register (syssr4) and the internal factor reset detection status register (irstsr). system control register 3 syscr3 (0x00fde) 7 6 5 4 3 2 1 0 bit symbol - - - - - (rvctr) (rarea) rstdis read/write r r r r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note 1: the enabled syscr3 is initialized by a power-on reset only, and cannot be initialized by an external reset input or internal factor reset. the value written in syscr3 is reset by a power-on reset, external reset input or inter- nal factor reset. note 2: the value of syscr3 is invalid until 0xb2 is written into syscr4. note 3: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in nor- mal1 mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpec- ted timing. note 4: bits 7 to 3 of syscr3 are read as "0". note 5: when using the voltage detection circuit, must protect the reset pin from external noise. if the reset pin recogni- zes as an external reset input, the voltage detection circuit will be initialized and the voltage detection reset signal is re- leased. cpu and the peripheral circuit start operation. at this time, if supply voltage is below in the level of recommen- ded voltage, this may cause malfunction. tmp89fw20a page 47 2012/5/18 ra000 p10(reset) internal factor reset detection status register, voltage detection circuit reset signal external reset input enable reset signal warm-up counter reset signal system clock control circuit warm-up counter cpu/peripheral circuits reset signal system clock reset signal watchdog timer reset signal power-on reset signal p10 port voltage detection reset signal
system control register 4 syscr4 (0x00fdf) 7 6 5 4 3 2 1 0 bit symbol syscr4 read/write w after reset 0 0 0 0 0 0 0 0 syscr4 writes the syscr3 data control code. 0xb2 : 0xd4 : 0x71 : others : enables the contents of syscr3 enables the contents of syscr3 and syscr3 enables the contents of irstsr invalid note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit op- eration. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in nor- mal mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpec- ted timing. note 3: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. system control status register 4 syssr4 (0x00fdf) 7 6 5 4 3 2 1 0 bit symbol - - - - - (rvctrs) (rareas) rstdiss read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 note 1: the enabled syscr3 is initialized by a power-on reset only, and cannot be initialized by any other reset sig- nals. the value written in syscr3 is reset by a power-on reset and other reset signals. note 2: bits 7 to 3 of syscr4 are read as "0". tmp89fw20a 2. cpu core 2.4 reset control circuit page 48 2012/5/18 ra000
internal factor reset detection status register irstsr (0x00fcc) 7 6 5 4 3 2 1 0 bit symbol fclr - - - - lvdrf sysrf wdtrf read/write w r r r r r r r after reset 0 0 0 0 0 0 0 0 fclr flag initialization control 0 : 1 : - clears the internal factor reset flag to "0". lvdrf voltage detection reset detection flag 0: 1: - detects the voltage detection reset. sysrf system clock reset detection flag 0 : 1 : - detects the system clock reset. wdtrf watchdog timer reset detection flag 0 : 1 : - detects the watchdog timer reset. sysrf which does not occur may be really set the same time. note that when checking the reset detection flag, check all bits of the reset detection flag to identify which internal factor resets occurred actually. state of flag lvdrf sysrf wdtrf detects the voltage detection reset. 1 * (irregularity) 0 detects the system clock reset. 0 1 0 detects the watchdog timer reset. 0 * (irregularity) 1 note 1: internal reset factor flag (irstsr) is initialized only by a power-on reset, an external re- set input or irstsr . it is not initialized by an internal factor reset. note 2: care must be taken in system designing since the irstsr may not fulfill its functions due to disturbing noise and oth- er effects. note 3: if syscr4 is set to 0x71 after irstsr is set to "1", internal factor reset flag is cleared to "0" and irstsr is automatically cleared to "0". note 4: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. note 5: bit 7 to 3 of irstsr is read as "0". 2.4.3 functions the power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of the clock generator. during reset, the warm-up counter circuit is reset, and the cpu and the peripheral circuits are reset. after reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the warm-up operation that follows reset release. when the warm-up operation and copying of the shadow ram that follow reset release are finished, the cpu starts execution of the program from the reset vector address stored in addresses 0x1fffe to 0x1ffff. when a reset signal is input during the warm-up operation and copying of the shadow ram that follow re- set release, the warm-up counter circuit is reset. the reset operation is common to the power-on reset, external reset input and internal factor resets, except for the initialization of some special function registers and the initialization of the voltage detection circuits. when a reset is applied, the peripheral circuits become the states as shown in table 2-7. tmp89fw20a page 49 2012/5/18 ra000
table 2-7 initialization of built-in hardware by reset operation and its status after release built-in hardware during reset during the warm-up opera- tion that follows reset re- lease immediately after the warm-up operation that fol- lows reset release program counter (pc) mcu mode: 0x1fffe serial prom mode: 0x11ffe mcu mode: 0x1fffe serial prom mode: 0x11ffe mcu mode: 0x1fffe serial prom mode: 0x11ffe stack pointer (sp) 0x000ff 0x000ff 0x000ff ram indeterminate indeterminate indeterminate general-purpose registers (w, a, b, c, d, e, h, l, ix and iy) indeterminate indeterminate indeterminate register bank selector (rbs) 0 0 0 jump status flag (jf) indeterminate indeterminate indeterminate zero flag (zf) indeterminate indeterminate indeterminate carry flag (cf) indeterminate indeterminate indeterminate half carry flag (hf) indeterminate indeterminate indeterminate sign flag (sf) indeterminate indeterminate indeterminate overflow flag (vf) indeterminate indeterminate indeterminate interrupt master enable flag (imf) 0 0 0 individual interrupt enable flag (ef) 0 0 0 interrupt latch (il) 0 0 0 internal high-frequency clock oscillation circuit oscillation enabled oscillation enabled oscillation enabled external high-frequency clock oscillation circuit oscillation disabled oscillation disabled oscillation disabled external low-frequency clock oscillation circuit oscillation disabled oscillation disabled oscillation disabled warm-up counter reset start stop timing generator prescaler and divider 0 0 0 watchdog timer disabled disabled enabled voltage detection circuit disabled or enabled disabled or enabled disabled or enabled i/o port pin status hiz hiz hiz special function register refer to the sfr map. refer to the sfr map. refer to the sfr map. note:the voltage detection circuits are disabled by an external reset input or power-on reset only. tmp89fw20a 2. cpu core 2.4 reset control circuit page 50 2012/5/18 ra000
2.4.4 reset signal generating factors reset signals are generated by each factor as follows: 2.4.4.1 power-on reset the power-on reset is an internal reset that occurs when power is turned on. during power-up, a power-on reset signal is generated while the supply voltage is below the power-on re- set release voltage. when the supply voltage rises above the power-on reset release voltage, the power-on reset signal is released. during power-down, a power-on reset signal is generated when the supply voltage falls below the power- on reset detection voltage. refer to "power-on reset circuit". 2.4.4.2 external reset input ( reset pin input) this is an external reset that is generated by the reset pin input. port p10 is also used as the reset pin, and it is configured as the reset pin at power-up. ? during power-up - when the supply voltage rises rapidly when the power supply rise time (t vdd ) is shorter than 5 [ms] with enough margin, the reset can be released by a power-on reset or an external reset ( reset pin input). the power-on reset logic and external reset ( reset pin input) logic are ored. this means that the tmp89fw20a is reset when either or both of these reset sources are asser- ted. therefore, the reset time is determined by the reset source with a longer reset period. if the reset pin level changes from low to high before the supply voltage rises above the power-on-reset release voltage (v proff ) (or if the reset pin level is high from the beginning), the reset time depends on the power-on reset. if the reset pin level changes from low to high after the supply voltage rises above v proff , the reset time de- pends on the external reset. in the former case, a warm-up period begins when the power-on reset signal is re- leased. in the latter case, a warm-up period begins when the reset pin level becomes high. upon completion of the warm-up period and copying of the shadow ram, the cpu and peripheral circuits start operating (figure 2-17). - when the supply voltage rises slowly when the power supply rise time (t vdd ) is longer than 5 [ms], the reset must be re- leased by using the reset pin. in this case, hold the reset pin low until the supply volt- age rises to the operating voltage range and oscillation is stabilized. when this state is ach- ieved, wait at least 5 [s] and then pull the reset pin high. changing the reset pin lev- el to high starts a warm-up period. upon completion of the warm-up period and copying of the shadow ram, the cpu and peripheral circuits start operating (figure 2-17). tmp89fw20a page 51 2012/5/18 ra000
figure 2-17 external reset input (during power-up) tmp89fw20a 2. cpu core 2.4 reset control circuit page 52 2012/5/18 ra000 operating voltage range v proff t vdd reset pin when the supply voltage rises rapidly (when the reset time depends on external reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff 5 s or more t vdd reset pin warm-up period (t pwup ) when the supply voltage rises slowly cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff t vdd reset pin warm-up period (t pwup ) when the supply voltage rises rapidly (when the reset time depends on power-on reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset shadow ram copy period (t cpy ) warm-up period (t pwup ) shadow ram copy period (t cpy ) shadow ram copy period (t cpy )
? when the supply voltage is within the operating voltage range when the supply voltage is within the operating voltage range and stable oscillation is ach- ieved, holding the reset pin low for 5 [s] or longer generates a reset. then, changing the re- set pin level to high starts a warm-up period. upon completion of the warm-up period and copying of the shadow ram, the cpu and peripheral circuits start operating (figure 2-18). figure 2-18 external reset input (when the power supply is stable) 2.4.4.3 voltage detection reset the voltage detection reset is an internal factor reset that occurs when it is detected that the supply volt- age has reached a predetermined detection voltage. refer to "voltage detection circuit". 2.4.4.4 watchdog timer reset the watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog tim- er is detected. refer to "watchdog timer". 2.4.4.5 system clock reset the system clock reset is an internal factor reset that occurs when it is detected that the oscillation ena- ble register is set to a combination that puts the cpu into deadlock. refer to "clock control circuit". 2.4.4.6 internal factor reset detection status register by reading the internal factor reset detection status register irstsr after the release of an internal fac- tor reset, except the power-on reset, the factor which causes a reset can be detected. sysrf which does not occur may be really set the same time. note that when checking the reset detection flag, check all bits of the reset detection flag to identify which internal factor resets occur- red actually. the internal factor reset detection status register is initialized by an external reset input or power-on re- set. tmp89fw20a page 53 2012/5/18 ra000 operating voltage range reset pin warm-up period (t pwup ) shadow ram copy period (t cpy ) cpu and peripheral circuits start operating cpu and peripheral circuits reset 5 s or more
set irstsr to "1" and write 0x71 to syscr4. this enables irstsr and the inter- nal factor reset detection status register is clear to "0". irstsr is cleared to "0" automatically af- ter initializing the internal factor reset detection status register. note 1: care must be taken in system designing since the irstsr may not fulfill its functions due to disturb- ing noise and other effects. note 2: when setting irstsr is to "1" and writing the enable code (0x71) to syscr4, these opera- tions should be performed consecutively in normal mode with the gear clock (fcgck) as fc/4 (ogcr=00) without switching to a different operating mode. otherwise, irstsr may be enabled at unexpected timing. 2.4.4.7 how to use the external reset input pin as a port to use the external reset input pin as a port, keep the external reset input pin at the "h" level until the pow- er is turned on and the warm-up operation and copying of the shadow ram that follow reset release are fin- ished. after the warm-up operation and copying of the shadow ram that follow reset release are finished, set p1pu0 to "1" and p1cr0 to "0", and connect a pull-up resistor for a port. then set syscr3 to "1" and write 0xb2 to syscr4. this disables the external reset function and makes the external reset input pin usable as a normal port. to use the pin as an external reset pin when it is used as a port, set p1pu0 to "1" and p1cr0 to "0" and connect the pull-up resistor to put the pin to the input mode. then clear syscr3 to "0" and write 0xb2 to syscr4. this enables the external reset function and makes the pin usable as the exter- nal reset input pin. note 1: if you switch the external reset input pin to a port or switch the pin used as a port to the external re- set input pin, do it when the pin is stabilized at the "h" level. switching the pin function when the "l" level is input may cause a reset. note 2: if the external reset input is used as a port, the statement which clears syscr3 to "0" is not written in a program. by the abnormal execution of program, the external reset input set as a port may be changed as the external reset input at unexpected timing. note 3: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal1 mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpected timing. tmp89fw20a 2. cpu core 2.4 reset control circuit page 54 2012/5/18 ra000
3. interrupt control circuit the tmp89fw20a has a total of 30 interrupt sources excluding reset. interrupts can be nested with priorities. three of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and have independent vec- tor addresses. when a request for an interrupt is generated, its interrupt latch is set to "1", which requests the cpu to accept the interrupt. acceptance of interrupts is enabled or disabled by software using the interrupt mas- ter enable flag (imf) and individual enable flag (ef) for each interrupt source. if multiple maskable interrupts are generated simultaneously, the interrupts are accepted in order of descending priority. the priorities are deter- mined by the interrupt priority change control register (ilprs1-ilprs7) as levels and determined by the hard- ware as the basic priorities. however, there are no prioritized interrupt sources among non-maskable interrupts. interrupt sources enable condition interrupt latch vector address (mcu mode) basic priori- ty rvctr=0 enabled rvctr=1 enabled internal/ex- ternal (reset) non-maskable - 0xfffe - 1 internal intswi non-maskable - 0xfffc 0x01fc 2 internal intundef non-maskable - 0xfffc 0x01fc 2 internal intwdt non-maskable ill 0xfff8 0x01f8 2 internal intwuc imf and eirl = 1 ill 0xfff6 0x01f6 5 internal inttbt imf and eirl = 1 ill 0xfff4 0x01f4 6 internal intrxd0 imf and eirl = 1 ill 0xfff2 0x01f2 7 internal inttxd0 imf and eirl = 1 ill 0xfff0 0x01f0 8 external int5 imf and eirh = 1 ilh 0xffee 0x01ee 9 internal intvltd imf and eirh = 1 ilh 0xffec 0x01ec 10 internal intadc imf and eirh = 1 ilh 0xffea 0x01ea 11 internal intrtc imf and eirh = 1 ilh 0xffe8 0x01e8 12 internal inttc00 imf and eirh = 1 ilh 0xffe6 0x01e6 13 internal inttc01 imf and eirh = 1 ilh 0xffe4 0x01e4 14 internal inttca0 imf and eirh = 1 ilh 0xffe2 0x01e2 15 internal intsio0 imf and eirh = 1 ilh 0xffe0 0x01e0 16 external int0 imf and eire = 1 ile 0xffde 0x01de 17 external int1 imf and eire = 1 ile 0xffdc 0x01dc 18 external int2 imf and eire = 1 ile 0xffda 0x01da 19 external int3 imf and eire = 1 ile 0xffd8 0x01d8 20 internal intemg0 imf and eire = 1 ile 0xffd6 0x01d6 21 internal inttcb0 imf and eire = 1 ile 0xffd4 0x01d4 22 internal intrxd1 imf and eire = 1 ile 0xffd2 0x01d2 23 internal inttxd1 imf and eire = 1 ile 0xffd0 0x01d0 24 internal inttc02 imf and eird = 1 ild 0xffce 0x01ce 25 internal inttc03 imf and eird = 1 ild 0xffcc 0x01cc 26 internal intrxd2 imf and eird = 1 ild 0xffca 0x01ca 27 internal inttxd2 imf and eird = 1 ild 0xffc8 0x01c8 28 internal intsio1/intsbi0 imf and eird = 1 ild 0xffc6 0x01c6 29 internal inttcc0p imf and eird = 1 ild 0xffc4 0x01c4 30 internal inttcc0t imf and eird = 1 ild 0xffc2 0x01c2 31 - - - - - - - tmp89fw20a page 55 2012/5/18 ra003
note 1: to use the watchdog timer interrupt (intwdt), clear wdctr to "0" (it is set for the "reset re- quest" after reset is released). for details, see "watchdog timer". note 2: vector address areas can be changed by the syscr3 setting. to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". note 3: 0x1fffa and 0x1fffb function not as interrupt vectors but as option codes in the serial prom mode. for de- tails, see "serial prom mode". note 4: do not set syscr3 to "0" in the serial prom mode. if an interrupt is generated with syscr3 ="0", the software refers to the vector area in the bootrom and the user cannot use it. tmp89fw20a 3. interrupt control circuit page 56 2012/5/18 ra003
3.1 configuration figure 3-1 interrupt control circuit tmp89fw20a page 57 2012/5/18 ra003 s a3 2 1 0 4 b q il 4 il 4 il 5 il 6 il 7 il 8 il 9 il 10 il 11 il 12 il 13 il 14 il 15 il 16 il 17 il 18 il 19 il 20 il 21 r s q imf r internal factor reset en intswi intundef intwdt interrupt source 4 interrupt source 5 interrupt source 6 interrupt source 7 interrupt source 8 interrupt source 9 interrupt source 10 interrupt source 11 interrupt source 12 interrupt source 13 interrupt source 14 interrupt source 15 interrupt source 16 interrupt source 17 interrupt source 18 interrupt source 19 interrupt source 20 decoder vector address generation priority encoder di instruction interrupt accept idle1/2,sleep1/2 mode clear request interrupt request imf (interrupt master enable flag) internal factor reset instruction to write ?0? to imf non-maskable interrupts maskable interrupts maskable interrupt priority change circuit ilprs1 ilprs2 ilprs3 ilprs4 s q il 3 r 5 4 3 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 data bus address bus il 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 [retn] instruction [ret1]1 instruction (only when the imf is set to ?1? before interrupt acceptance) (only when the imf is set to ?1? before interrupt acceptance) [ei] instruction instruction to write ?1? to imf il3 vector read signal il4 clear signal il4 vector read signal reading ilprs7 30 ef 30 to ef 4 il 30 interrupt source30 il 30 to il 4
3.2 interrupt latches (il30 to il3) an interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruc- tion execution interrupt. when an interrupt request is generated, the latch is set to "1", and the cpu is requested to accept the interrupt if its acceptance is enabled. the interrupt latch is cleared to "0" immediately after the inter- rupt is accepted. all interrupt latches are initialized to "0" during reset. the interrupt latches are located at addresses 0x0fe0, 0x0fe1, 0x0fe2, 0x0fe3 in sfr area. each latch can be cleared to "0" individually by an instruction. however, il2 and il3 interrupt latches cannot be cleared by instruc- tions. do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may clear interrupt requests generated while the instruction is executed. interrupt latches cannot be set to "1" by using an instruction. writing "1" to an interrupt latch is equivalent to de- nying clearing of the interrupt latch, and not setting the interrupt latch. since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software. note:in the main program, before manipulating an interrupt latch (il), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the il (en- able interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the il before setting the imf to "1". example 1:clears interrupt latches di ;imf 0 ld (ill), 0y00111111 ;il7 to il6 0 ld (ilh), 0y11101000 ;il12, il10 to il8 0 ei ;imf 1 example 2:reads interrupt latches ld wa, (ill) ;w ilh, a ill example 3:tests interrupt latches test (ill). 7 ;if il7=1 then jump jr f, code_addr(sset) ; tmp89fw20a 3. interrupt control circuit 3.2 interrupt latches (il30 to il3) page 58 2012/5/18 ra003
3.3 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maska- ble interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). non-maskable inter- rupts are accepted regardless of the contents of the eir. the eir consists of the interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these registers are located at addresses 0x003a, 0x003b, 0x003c, 0x003d in the sfr area, and they can be read and writ- ten by instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.3.1 interrupt master enable flag (imf) the interrupt master enable flag (imf) enables and disables the acceptance of all maskable interrupts. clear- ing the imf to "0" disables the acceptance of all maskable interrupts. setting the imf to "1" enables the accept- ance of the interrupts that are specified by the individual interrupt enable flags. when an interrupt is accepted, the imf is stacked and then cleared to "0", which temporarily disables the sub- sequent maskable interrupts. after the interrupt service routine is executed, the stacked data, which was the sta- tus before interrupt acceptance, reloaded on the imf by return interrupt instruction [reti]/[retn]. the imf is located on bit 0 in eirl (address: 0x03a in sfr), and can be read and written by instruc- tions. the imf is normally set and cleared by [ei] and [di] instructions respectively. during reset, the imf is initialized to "0". 3.3.2 individual interrupt enable flags (ef30 to ef4) each of these flags enables and disables the acceptance of its maskable interrupt. setting the correspond- ing bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. during reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are ac- cepted until the flags are set to "1". note:in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master en- able flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after op- erating the ef (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" nor- mally. however, if using multiple interrupt in the interrupt service routine, manipulate the ef before set- ting the imf to "1". example:enables interrupts individually and sets imf di ;imf 0 ldw : (eirl), 0y1110100010100000 ; ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ;imf 1 tmp89fw20a page 59 2012/5/18 ra003
interrupt latch (ill) ill 7 6 5 4 3 2 1 0 (0x00fe0) bit symbol il7 il6 il5 il4 il3 - - - read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 0 0 0 0 function inttxd0 intrxd0 inttbt intwuc intwdt interrupt latch (ilh) ilh 7 6 5 4 3 2 1 0 (0x00fe1) bit symbol il15 il14 il13 il12 il11 il10 il9 il8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function intsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt latch (ile) ile 7 6 5 4 3 2 1 0 (0x00fe2) bit symbol il23 il22 il21 il20 il19 il18 il17 il16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttxd1 intrxd1 inttcb0 intemg0 int3 int2 int1 int0 interrupt latch (ild) ild 7 6 5 4 3 2 1 0 (0x00fe3) bit symbol - il30 il29 il28 il27 il26 il25 il24 read/write r r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttcc0t inttcc0p intsio1/ intsbi0 inttxd2 intrxd2 inttc03 inttc02 il30 to il4 interrupt latch read write 0: no interrupt request clears the interrupt request (notes 2 and 3) 1: interrupt request does not clear the interrupt re- quest (interrupt is not set by writing "1".) il3 0: 1: no interrupt request interrupt request - note 1: il3 is a read-only register. writing the register does not affect interrupt latch. note 2: in the main program, before manipulating an interrupt latch (il), be sure to clear the interrupt master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the il (enable inter- rupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. howev- er, if using multiple interrupt in the interrupt service routine, manipulate the il before setting the imf to "1". note 3: do not clear il with read-modify-write instructions such as bit operations. note 4: when a read instruction is executed on ill, bits 0 to 2 are read as "0". other unused bits are read as "0". tmp89fw20a 3. interrupt control circuit 3.3 interrupt enable register (eir) page 60 2012/5/18 ra003
interrupt enable register (eirl) eirl 7 6 5 4 3 2 1 0 (0x0003a) bit symbol ef7 ef6 ef5 ef4 - - - imf read/write r/w r/w r/w r/w r r r r/w after reset 0 0 0 0 0 0 0 0 function inttxd0 intrxd0 inttbt intwuc interrupt master ena- ble flag interrupt enable register (eirh) eirh 7 6 5 4 3 2 1 0 (0x0003b) bit symbol ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function intsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt enable register (eire) eire 7 6 5 4 3 2 1 0 (0x0003c) bit symbol ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttxd1 intrxd1 inttcb0 intemg0 int3 int2 int1 int0 interrupt enable register (eird) eird 7 6 5 4 3 2 1 0 (0x0003d) bit symbol - ef30 ef29 ef28 ef27 ef26 ef25 ef24 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttcc0t inttcc0p intsio1/ intsbi0 inttxd2 intrxd2 inttc03 inttc02 ef30 to ef4 individual interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts. enables the acceptance of all maskable interrupts. note 1: do not set the imf and the interrupt enable flag (ef15 to ef4) to "1" at the same time. note 2: in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the ef (enable inter- rupt by ei instruction) in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. howev- er, if using multiple interrupt in the interrupt service routine, manipulate the ef before setting the imf to "1". note 3: when a read instruction is executed on eirl, bits 3 to 1 are read as "0". other unused bits are read as "0". tmp89fw20a page 61 2012/5/18 ra003
3.4 maskable interrupt priority change function the priority of maskable interrupts (il4 to il30) can be changed to four levels, levels 0 to 3, regardless of the basic priorities 5 to 31. interrupt priorities can be changed by the interrupt priority change control register (ilprs1 to ilprs7). to raise the interrupt priority, set the level to a larger number. to lower the interrupt prior- ity, set the level to a smaller number. when different maskable interrupts are generated simultaneously at the same level, the interrupt with higher basic priority is processed preferentially. for example, when the ilprs1 reg- ister is set to 0xc0 and interrupts il4 and il7 are generated at the same time, il7 is preferentially processed (pro- vided that ef4 and ef7 have been enabled). after reset is released, all maskable interrupts are set to priority level 0 (the lowest priority). note:in the main program, before manipulating the interrupt priority change control register (ilprs1 to 7), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). set the imf to "1" as required after operating ilprs1 to 7 (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate ilprs1 to 7 before setting the imf to "1". interrupt priority change control register 1 ilprs1 7 6 5 4 3 2 1 0 (0x00ff0) bit symbol il07p il06p il05p il04p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il07p sets the interrupt priority of il7. 00: level 0 (lower priority) il06p sets the interrupt priority of il6. 01: level 1 il05p sets the interrupt priority of il5. 10: level 2 il04p sets the interrupt priority of il4. 11: level 3 (higher priority) interrupt priority change control register 2 ilprs2 7 6 5 4 3 2 1 0 (0x00ff1) bit symbol il11p il10p il09p il08p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il11p sets the interrupt priority of il11. 00: level 0 (lower priority) il10p sets the interrupt priority of il10. 01: level 1 il09p sets the interrupt priority of il9. 10: level 2 il08p sets the interrupt priority of il8. 11: level 3 (higher priority) interrupt priority change control register 3 ilprs3 7 6 5 4 3 2 1 0 (0x00ff2) bit symbol il15p il14p il13p il12p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il15p sets the interrupt priority of il15. 00: level 0 (lower priority) il14p sets the interrupt priority of il14. 01: level 1 il13p sets the interrupt priority of il13. 10: level 2 il12p sets the interrupt priority of il12. 11: level 3 (higher priority) tmp89fw20a 3. interrupt control circuit 3.4 maskable interrupt priority change function page 62 2012/5/18 ra003
interrupt priority change control register 4 ilprs4 7 6 5 4 3 2 1 0 (0x00ff3) bit symbol il19p il18p il17p il16p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il19p sets the interrupt priority of il19. 00: level 0 (lower priority) il18p sets the interrupt priority of il18. 01: level 1 il17p sets the interrupt priority of il17. 10: level 2 il16p sets the interrupt priority of il16. 11: level 3 (higher priority) interrupt priority change control register 5 ilprs5 7 6 5 4 3 2 1 0 (0x00ff4) bit symbol il23p il22p il21p il20p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il23p sets the interrupt priority of il23. 00: level 0 (lower priority) il22p sets the interrupt priority of il22. 01: level 1 il21p sets the interrupt priority of il21. 10: level 2 il20p sets the interrupt priority of il20. 11: level 3 (higher priority) interrupt priority change control register 6 ilprs6 7 6 5 4 3 2 1 0 (0x00ff5) bit symbol il27p il26p il25p il24p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il27p sets the interrupt priority of il27. 00: level 0 (lower priority) il26p sets the interrupt priority of il26. 01: level 1 il25p sets the interrupt priority of il25. 10: level 2 il24p sets the interrupt priority of il24. 11: level 3 (higher priority) interrupt priority change control register 7 ilprs7 7 6 5 4 3 2 1 0 (0x00ff6) bit symbol il30p il29p il28p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 00: level 0 (lower priority) il30p sets the interrupt priority of il30. 01: level 1 il29p sets the interrupt priority of il29. 10: level 2 il28p sets the interrupt priority of il28. 11: level 3 (higher priority) tmp89fw20a page 63 2012/5/18 ra003
3.5 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 8-machine cycles after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [re- ti] (for maskable interrupts) or [retn] (for non-maskable interrupts). 3.5.1 initial setting using an interrupt requires specifying an sp (stack pointer) for it in advance. the sp is a 16-bit register point- ing at the start address of a stack. the sp is post-decremented when a subroutine call or a push instruction is executed or when an interrupt request is accepted. it is pre-incremented when a return or pop instruction is exe- cuted. therefore, the stack becomes deeper toward lower stack location addresses. be sure to reserve a stack area having an appropriate size based on the sp setting. the sp is initialized to 00ffh after a reset. if you need to change the sp, do so right after a reset or when the interrupt master enable flag (imf) is 0. example :sp setting ld sp, 023fh ; sp = 023fh ld sp, sp+04h ; sp = sp + 04h add sp, 0010h ; sp = sp + 0010h 3.5.2 interrupt acceptance processing interrupt acceptance processing is packaged as follows. 1. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any fol- lowing interrupt. 2. the interrupt latch (il) for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (pc) and the program status word, including the interrupt mas- ter enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (sp) is decremented by 3. 4. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of register bank and imf are also saved. example: correspondence between vector table address for inttbt and the entry address of the interrupt service program tmp89fw20a 3. interrupt control circuit 3.5 interrupt sequence page 64 2012/5/18 ra003
figure 3-2 vector table address and entry address tmp89fw20a page 65 2012/5/18 ra003 0x03 0xfff4 0xfff5 vector table address 0xd2 0x0f 0xd203 0xd204 vector table address 0x06
a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt is requested in the interrupt service routine. in order to utilize nested interrupt service, the imf must be set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serv- iced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests. 3.5.3 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, in- cludes imf) are automatically saved on the stack, but the general purpose registers are not. these registers must be saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following methods are used to save/restore the general-purpose registers. 3.5.3.1 using push and pop instructions to save only a specific register, push and pop instructions are available. example :using push and pop instructions pintxx push wa ; save wa register interrupt processing pop wa ; restore wa register reti ; return figure 3-3 saving/restoring general-purpose registers tmp89fw20a 3. interrupt control circuit 3.5 interrupt sequence page 66 2012/5/18 ra003 at acceptance of an interrupt psw sp pc l pc h address (example) b-4 b-3 b-2 b-1 b psw sp pc l pc h at execution of push instruction at execution of pop instruction sp at execution of an reti instruction psw w a sp pc l pc h
3.5.3.2 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register interrupt processing ld a, (gsava) ; restore a register reti ; return figure 3-4 saving/restoring general-purpose registers under interrupt processing 3.5.3.3 using a register bank to save/restore general-purpose registers in non-multiple interrupt handling, the register bank function can be used to save/restore the general-pur- pose registers at a time. the register bank function saves (switches) the general-purpose registers by execut- ing a register bank manipulation instruction (such as ld rbs,1) at the beginning of an interrupt service task. it is unnecessary to re-execute the register bank manipulation instruction at the end of the interrupt serv- ice task because executing the reti instruction makes a return automatically to the register bank that was being used by the main task according to the content of the psw. note:two register banks (bank0 and bank1) are available. each bank consists of 8-bit general-pur- pose registers (w, a, b, c, d, e, h, and l) and 16-bit general-purpose registers (ix and iy). example :saving/restoring registers, using an instruction for transfer with data memory (with the main task using the reg- ister bank bank0) pintxx: ld rbs, 1 ; switches to the register bank bank1 interrupt processing reti ; return (makes a return automatically to bank0 that was being used by the main task when the psw is restored) tmp89fw20a page 67 2012/5/18 ra003 main task interrupt acceptance interrupt service task saving registers restoring registers interrupt return
figure 3-5 saving/restoring general-purpose registers under interrupt processing 3.5.4 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (register bank) are re- stored from tha stack. 2. stack pointer (sp) is incremented by 3. tmp89fw20a 3. interrupt control circuit 3.5 interrupt sequence page 68 2012/5/18 ra003 main task interrupt service task interrupt acceptance interrupt return switching occurs to the register bank bank1. a return is made automatically to the register bank bank0. ld (rbs),1 the register bank bank0 is in use.
3.6 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is the top-priority interrupt). use the swi instruction only for address error detection or for debugging described below. 3.6.1 address error detection 0xff is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address. code 0xff is an swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing 0xff to unused areas in the program memory. 3.6.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting ad- dress. 3.7 undefined instruction interrupt (intundef) when the cpu tries to fetch and execute an instruction that is not defined, intundef is generated and starts the interrupt processing. intundef is accepted even if another non-maskable interrupt is in process. the current process is discontinued and the intundef interrupt process starts soon after it is requested. note:the undefined instruction interrupt (intundef) forces the cpu to jump into the interrupt vector address, as software interrupt (swi) does. tmp89fw20a page 69 2012/5/18 ra003
tmp89fw20a 3. interrupt control circuit 3.7 undefined instruction interrupt (intundef) page 70 2012/5/18 ra003
4. external interrupt control circuit external interrupts detects the change of the input signal and generates an interrupt request. noise can be re- moved by the built-in digital noise canceller. 4.1 configuration the external interrupt control circuit consists of a noise canceller, an edge detection circuit, a level detection cir- cuit and an interrupt signal generation circuit. externally input signals are input to the rising edge or falling edge or level detection circuit for each external in- terrupt, after noise is removed by the noise canceller. figure 4-1 external interrupts 0/5 figure 4-2 external interrupts 1/2/3 figure 4-3 external interrupt 4 4.2 control external interrupts are controlled by the following registers: tmp89fw20a page 71 2012/5/18 ra000 noise canceller intj pin fs/4 fcgck intj interrupt request j=0,5 falling edge detection circuit interrupt request signal generation circuit noise canceller 3 4 2 1 fcgck fs/4 inti pin intilvl inties inti interrupt request i=1 to 3 abcd s z rising edge detection circuit interrupt request signal generation circuit falling edge detection circuit eintcri noise canceller 3 4 2 1 fcgck int4 pin int4lvl int4es int4 interrupt request abcd s z rising edge detection circuit interrupt request signal generation circuit level detection circuit falling edge detection circuit eintcr4 fs
low power consumption register 3 poffcr3 7 6 5 4 3 2 1 0 (0x00f77) bit symbol - - int5en - int3en int2en int1en int0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 int5en int5 control 0 1 disable enable int3en int3 control 0 1 disable enable int2en int2 control 0 1 disable enable int1en int1 control 0 1 disable enable int0en int0 control 0 1 disable enable note 1: clearing intxen(x=0 to 5) to "0" stops the clock supply to the external interrupts. this invalidates the data written in the control register for each external interrupt. when using the external interrupts, set intxen to "1" and then write da- ta into the control register for each external interrupt. note 2: interrupt request signals may be generated when intxen is changed. before changing intxen, clear the correspond- ing interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: bits 7 and 6 of poffset3 are read as "0". external interrupt control register 1 eintcr1 (0x00fd8) 7 6 5 4 3 2 1 0 bit symbol - - - int1lvl int1es int1nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini1lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 1 0 : 1 : initial state or signal level "l" signal level "h" int1es selects the interrupt request gener- ating condition for external inter- rupt 1 00 : an interrupt request is generated at the rising edge of the noise cancel- ler pass signal 01 : an interrupt request is generated at the falling edge of the noise cancel- ler pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int1nc sets the noise canceller sampling interval for external interrupt 1 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to nor- mal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr1 is changed. before doing such operation, clear the correspond- ing interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- tmp89fw20a 4. external interrupt control circuit 4.2 control page 72 2012/5/18 ra000
mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr1 are read as "0". external interrupt control register 2 eintcr1 (0x00fd9) 7 6 5 4 3 2 1 0 bit symbol - - - int2lvl int2es int2nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini2lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 2 0 : 1 : initial state or signal level "l" signal level "h" int2es selects the interrupt request gener- ating condition for external inter- rupt 2 00 : an interrupt request is generated at the rising edge of the noise cancel- ler pass signal 01 : an interrupt request is generated at the falling edge of the noise cancel- ler pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int2nc sets the noise canceller sampling interval for external interrupt 2 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to nor- mal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr2 is changed. before doing such operation, clear the correspond- ing interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr2 are read as "0". tmp89fw20a page 73 2012/5/18 ra000
external interrupt control register 3 eintcr3 (0x00fda) 7 6 5 4 3 2 1 0 bit symbol - - - int3lvl int3es int3nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini3lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 3 0 : 1 : initial state or signal level "l" signal level "h" int3es selects the interrupt request gener- ating condition for external inter- rupt 3 00 : an interrupt request is generated at the rising edge of the noise cancel- ler pass signal 01 : an interrupt request is generated at the falling edge of the noise cancel- ler pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int3nc sets the noise canceller sampling interval for external interrupt 3 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to nor- mal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr3 is changed. before doing such operation, clear the correspond- ing interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr3 are read as "0". tmp89fw20a 4. external interrupt control circuit 4.2 control page 74 2012/5/18 ra000
external interrupt control register 4 eintcr4 (0x00fdb) 7 6 5 4 3 2 1 0 bit symbol - - - int4lvl int4es int4nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini4lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 4 0 : 1 : initial state or signal level "l" signal level "h" int4es selects the interrupt request gener- ating condition for external inter- rupt 4 00 : an interrupt request is generated at the rising edge of the noise cancel- ler pass signal 01 : an interrupt request is generated at the falling edge of the noise cancel- ler pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : an interrupt request is generated at "h" of the noise canceller pass signal int4nc sets the noise canceller sampling interval for external interrupt 4 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to nor- mal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr4 is changed. before doing such operation, clear the correspond- ing interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: the contents of eintcrx are updated each time an interrupt request signal is generated. note 5: bits 7 to 5 of eintcr4 are read as "0". 4.3 function the condition for generating interrupt request signals and the noise cancel time can be set for external inter- rupts 1 to 4. the condition for generating interrupt request signals and the noise cancel time are fixed for external interrupts 0 and 5. tmp89fw20a page 75 2012/5/18 ra000
table 4-1 external interrupts source pin enable conditions interrupt request sig- nal generated at external interrupt pin input signal width and noise removal normal1/2, idle1/2 slow1/2, sleep1 int0 int0 imf and ef16 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/ fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int1 int1 imf and ef17 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int2 int2 imf and ef18 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int3 int3 imf and ef19 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int4 int4 imf and #!unde- fined!# = 1 falling edge rising edge both edges "h" level less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int5 int5 imf and ef8 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/ fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal note 1: fcgck, gear clock [hz]; fs, low frequency clock [hz]; fspl, sampling interval [hz] 4.3.1 low power consumption function external interrupts have a function that saves power by using the low power consumption register (poffcr3) when they are not used. setting poffcr3 to "0" stops (disables) the basic clock for external interrupts and helps save power. note that this makes external interrupts unavailable. setting poffcr3 to "1" supplies (en- ables) the basic clock for external interrupts and makes external interrupts available. after reset, poffcr3 is initialized to "0" and external interrupts become unavailable. when us- ing the external interrupt function for the first time, be sure to set poffcr3 to "1" in the initial set- ting of software (before operating the external interrupt control registers). note:interrupt request signals may be generated when intxen is changed. before changing intxen, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the oper- ation mode is changed and clear the interrupt latch. 4.3.2 external interrupt 0 external interrupt 0 detects the falling edge of the int0 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recog- nized as signals. tmp89fw20a 4. external interrupt control circuit 4.3 function page 76 2012/5/18 ra000
4.3.3 external interrupts 1/2/3 external interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the int1, int2 and int3 pins and generate interrupt request signals. 4.3.3.1 interrupt request signal generating condition detection function select interrupt request signal generating conditions at eintcrx for external interrupts 1/2/3. table 4-2 selection of interrupt request generation edge eintcrx detected at 00 rising edge 01 falling edge 10 both edges 11 reserved note:x=1 to 3 4.3.3.2 a noise canceller pass signal monitoring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcrx. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcrx. note:the contents of eintcrx are updated each time an interrupt request signal is generated. figure 4-4 interrupt request generation and eintcrx 4.3.3.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sam- pling interval selected at eintcrx. if the same level is detected three consecutive times, the sig- nal is recognized as a signal. if not, the signal is removed as noise. tmp89fw20a page 77 2012/5/18 ra000 signal that has passed through the noise canceller inti pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int lvl int lvl int lvl
table 4-3 noise canceller sampling lock eintcrx sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 figure 4-5 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise canceller sampling operation is stopped and an external in- terrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: if noise is input consecutively during sampling of external interrupt pins, the noise cancel function does not work properly. set eintcrx according to the cycle of externally input noise. note 2: if an external interrupt pin is used as an output port, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an interrupt request occurs. to use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during transition of the operation mode. before changing the op- eration mode, clear the corresponding interrupt enable register to "0" to disable the generation of inter- rupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the opera- tion mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] af- ter the operation mode is changed and clear the interrupt latch. 4.3.4 external interrupt 4 external interrupt 4 detects the falling edge, the rising edge, both edges or "h" level of the int4 pin and gen- erates interrupt request signals. 4.3.4.1 interrupt request signal generating condition detection function select an interrupt request signal generating condition at eintcr4 for external interrupt 4. table 4-4 selection of interrupt request generation edge eintcr4 detected at 00 rising edge 01 falling edge 10 both edges 11 "h" level interrupt tmp89fw20a 4. external interrupt control circuit 4.3 function page 78 2012/5/18 ra000 inti pin signal after noise removal i=1 to 3 noise signal
4.3.4.2 a noise canceller pass signal monitoring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcr4. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcr4. figure 4-6 interrupt request generation and eintcr4 4.3.4.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sam- pling interval selected at eintcrx. if the same level is detected three consecutive times, the sig- nal is recognized as a signal. if not, the signal is removed as noise. table 4-5 noise canceller sampling lock eintcr4 sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 tmp89fw20a page 79 2012/5/18 ra000 int4 pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int4lvl int4lvl int4lvl int4lvl interrupt request signal (level detection) signal that has passed through the noise canceller
figure 4-7 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise canceller sampling operation is stopped and an external in- terrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: when noise is input consecutively during sampling external interrupt pins, the noise cancel function does not work properly. set eintcrx according to the cycle of externally input noise. note 2: when an external interrupt pin is used as an output port, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an interrupt request occurs. to use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during transition of the operation mode. before changing the op- eration mode, clear the corresponding interrupt enable register to "0" to disable the generation of inter- rupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the opera- tion mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] af- ter the operation mode is changed and clear the interrupt latch. 4.3.5 external interrupt 5 external interrupt 5 detects the falling edge of the int5 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recog- nized as signals. tmp89fw20a 4. external interrupt control circuit 4.3 function page 80 2012/5/18 ra000 int4 pin signal after noise removal noise signal
5. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request sig- nals or watchdog timer reset signals. note:care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturb- ing noise and other effects. 5.1 configuration figure 5-1 watchdog timer configuration tmp89fw20a page 81 2012/5/18 ra000 source clock watchdog timer interrupt requestl cpu/peripheral circuits reset fcgck/2 10 or fs/2 3 fcgck/2 12 or fs/2 5 fcgck/2 14 or fs/2 7 fcgck/2 16 or fs/2 9 watchdog timer reset signal 2 8 wdctr wdcdr wdcnt wdst overflow clear 2 3 4 6 7 8 5 control code decoder disable control circuit disable code (0xb1) clear code (0x4e) n e t d w w t d w t t d w t u o t d w t s t d w 1 t s t n i w 2 t s t n i w clear time control circuit 8-bit up counter interrupt request/reset signal control circuit r o t c e l e s
5.2 control the watchdog timer is controlled by the watchdog timer control register (wdctr), the watchdog timer control code register (wdcdr), the watchdog timer counter monitor (wdcnt) and the watchdog timer status (wdst). the watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished. watchdog timer control register wdctr (0x00fd4) 7 6 5 4 3 2 1 0 bit symbol - - wdten wdtw wdtt wdtout read/write r r r/w r/w r/w r/w after reset 1 0 1 0 0 1 1 0 wdten enables/disables the watchdog tim- er operation. 0 : 1 : disable enable wdtw sets the clear time of the 8-bit up counter. 00 : the 8-bit up counter is cleared by writing the clear code at any point with- in the overflow time of the 8-bit up counter. 01 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code af- ter the first quarter of the overflow time has elapsed. 10 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first half of the overflow time of the 8-bit up coun- ter. the 8-bit up counter is cleared by writing the clear code after the first half of the overflow time has elapsed. 11 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first three quarters of the overflow time have elapsed. wdtt sets the overflow time of the 8-bit up counter. normal mode slow mode dv9ck=0 dv9ck=1 00 : 2 18 /fcgck 2 11 /fs 2 11 /fs 01: 2 20/ fcgck 2 13 /fs 2 13 /fs 10: 2 22 /fcgck 2 15 /fs 2 15 /fs 11: 2 24 /fcgck 2 17 /fs 2 17 /fs wdtout selects an overflow detection sig- nal of the 8-bit up counter. 0 : 1 : watchdog timer interrupt request signal watchdog timer reset request signal note 1: fcgck, gear clock [hz]; fs, low frequency clock [hz] note 2: wdctr, wdctr and wdctr cannot be changed when wdctr is "1". if wdctr is "1", clear wdctr to "0" and write the disable code (0xb1) into wdcdr to disable the watchdog timer operation. note that wdctr, wdctr and wdctr can be changed at the same time as setting wdctr to "1". note 3: bit 7 and bit 6 of wdctr are read as "1" and "0" respectively. watchdog timer control code register wdcdr (0x00fd5) 7 6 5 4 3 2 1 0 bit symbol wdtcr2 read/write w after reset 0 0 0 0 0 0 0 0 wdtcr2 writes watchdog timer control co- des. 0x4e : clears the watchdog timer. (clear code) 0xb1 : disables the watchdog timer operation and clears the 8-bit up coun- ter when wdctr is "0". (disable code) others : invalid note:wdcdr is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation. tmp89fw20a 5. watchdog timer (wdt) 5.2 control page 82 2012/5/18 ra000
8-bit up counter monitor wdcnt (0x00fd6) 7 6 5 4 3 2 1 0 bit symbol wdcnt read/write r after reset 0 0 0 0 0 0 0 0 wdcnt monitors the count value of the 8- bit up counter the count value of the 8-bit up counter is read. watchdog timer status wdst (0x00fd7) 7 6 5 4 3 2 1 0 bit symbol - - - - - wintst2 wintst1 wdtst read/write r r r r r r r r after reset 0 1 0 1 1 0 0 1 wintst2 watchdog timer interrupt request signal factor status 2 0 : no watchdog timer interrupt request signal has occurred. 1 : a watchdog timer interrupt request signal has occurred due to the over- flow of the 8-bit up counter. wintst1 watchdog timer interrupt request signal factor status 1 0 : no watchdog timer interrupt request signal has occurred. 1 : a watchdog timer interrupt request signal has occurred due to releasing of the 8-bit up counter outside the clear time. wdtst watchdog timer operating state sta- tus 0 : 1 : operation disabled operation enabled note 1: wdst and wdst are cleared to "0" by reading wdst. note 2: values after reset are read from bits 7 to 3 of wdst. tmp89fw20a page 83 2012/5/18 ra000
5.3 functions the watchdog timer can detect the cpu malfunctions and deadlock by detecting the overflow of the 8-bit up coun- ter and detecting releasing of the 8-bit up counter outside the clear time. the watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up counter at random times and comparing the value to the last read value. 5.3.1 setting of enabling/disabling the watchdog timer operation setting wdctr to "1" enables the watchdog timer operation, and the 8-bit up counter starts counting the source clock. wdctr is initialized to "1" after the warm-up operation that follows reset is released. this means that the watchdog timer is enabled. to disable the watchdog timer operation, clear wdctr to "0" and write 0xb1 into wdcdr. dis- abling the watchdog timer operation clears the 8-bit up counter to "0". note:if the overflow of the 8-bit up counter occurs at the same time as 0xb1 (disable code) is written into wdcdr with wdctr set at "1", the watchdog timer operation is disabled preferentially and the overflow detection is not executed. to re-enable the watchdog timer operation, set wdctr to "1". there is no need to write a con- trol code into wdcdr. figure 5-2 wdctr set timing and overflow time note: the 8-bit up counter source clock operates out of synchronization with wdctr. there- fore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get short- er by a maximum of 1 source clock. the 8-bit up counter must be cleared within the period of the over- flow time minus 1 source clock cycle. 5.3.2 setting the clear time of the 8-bit up counter wdctr sets the clear time of the 8-bit up counter. when wdctr is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the 8-bit up counter can be cleared at any time. when wdctr is not "00", the clear time is fixed to only a certain period within the overflow time of the 8-bit up counter. if the operation for releasing the 8-bit up counter is attempted outside the clear time, a watchdog timer interrupt request signal occurs. at this time, the watchdog timer is not cleared but continues counting. if the 8-bit up counter is not cleared within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request sig- nal occurs due to the overflow, depending on the wdctr setting. tmp89fw20a 5. watchdog timer (wdt) 5.3 functions page 84 2012/5/18 ra000 wdctr 0x00 0x01 0xff wdctr 0x00 watchdog timer source clock 8-bit up counter value interrupt request signal 1 clock (max.) overflow time overflow time
figure 5-3 wdctr and the 8-bit up counter clear time 5.3.3 setting the overflow time of the 8-bit up counter wdctr sets the overflow time of the 8-bit up counter. when the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt re- quest signal occurs, depending on the wdctr setting. if the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog counter continues counting, even after the overflow has occurred. the watchdog timer temporarily stops counting up in the stop mode (including warm-up) or in the idle/ sleep mode, and restarts counting up after the stop/idle/sleep mode is released. to prevent the 8-bit up counter from overflowing immediately after the stop/idle/sleep mode is released, it is recommended to clear the 8-bit up counter before the operation mode is changed. table 5-1 watchdog timer overflow time (fcgck=10.0 mhz; fs=32.768 khz) wdtt watchdog timer overflow time [s] normal mode slow mode dv9ck = 0 dv9ck = 1 00 26.21 m 62.50 m 62.50 m 01 104.86 m 250.00 m 250.00 m 10 419.43 m 1.000 1.000 11 1.678 4.000 4.000 note:the 8-bit up counter source clock operates out of synchronization with wdctr. there- fore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get short- er by a maximum of 1 source clock. the 8-bit up counter must be cleared within a period of the over- flow time minus 1 source clock cycle. 5.3.4 setting an overflow detection signal of the 8-bit up counter wdctr selects a signal to be generated when the overflow of the 8-bit up counter is detected. 1. when the watchdog timer interrupt request signal is selected (when wdctr is "0") releasing wdctr to "0" causes a watchdog timer interrupt request signal to occur when the 8-bit up counter overflows. a watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regard- less of the interrupt master enable flag (imf) setting. note: when a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is al- ready accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put tmp89fw20a page 85 2012/5/18 ra000 when wdctr is ?00? 8-bit up counter value when wdctr is ?01? when wdctr is ?10? when wdctr is ?11? 0x40 0x7f 0x80 0xbf 0xc0 0xff 0x00 0xff 0x00 0x01 0x3f clear time clear time outside the clear time clear time outside the clear time clear time outside the clear time
on hold. therefore, if watchdog timer interrupts are generated continuously without execution of the retn in- struction, too many levels of nesting may cause a malfunction of the microcontroller. 2. when the watchdog timer reset request signal is selected (when wdctr is "1") setting wdctr to "1" causes a watchdog timer reset request signal to occur when the 8-bit up counter overflows. this watchdog timer reset request signal resets the tmp89fw20a and starts the warm-up opera- tion. 5.3.5 writing the watchdog timer control codes the watchdog timer control codes are written into wdcdr. by writing 0x4e (clear code) into wdcdr, the 8-bit up counter is cleared to "0" and continues counting the source clock. when wdctr is "0", writing 0xb1 (disable code) into wdcdr disables the watchdog timer op- eration. to prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the over- flow time of the 8-bit up counter and within the clear time. by designing the program so that no overflow will occur, the program malfunctions and deadlock can be de- tected through interrupts generated by watchdog timer interrupt request signals. by applying a reset to the microcomputer using watchdog timer reset request signals, the cpu can be re- stored from malfunctions and deadlock. example: when wdctr is "0", set the watchdog timer detection time to 2 20 /fcgck [s], set the counter clear time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is detected. ld (wdctr), 0y00110011 ;wdtw10, wdtt01, wdtout1 clear the 8-bit up counter at a point after half of its overflow time and within a peri- od of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ;clear the 8-bit up counter clear the 8-bit up counter at a point after half of its overflow time and within a peri- od of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ;clear the 8-bit up counter note:if the overflow of the 8-bit up counter and writing of 0x4e (clear code) into wdcdr occur simultaneous- ly, the 8-bit up counter is cleared preferentially and the overflow detection is not executed. 5.3.6 reading the 8-bit up counter the counter value of the 8-bit up counter can be read by reading wdcnt. the stoppage of the 8-bit up counter can be detected by reading wdcnt at random times and comparing the value to the last read value. 5.3.7 reading the watchdog timer status the watchdog timer status can be read at wdst. wdst is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when the watchdog timer operation is disabled. tmp89fw20a 5. watchdog timer (wdt) 5.3 functions page 86 2012/5/18 ra000
wdst is set to "1" when a watchdog timer interrupt request signal occurs due to the over- flow of the 8-bit up counter. wdst is set to "1" when a watchdog timer interrupt request signal occurs due to the opera- tion for releasing the 8-bit up counter outside the clear time. you can know which factor has caused a watchdog timer interrupt request signal by reading wdst and wdst in the watchdog timer interrupt service routine. wdst and wdst are cleared to "0" when wdst is read. if wdst is read at the same time as the condition for turning wdst or wdst to "1" is satisfied, wdst or wdst is set to "1", rather than being cleared. figure 5-4 changes in the watchdog timer status tmp89fw20a page 87 2012/5/18 ra000 8-bit up counter value when wdctr is ?10? writing of 4eh (clear code) wdst watchdog timer interrupt request signal interrupt request signal generated by clearing the 8-bit up counter outside the clear time interrupt request signal generated by the overflow of the 8-bit up counter 0x40 0x01 0x7f 0x80 0xbf 0xc0 0xff 0x00 0xff 0x00 0x01 0x3f clear time outside the clear time reading of wdst wdst
tmp89fw20a 5. watchdog timer (wdt) 5.3 functions page 88 2012/5/18 ra000
6. power-on reset circuit the power-on reset circuit generates a reset when the power is turned on. when the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 configuration the power-on reset circuit consists of a reference voltage generation circuit and a comparator. the supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage gen- eration circuit by the comparator. figure 6-1 power-on reset circuit 6.2 function when power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a power-on reset signal is generated and if it is higher than the releasing voltage of the power- on reset circuit, a power-on reset signal is released. until the power-on reset signal is generated, a warm-up circuit and a cpu is reset. when the power-on reset signal is released, the warm-up circuit is activated. the reset of the cpu and peripher- al circuits is released after the warm-up time that follows reset release has elapsed. increase the supply voltage into the operating range during the period from detection of the power-on reset re- lease voltage until the end of the warm-up time that follows reset release. if the supply voltage has not reached the operating range by the end of the warm-up time that follows reset release, the tmp89fw20a cannot operate properly. for voltage drop detection, use the voltage detection circuit. for details, refer to the chapter on the voltage detec- tion circuit. tmp89fw20a page 89 2012/5/18 ra000 vdd power-on reset signal comparator reference voltage generation circuit
note 1: the power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (vdd). refer to the electrical characteristics and take them into consideration when designing equipment. note 2: for the ac timing, refer to the electrical characteristics. figure 6-2 operation timing of power-on reset tmp89fw20a 6. power-on reset circuit 6.2 function page 90 2012/5/18 ra000 t pwup t vdd v proff supply voltage (vdd) operating voltage power-on reset signal warm-up counter start shadow ram copy start warm-up counter clock cpu/peripheral circuits reset signal t cpy
7. voltage detection circuit the voltage detection circuit detects any decrease in the supply voltage and generates intvltd interrupt re- quest signals and voltage detection reset signals. note:the voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (vdd). refer to the electrical characteristics and take them into consideration when designing equipment. 7.1 configuration the voltage detection circuit consists of a reference voltage generation circuit, a detection voltage level selec- tion circuit, a comparator and control registers. the supply voltage (vdd) is divided by the ladder resistor and input to the detection voltage selection circuit. the detection voltage selection circuit selects a voltage according to the specified detection voltage (vdlvl), and the comparator compares it with the reference voltage. when the comparator detects the selected voltage, a volt- age detection reset signal or an intvltd interrupt request signal can be generated. whether to generate a voltage detection reset signal or an intvltd interrupt request signal can be program- med by software. in the former case, a voltage detection reset signal is generated when the supply voltage (vdd) becomes lower than the detection voltage (vdlvl). in the latter case, an intvltd interrupt request signal is gen- erated when the supply voltage (vdd) falls to the detection voltage level. note:since the comparators used for voltage detection do not have a hysteresis structure, intvltd interrupt re- quest signals may be generated frequently if the supply voltage (vdd) is close to the detection voltage (vdxlvl). intvltd interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. figure 7-1 voltage detection circuit tmp89fw20a page 91 2012/5/18 rb000 vdd vden vdmod vdlvl vdsf vdf vdcr2 vdcr1 voltage detection reset signal intvltd interrupt request signal f/f internal bus detection voltage level selection circuit reference voltage generation circuit interrupt request signal generation circuit ? +
7.2 control the voltage detection circuit is controlled by voltage detection control registers 1 and 2. voltage detection control register 1 vdcr1 (0x00fc6) 7 6 5 4 3 2 1 0 bit symbol "0" "0" "0" vd1f vd1sf vd1lvl read/write r/w r r/w r/w r/w read only r/w after reset 0 0 1 0 0 0 0 0 vdf voltage detection flag (retains the state when vdd < vdlvl is detec- ted) read write 0: 1: vdd vdlvl vdd < vdlvl clears vdf to "0" - vdsf voltage detection status flag (mag- nitude relation of vdd and vdlvl when they are read) 0: 1: vdd vdlvl vdd < vdlvl vdlvl selection for detection voltage 00: 01: 10: 11: 2.00 +0.15 / -0.15v 2.20 +0.15 / -0.15v 2.85 +0.15 / -0.15v 4.50 +0.20 / -0.20v note 1: vdcr1 is initialized by a power-on reset or an external reset input. note 2: when vdf is cleared by the software and is set due to voltage detection at the same time, the setting due to voltage detection is given priority. note 3: vdf cannot be programmed to "1" by the software. note 4: bit 7, 5 and 4 of vdcr1 should be cleared to "0". voltage detection control register 2 vdcr2 (0x00fc7) 7 6 5 4 3 2 1 0 bit symbol - - "0" "0" "0" "0" vd1mod vd1en read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 vdmod selects the operation mode of volt- age detection 0: 1: generates an intvltd interrupt request signal generates a voltage detection reset signal vden enables/disables the operation of voltage detection 0: 1: disables the operation of voltage detection enables the operation of voltage detection note 1: vdcr2 is initialized by a power-on reset or an external reset input. note 2: bits 7 and 6 of vdcr2 are read as "0". note 3: bit 5 and 2 of vdcr2 should be cleared to "0". tmp89fw20a 7. voltage detection circuit 7.2 control page 92 2012/5/18 rb000
7.3 function two detection voltage can be set in the voltage detection circuit. enabling/disabling the voltage detection and the operation to be executed when the supply voltage (vdd) falls to or below the detection voltage (vdlvl) can be programmed. 7.3.1 enabling/disabling the voltage detection operation setting vdcr2 to "1" enables the voltage detection operation. setting it to "0" disables the opera- tion. vdcr2 is cleared to "0" immediately after a power-on reset or a reset by an external reset input is released. note:when the supply voltage (vdd) is lower than the detection voltage (vdlvl), setting vdcr2 to "1" generates an intvltd interrupt request signal or a voltage detection reset sig- nal at the time. 7.3.2 selecting the voltage detection operation mode when vdcr2 is set to "0", the voltage detection operation mode is set to generate intvltd interrupt request signals. when vdcr2 is set to "1", the operation mode is set to gen- erate voltage detection reset signals. ? when the operation mode is set to generate intvltd interrupt signals (vdcr2="0") when vdcr2="1", an intvltd interrupt request signal is generated when the sup- ply voltage (vdd) falls to the detection voltage (vdxlvl). figure 7-2 voltage detection interrupt request note1: since the comparators used for voltage detection do not have a hysteresis structure, intvltd interrupt re- quest signals may be generated frequently when the supply voltage (vdd) is close to the detection volt- age (vdxlvl). intvltd interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. note2: if the supply voltage (vdd) falls to the detection voltage (vdxlvl) during idle0 or sleep0 mode, an intvltd interrupt request signal is generated after the tbt counts the specified period and idle0 or sleep mode is released. in the case of stop mode, an intlvtd interrupt request signal is generated after stop mode is released by the stop pin. ? when the operation mode is set to generate voltage detection reset signals (vdcr2="1") when vdcr2 = "1", a voltage detection reset signal is generated when the supply volt- age (vdd) becomes lower than the detection voltage (vdxlvl). vdcr1 and vdcr2 are initialized by a power-on reset or an external reset input only. a volt- age detection reset signal is generated continuously as long as the supply voltage (vdd) is lower than the detection voltage (vdxlvl). tmp89fw20a page 93 2012/5/18 rb000 detection voltage level vdd level intvltd interruptrequest signal (note1) vdcr2 (note1)
figure 7-3 voltage detection reset signal 7.3.3 selecting the detection voltage level select a detection voltage at vdcr1. 7.3.4 voltage detection flag and voltage detection status flag the magnitude relation between the supply voltage (vdd) and the detection voltage (vdlvl) can be checked by reading vdcr1 and vdcr1. if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection volt- age (vdlvl), vdcr1 is set to "1" and is held in this state. vdcr1 is not cleared to "0" when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdlvl). when vdcr2 is cleared to "0" after vdcr1 is set to "1", the previous state is still held. to clear vdcr1, "0" must be written to it. if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection volt- age (vdlvl), vdcr1 is set to "1". when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdlvl), vdcr1 is cleared to "0". unlike vdcr1, vdcr1 does not hold the set state. note 1: when the supply voltage (vdd) becomes lower than the detection voltage (vdlvl) in the stop, idle0 or sleep0 mode, the voltage detection flag and the voltage detection status flag are changed after the op- eration mode is returned to normal or slow mode. note 2: depending on the voltage detection timing, the voltage detection status flag (vdsf) may be changed ear- lier than the voltage detection flag (vdf) by a maximum of 2/fcgck[s]. tmp89fw20a 7. voltage detection circuit 7.3 function page 94 2012/5/18 rb000 detection voltage level vdd level voltage detection reset signal vdcr2
figure 7-4 changes in the voltage detection flag and the voltage detection status flag tmp89fw20a page 95 2012/5/18 rb000 detection voltage level vdd level vdcr2 vdcr1 vdcr1 write "0" to vdcr1 the flag is not set because vdcr2 is "0"
7.4 register settings 7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals when the operation mode is set to generate intvltd interrupt request signal, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. set the detection voltage at vdcr1. 3. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [s] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". 7. clear the voltage detection circuit interrupt latch to "0" and set the interrupt enable flag to "1" to en- able interrupts. note:when the supply voltage (vdd) is close to the detection voltage (vdxlvl), voltage detection re- quest signals may be generated frequently. if this may pose any problem, execute appropriate wait pro- cessing depending on fluctuations in the system power supply and clear the interrupt latch before re- turning from the intvltd interrupt service routine. to disable the voltage detection circuit while it is enabled with the intvltd interrupt request, make the fol- lowing setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. clear vdcr2 to "0" to disable the voltage detection operation. note:if the voltage detection circuit is disabled without clearing interrupt enable flag, unexpected interrupt re- quest may occur. 7.4.2 setting procedure when the operation mode is set to generate voltage detection re- set signals when the operation mode is set to generate voltage detection reset signals, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. set the detection voltage at vdcr1. 3. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [s] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". tmp89fw20a 7. voltage detection circuit 7.4 register settings page 96 2012/5/18 rb000
7. clear vdcr1 to "0". 8. set vdcr2 to "1" to set the operation mode to generate voltage detection reset signals. note 1: vdcr1 and vdcr2 are initialized by a power-on reset or an external reset input only. if the supply volt- age (vdd) becomes lower than the detection voltage (vdlvl) in the period from release of the voltage de- tection reset until clearing of vdcr2 to "0", a voltage detection reset signal is generated immedi- ately. note 2: the voltage detection reset signals are generated continuously as long as the supply voltage (vdd) is low- er than the detection voltage (vdlvl). to disable the voltage detection circuit while it is enabled with the voltage detection reset, make the follow- ing setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 3. clear vdcr2 to "0" to disable the voltage detection operation. note:if the voltage detection circuit is disabled without clearing interrupt enable flag, unexpected interrupt re- quest may occur. 7.5 caution in the using voltage detevtion circuit when using the voltage detection circuit, must protect the reset pin from external noise. if the reset pin recognizes as an external reset input, the voltage detection circuit will be initialized and the volt- age detection reset signal is released. cpu and the peripheral circuit start operation. at this time, if supply voltage is below in the level of recommended operational voltage, this may cause malfunc- tion. be sure to set a level of reset pin to high/low by using external circuits. reset pin has a built-in pull-up resistor. however when reset pin is open, it is not effective enough against external noise. when reset pin is set to high/low using external circuits, sonfirm a result of the countermesures of blocking ex- ternal noise. tmp89fw20a page 97 2012/5/18 rb000
tmp89fw20a 7. voltage detection circuit 7.5 caution in the using voltage detevtion circuit page 98 2012/5/18 rb000
8. io ports the tmp89fw20 has 8 parallel input/output ports and 1 input ports(52 pins) as follows: table 8-1 list of i/o ports port name pin name number of pin input/output seccondary functions port p0 p03 ~ p00 4 input/output also used as the high-frequency oscillator connection pin and the lowfrequency oscillator connection pin port p1 p13, p12 ~ p10 3 input/output also used as the external reset input, the segment output and the ex- ternal resistor divider output port p2 p25 ~ p20 6 input/output also used as the segment output,external interrupt input,serial inter- face input/output,the uart input/output, the timer counter input/out- put, and the onchip debug input. port p4 p47 ~ p40 8 input/output also used as the analog input , the key-on wakeup input,the time- rcounter input/output,uart input/output,the external interrupt input and the stop mode release signal input port p5 p57 ~ p50 8 input/output also used as the segment output port p6 p67 ~ p60 8 input/output also used as the segment output port p7 p77 ~ p70 8 input/output also used as the segment output port p9 p97 ~ p90 8 input/output (p93 input) also used as the timer counter input/output, the divider output and the uart input/output tmp89fw20a page 99 2012/5/18 ra000
each output port contains a latch, which holds the output data. no input port has a latch, so the external input da- ta should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 8-1 shows input/output timing examples. external data is read from an i/o port in the read cycle during execution of the read instruction. this timing can- not be recognized from outside, so that transient input such as chattering must be processed by the program. data is output to an i/o port in the next cycle of the write cycle during execution of the write instruction. figure 8-1 input/output timing(example) note: the positions of the read and write cycles may vary, depending on the instruction tmp89fw20a 8. io ports page 100 2012/5/18 ra000 instruction execution cycle system clock internal read signal data input example:ld a, (x) fetch cycle fetch cycle read cycle instruction execution cycle internal read signal data output example:ld (x), a fetch cycle fetch cycle write cycle (a) input timing (b) output timing system clock
8.1 i/o port control registers the following control registers are used for i/o ports. (the port number is indicated in place of x.) registers that- can be set vary depending on the port. for details, refer to the description of each port. ? pxdr register this is the register for setting output data. when a port is set to the "output mode", the value specified at pxdr is output from the port. ? pxprd register this is the register for reading input data. when a port is set to the "input mode", the current port in- put status can be read by reading pxprd. ? pxcr register this register switches a port between input and output. a port can be switched between the "input mode" and the "output mode". ? pxfc register this register enables the secondary function output of each port. the secondary function output of each port can be enabled or disabled. ? pxoutcr register this register switches the port output between the c-mos output and the open drain output. ? pxpu register this register determines whether or not the built-in pull-up resistor is connected when a port is used in the input mode or as the open drain output. ? pxpud1 register this register determines whether or not the built-in pull-up resistor or pull-down resistor is connected when a port is used in the input mode or as the open drain output. ? pxpud2 register this register determines whether or not the built-in pull-up resistor or the built-in pull-down resistor is connected when pxud1 resitor set connection.(only port for embbeded built-in pull-up/built-in pull- down port) tmp89fw20a page 101 2012/5/18 ra000
8.2 list of i/o port settings for the setting methods for individual i/o ports, refer to the following table.table 8-2 table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc pxlcr other required settings port p0 p03, p01 port input 0 without resister without resister without resister port output 1 p02, p00 port input 0 0 port output 1 0 p03 xtout * without resister syscr2="1" p02 xtin * 1 syscr2="1" p01 xout * without resister syscr2="1" p00 xin * 1 syscr2="1" port p1 p13 ~ p12 port input 0 without resister without resister 0 lcdcr2="1" note 4 port output 1 0 lcdcr2="1" note 4 p10 port input 0 without resister note 1 p10 port output 1 note 1 p13 ~ p12 seg30 ~ seg31 output * 1 lcdcr2="1" note 4 p13 ~ p12 external resitor divider 0 0 lcdcr2="0" note 4 p10 reset input * without resister note 1 port p2 p25 ~ p20 port input 0 * * 0 port output 1 ** 0 0 p25 ~ p20 seg24 ~ seg29output * * * 1 p25 si1input 0 * * 0 sersel="0" p24 so0 output 1 ** 1 0 sersel="0" scl0 input/output 0 1 1 0 sersel="1" p23 sclk1input/output 0 * * 0 sersel="0" sclk1output 1 ** 1 0 sersel="0" sda0?output 0 1 1 0 sersel="1" p22 sclk0 input 0 * * 0 sersel="1" sclk0 output 1 ** 1 0 sersel="1" tcb0 input 0 * * 0 sersel="0" itsel="1" ppgb0 output 1 ** 1 0 sersel="0" p21 si0 input 0 * * 0 sersel="1" rxd0 input 0 * * 0 sersel="0" p20 so0 output 1 ** 1 0 sersel="1" txd0 output 1 ** 1 0 sersel="0" tmp89fw20a 8. io ports 8.2 list of i/o port settings page 102 2012/5/18 ra000
table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc pxlcr other required settings port p4 p47 ~ p40 port input 0 without resister 0 without resister port output 1 0 ain7 ~ ain0 0 1 p47 stop input 0 0 int5 input 0 0 p46 kwi2 input * * kwucr0="1" p45 rxd2 injput 0 0 sersel="0" kwi1 input * * kwucr0="1" p44 txd2 output 1 1 kwi0 input * * kwucr0="1" p43 int0 input 0 0 p42 ppgb0 output 1 1 p41 tcb0 input 0 0 itsel="0" port p5 p57 ~ p50 port input 0 without resister * 0 port output 1 0 0 seg16 ~ seg23 * * 1 p54 sclk0 input 0 * 0 sersel="0" int3 input 0 * 0 itsel="1" sclk0 output 1 1 0 sersel="0" p53 rxd0 input 0 * 0 sersel="1" int2 input 0 * 0 itsel="1" si0 input 0 * 0 sersel="0" p52 txd0ooutput 1 1 0 sersel="1" int1 inpu input 0 * 0 itsel="1" so0 output 1 1 0 sersel="0" p51 rxd1 input 0 * 0 sersel="0*" rxd0 input 0 * 0 sersel="1*" p50 txd1output 1 1 0 sersel="0*" txd 0output 1 1 0 sersel="1*" port p6 p67 ~ p60 port input 0 without resister without resister 0 port output 1 0 seg8 ~ seg15 * 1 port p7 p77 ~ p70 port input 0 without resister without resister 0 port output 1 0 seg0 ~ seg7 * 1 tmp89fw20a page 103 2012/5/18 ra000
table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc pxlcr other required settings port p9 p97 ~ p90 port input 0 without resister * without resister p97 ~ p94 p92 ~ p90 port output 1 0 p97 tc03 input 0 * int3 input 0 * itsel="0" ppg03 / pwm03 output 1 1 p96 tc02 input 0 * ppg02 / pwm02 output 1 1 itsel="0" dvo output 1 1 itsel="1" p95 tc01 input 0 * int2 input 0 * itsel="0" ppg01 / pwm01 1 1 p94 tc00 input 0 * int1 input 0 * itsel="1" ppg00 / pwm00 output 1 1 p93 emg input 0 * sersel="0" rxd1 input 0 * sersel="11" p92 ppgc02 output 1 1 sersel="0" txd1 output 1 1 sersel="1" p91 ppgc01 output 1 1 sersel="0" itsel="0" ppga0 output 1 1 sersel="0" itsel="1" txd2 output 1 1 sersel="1" p90 tcc0input 0 * sersel="0" tca0 input 0 * sersel="0" sersel="00" rxd2 input 0 * sersel="1" note 1: after the power is turend on.pin p10 serves as an external reset input.to use pin p10 as a port,refer to "how to use the external reset pin as a port" note 2: about sersel,please refer to "x.x peripheral input/output select function note 3: the symbol and numeric characters in the table have the folowing meanings note 4: lcdcr2 should be set when poffcr2 is "1" symbol and nu- meric characters meaning 0 set "0" 1 set "1" * dont care (operation is the same whether "1" or "0" is selected) ** the sink open drain output or the c-mos output can be se- lected. without register ther is no register that corresponds to the bit. tmp89fw20a 8. io ports 8.2 list of i/o port settings page 104 2012/5/18 ra000
8.3 i/o port registers 8.3.1 port p0 (p03 ~ p00) port p0 is a 4-bit input/output port that can be set to input or output for each bit individually, and it is also used as the high-frequency oscillation connection pin and the low-frequency oscillation connection pin. port p0 contains a programmable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode. table 8-3 port p0 - - - - p03 p02 p01 p00 secondary function - - - - xtout xtin xout xin figure 8-2 port p0 (p00, p01) tmp89fw20a page 105 2012/5/18 ra000 internal data bus output latch (for each bit) p0dr0 write p00 (xin) r note1 : r = 100 (typ.) note2 : rf = 1.2m (typ.) note3 : ro = 0.5k (typ.) note4 : r in3 = 50k (typ.) p0prd0 read function control (for each bit) input/output control (for each bit) p0fc0 write p0cr0 write vdd vdd pull-up control (for each bit) p0pu0 write syscr2 spcr output latch (for each bit) p0dr1 write p01 (xout) r rf r in3 r in3 ro p0prd1 read system clock reset (internal factor reset) input/output control (for each bit) p0cr1 write programmable pull-up resistor programmable pull-up resistor vdd vdd pull-up control (for each bit) p0pu1 write syscr1 syscr1 reset signal (reset 2)
figure 8-3 port p0 (p02, p03) tmp89fw20a 8. io ports 8.3 i/o port registers page 106 2012/5/18 ra000 output latch (for each bit) p0dr2 write p02 (xtin) r rf p0prd2 read function control (for each bit) input/output control (for each bit) p0fc2 write p0cr2 write vdd vdd pull-up control (for each bit) p0pu2 write syscr2 spcr output latch (for each bit) p0dr3 write p03 (xtout) r p0prd3 read input/output control (for each bit) p0cr3 write programmable pull-up resistor programmable pull-up resistor vdd vdd pull-up control (for each bit) p0pu3 write syscr1 syscr1 reset signal (reset 2) note1 : r = 100 (typ.) note2 : rf = 6m (typ.) note3 : ro = 220k (typ.) note4 : r in3 = 50k (typ.) ro r in3 r in3 internal data bus
port p0 output latch p0dr (0x00000) 7 6 5 4 3 2 1 0 bit symbol - - - - p03 p02 p01 p00 read/write r r r r r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p0 input/output control p0cr (0x00f1a) 7 6 5 4 3 2 1 0 bit symbol - - - - p0cr3 p0cr2 p0cr1 p0cr0 read/write r r r r r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode (port input) 1: output mode (port output) note:when p0fc0 is set to "1" (xin(i) is selected as function), p0cr1 and p0cr0 must be clear to "0".if p0cr0 or p0cr1 is set to "1" while p0fc0 is "1" then the output of oscillation port will be short and operation cur- rent will increase. port p0 function control p0fc (0x00f34) 7 6 5 4 3 2 1 0 bit symbol - - - - - p0fc2 - p0fc0 read/write r r r r r r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: port func- tions port func- tions 1: xtin (i) xin (i) note 1: to select the external high-freuency clock,the setting"1"to p0fc0 should be done before syscr2 is set to "1"when p0fc0 is "0",the setting"1"to syscr2generates a system clock(internal factor)reset. note 2: symbol"i"means secondary function input port p0 built-in pull-up resistor control p0pu (0x00f27) 7 6 5 4 3 2 1 0 bit symbol - - - - p0pu3 p0pu2 p0pu1 p0pu0 read/write r r r r r/w r/w r/w r/w after rset 0 0 0 0 0 0 0 0 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected. (the resistor is connected in the input mode only. under any other conditions,setting to "1" does not make the resistor con- nected.) tmp89fw20a page 107 2012/5/18 ra000
port p0 input data p0prd (0x0000d) 7 6 5 4 3 2 1 0 bit symbol - - - - p0prd3 p0prd2 p0prd1 p0prd0 read/write r r r r r r r r after reset 0 0 0 0 * * * * function if the port is in the input mode, the contents of the port are read. if not, "0" is read table 8-4 p0prd read value (p00 ~ p01) set condition p1prd read value p0fc0 p0cri * 1 "0" 1 * "0" 0 0 contents of port note 1: * : dont care note 2: i = 0, 1 table 8-5 p0prd read value (p02 ~ p03) set condition p0prd read value p0fc2 p0crj * 1 "0" 1 * "0" 0 0 contents of port note 1: * : dont care note 2: j = 2, 3 tmp89fw20a 8. io ports 8.3 i/o port registers page 108 2012/5/18 ra000
8.3.2 p1 (p13 ~ p10) port p1 is a 3-bit input/output port that can be set to input or output for each bit individually, and is also used as the segment output, external resistor divider output and external reset input.port p1 contains a program- mable pull-up resistor on the vdd side. this pull-up resistor can be used when theport is used in the input mode.after reset, pin p10 serves as the external reset input and pin p12,p13 serves as external resitor divider output. to use pin p10 as a port, refer to "how to use external reset input pin as a port.to use pin p12 and p13 as port,set each register of p1 after set poffcr2 to "1" and set lcdcr2 to "1". table 8-6 port p1 - - - - p13 p12 - p10 secondary function - - - - seg38 v1 seg39 v2 - reset tmp89fw20a page 109 2012/5/18 ra000
figure 8-4 port p1 tmp89fw20a 8. io ports 8.3 i/o port registers page 110 2012/5/18 ra000 internal data bus output latch (for each bit) en p1dr write p10 r in2 r in3 r note1 : r = 100 (typ.) note2 : r in2 = 220k (typ.) note3 : r in3 = 50k (typ.) p1prd read input/output control (for each bit) p1cr write programmable pull-up resistor reset pull-up resistor vdd vdd vdd pull-up control (for each bit) p1pu write internal data bus output latch (for each bit) p1dr write syscr1 spcr syscr3 syscr4 0xb2 write syscr1 reset signal (reset 2) p1i r note1 : r = 100 (typ.) note2 : r in3 = 50k (typ.) note3 : i = 2 to 3 p1prd resd lcdcr2 external breeder resistor segment output input/output control (for each bit) p1lcr write vdd input/output control (for each bit) p1cr write syscr1 syscr1 reset signal (reset0) lcd peripheral functions low-voltage detection reset signal watchdog timer reset signal system clock reset signal power-on reset signal reset 1 reset 2 reset 0
port p1 output latch p1dr (0x00001) 7 6 5 4 3 2 1 0 bit symbol - - - - p13 p12 - p10 read/write r r r r r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected. outputs l level when the output mode is se- lected. 1: outputs h level when the output mode is selected. outputs h level when the output mode is se- lected. port p1 input/output control p1cr (0x00f1b) 7 6 5 4 3 2 1 0 bit symbol - - - - p1cr3 p1cr2 - p1cr0 read/write r r r r r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode (port input) input mode (port input) 1: output mode (port output) output mode (port output) port p1 built-in pull-up resistor control p1pu (0x00f28) 7 6 5 4 3 2 1 0 bit symbol - - - - - - - p1pu0 read/write r r r r r r r r/w after reset 0 0 0 0 0 0 0 0 function 0: the built-in pull-up re- sistor is not connected. 1: (note1) note 1: the built-in pull-up resistor is connected. (the resistor is connected only when the port is used in the input mode or as the open drain output. under any other conditions,setting to "1" does not make the resistor connected.) p1 port segment output control p1lcr (0x00ec1) 7 6 5 4 3 2 1 0 bit symbol - - - - p1lcr3 p1lcr2 - - read/write r r r r r/w r/w r r after reset 0 0 0 0 0 0 0 0 function 0: input/output port 1: lcd segment output (note1) note 1: when p1lcr is set to "1",there is no need to set p1cr. tmp89fw20a page 111 2012/5/18 ra000
port p1 input data p1prd (0x0000e) 7 6 5 4 3 2 1 0 bit symbol - - - - p1prd3 p1prd2 - p1prd0 read/write r r r r r r r r after reset 0 0 0 0 * * 0 * function (note1) (note1) note 1: if ther prot is in the input mode,the contents of the port are read.if not ,"0" is read. table 8-7 p1prd read value set condition p1prd read value p1cri p1lcri 0 0 contents of port 1 0 "0" * 1 "0" note 1: * : dont care note 2: i = 0, 2 ~ 3 tmp89fw20a 8. io ports 8.3 i/o port registers page 112 2012/5/18 ra000
8.3.3 port p2 (p25 ~ p20) port p2 is an 6-bit input/output port that can be set to input or output for each bit individually, and it is al- so used as lcd segment output, the serial interface input/output, the uart input/output ,the timer/counter in- put/output and the onchipdebug function.the output circuit has the p-channel output control function and ei- ther the sink open drain output or the cmos output can be selected. port p2 contains a programmable pull-up/ pull-down resistor. this pull-up resistor can be used when the port is used in the input mode or as a sink open drain output.when this port is used as the serial bus interface, the serial interface or the uart, setting for serial interface selecting function is also needed. for details, refer to "8.4 serial interface selecting func- tion".for the on-chip debug function, refer to the chapter of "on-chip debug function (ocd)" table 8-8 port p2 - - p25 p24 p23 p22 p21 p20 secondary function - - seg24 si1 seg25 so1 scl0 seg26 sclk1 sda0 seg27 sclk0 tcb0 ppgb0 seg28 si0 rxd0 ocdio seg29 so0 txd0 ocdck tmp89fw20a page 113 2012/5/18 ra000
figure 8-5 port p2 tmp89fw20a 8. io ports 8.3 i/o port registers page 114 2012/5/18 ra000 internal data bus 0 1 s output latch (for each bit) p2dr write p2i r r in3 note1 : r = 100 (typ.) note2 : r in3 = 50k (typ.) note3 : i = 0 to 5 peripheral functions i/o select peripheral functions peripheral functions p2prd read function control (for each bit) p2fc write output control (for each bit) p2outcr write programmable pull-up/down resistor vdd vdd input/output control (for each bit) p2cr write segment output control (for each bit) p2lcr write pull-up/down control (for each bit) p2pud1 write pull-up/down control (for each bit) p2pud2 write syscr1 syscr1 reset signal (reset 2) spcr lcd p22 only spcr p25 ~ p23 only tcb0 sio0 sio1 uart0 i2c0 sclk1, si1, sda0, scl0, sclk0, si0, rxd0, tcb0 sclk1, so1, sda0, scl0, sclk0, so0, txd0, ppgb0 p24 ~ p22, p20
port p2 output latch p2dr (0x00002) 7 6 5 4 3 2 1 0 bit symbol - - p25 p24 p23 p22 p21 p20 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected 1: outputs h level when the output mode is selected. (serves as hi-z or pull-up depend- ing on settings of p2outcrand p2pu.) port p2 function control p2cr (0x00f1c) 7 6 5 4 3 2 1 0 bit symbol - - p2cr5 p2cr4 p2cr3 p2cr2 p2cr1 p2cr0 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port input) si1 (i) scl0 (i/o) sclk1 (i) sda0 (i/o) sclk0 (i) tcb0 (i) rxd0 (i) si0 (i) - 1: output mode(port output) - so1 (o) sclk1 (o) sclk0 (o) ppgb0 (o) - txd0 (o) so0 (o) note:symbol "i" means secondary function input. symbol "o" means secondary function output. symbol "i/o" mean- ssecondary function input/output p2 function control p2fc (0x00f36) 7 6 5 4 3 2 1 0 bit symbol - - - p2fc4 p2fc3 p2fc2 - p2fc0 read/write r r r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: port function port func- tion 1: so1 (o) scl0 (i/o) sclk1 (o) sda0 (i/o) sclk0 (o) ppgb0 (o) txd0 (o) so0 (o) port p2 output control p2outcr (0x00f43) 7 6 5 4 3 2 1 0 bit symbol - - p2out5 p2out4 p2out3 p2out2 p2out1 p2out0 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: c-mos output 1: open drain output - scl0(i/o) sdao(i/o) - - - note:i/o : secondary function input/output tmp89fw20a page 115 2012/5/18 ra000
port p2 built-in pull-up/pull-down resistor control p2pud1 (0x00f29) 7 6 5 4 3 2 1 0 bit symbol - - p2pud15 p2pud14 p2pud13 p2pud12 p2pud11 p2pud10 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected.(the resistor is connected only when the port is used in the input mode or as the open drain output. under any other condi- tions.setting to "1" does not make the resitor connected) port p2 built-in pull-up/pull-dwon select control p2pud2 (0x00ed2) 7 6 5 4 3 2 1 0 bit symbol - - p2pud25 p2pud24 p2pud23 p2pud22 p2pud21 p2pud20 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 1 1 1 1 1 1 function 0: the built-in pull-down resistor is selected. 1: the built-in pull-up resistor is selected. note:select pull-up/pull-down resistor(p2pud2) after disconnect pull-up/pull-down resitor by built-in pull-up/pull- down resitor control (p2pud1) port p2 output control p2lcr (0x00ec2) 7 6 5 4 3 2 1 0 bit symbol - - p2lcr5 p2lcr4 p2lcr3 p2lcr2 p2lcr1 p2lcr0 read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input/output port 1: lcd segment oputput note 1 note 1: when p2lcr is set to "1", the value set to p2fc,p2cr and p2outcr has no meaning. tmp89fw20a 8. io ports 8.3 i/o port registers page 116 2012/5/18 ra000
port p2 input data p2prd (0x0000f) 7 6 5 4 3 2 1 0 bit symbol r r p2prd5 p2prd4 p2prd3 p2prd2 p2prd1 p2prd0 read/write 0 0 r r r r r r after reset * * * * * * function if the port is used in the input mode or as the open drain output, the contents of the port are read. if not, "0" is read. table 8-9 p2prd read value (p20 ~ p25) set condtion p2prd read value p2cri p2outcri 0 * contents of port 1 0 "0" 1 1 contents of port note 1: * : dont care note 2: i = 0 ~ 5 tmp89fw20a page 117 2012/5/18 ra000
8.3.4 port p4 (p47 ~ p40) port p4 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is al- so used as the analog input , the key-on wakeup input,the timer counter input/output,uart input/output,the ex- ternal interrupt input and the stop mode release signal input port p4 contains a programmable pull-up resis- tor on the vdd side. this pull-up resistor can be used when theport is used in the input mode. table 8-10 port p4 p47 p46 p45 p44 p43 p42 p41 p40 secondary function ain7 stop int5 ain6 kwi2 ain5 kwi1 rxd2 ain4 kwi0 txd2 ain3 int0 ain2 ppgb0 ain1 tcb0 ain0 figure 8-6 port p4 tmp89fw20a 8. io ports 8.3 i/o port registers page 118 2012/5/18 ra000 internal data bus 0 1 s output latch (for each bit) p4dr write p4i r r in3 note1 : r = 100 (typ.) note2 : r in3 = 50k (typ.) note3 : i = 0 to 7 note4 : j = 0 to 2 peripheral functions i/o selects tcb0 uart2 external interrupt p4prd read kwij enable signal stop enable signal tcb0, int5, rxd2 kwi0, kwi1, kwi2 ppgb0, txd2 stop function control (for each bit) p4fc write ainen aini enable programmable pull-up resisto r vdd vdd input/output control (for each bit) p4cr write pull-up control (for each bit) p4pu write syscr1 syscr1 reset signal (reset 2) spcr for p47 except for p47 p42, p44 only ad peripheral functions peripheral functions peripheral functions peripheral functions standby control key-on wakeup for p40 to p43 for p47 for p44 to p46
port p4 output latch p4dr (0x00004) 7 6 5 4 3 2 1 0 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p4 input/output control p4cr (0x00f1e) 7 6 5 4 3 2 1 0 bit symbol p4cr7 p4cr6 p4cr5 p4cr4 p4cr3 p4cr2 p4cr1 p4cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port input) stop (i) int5 (i) kwi2 (i) kwi1 (i) rxd2 (i) kwi0 (i) int0 (i) - tcb0 (i) - 1: output mode(port output) - - - txd2 (o) - ppgb0 (o) - - note:symbol "i" means secondary function input. symbol "o" means secondary function output. port p4 function control p4fc (0x00f38) 7 6 5 4 3 2 1 0 bit symbol p4fc7 p4fc6 p4fc5 p4fc4 p4fc3 p4fc2 p4fc1 p4fc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 f u n c t i o n 0: port function 1: p4crx=0 ain7 (i) ain6 (i) ain5 (i) ain4 (i) ain3 (i) ain2 (i) ain1 (i) ain0 (i) p4crx=1 - - - txd2 (o) - ppgb0(o) - - p4 built-in pull-up resistor control p4pu (0x00f2b) 7 6 5 4 3 2 1 0 bit symbol p4pu7 p4pu6 p4pu5 p4pu4 p4pu3 p4pu2 p4pu1 p4pu0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected. (the resistor is connected only when the port is used in input mode under any other conditions, setting to "1" does not make the resistor connected.) tmp89fw20a page 119 2012/5/18 ra000
port p4 input data p4prd (0x00011) 7 6 5 4 3 2 1 0 bit symbol p4prd7 p4prd6 p4prd5 p4prd4 p4prd3 p4prd2 p4prd1 p4prd0 read/write r r r r r r r r after reset * * * * * * * * function if the port is in the input mode, the contents of the port are read. if not, "0" is read. table 8-11 p4prd reaed valeu set condtion p4prd read value p4cri p4fci 0 0 contents of port * 1 "0" 1 * "0" note 1: * : dont care note 2: i = 0 ~ 7 tmp89fw20a 8. io ports 8.3 i/o port registers page 120 2012/5/18 ra000
8.3.5 port p5 (p57 ~ p50) port p5 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is al- so used as lcd segment output. table 8-12 port p5 p57 p56 p55 p54 p53 p52 p51 p50 secondary function seg16 seg17 seg18 seg19 int3 sclk0 seg20 int2 si0 rxd0 seg21 int1 so0 txd0 seg22 rxd1 rxd0 seg23 txd1 txd0 figure 8-7 port p5 tmp89fw20a page 121 2012/5/18 ra000 internal data bus 0 1 s output latch (for each bit) p5dr write p5i r note1 : r = 100 (typ.) note2 : i = 0 to 7 peripheral functions i/o selects peripheral functions peripheral functions p5prd read so0, sclk0, txd0, txd1 int1, int2, int3, si0, sclk0, rxd0, rxd1 function control (for each bit) p5fc write vdd input/output control (for each bit) p5cr write segment output control (for each bit) p5lcr write syscr1 syscr1 reset signal (reset 2) lcd uart0 uart1 sio0 external interrupt spcr p50, p52, p54 only
port p5 output latch p5dr (0x00005) 7 6 5 4 3 2 1 0 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected 1: outputs h level when the output mode is selected port p5 input/output control p5cr (0x00f1f) 7 6 5 4 3 2 1 0 bit symbol p5cr7 p5cr6 p5cr5 p5cr4 p5cr3 p5cr2 p5cr1 p5cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port input) - - - int3 (i) sclk0(i) int2 (i) si0 (i) rxd0 (i) int1 (i) rxd1 (i) rxd0 (i) - 1: outpu mode(port output) - - - sclk0 (o) - so0 (o) txd0 (o) - txd1 (o) txd0 (o) note:symbol "i" means secondary function input. symbol "o" means secondary function output. port p5 funtion control p5fc (0x00f39) 7 6 5 4 3 2 1 0 bit symbol - - - p5fc4 - p5fc2 - p5fc0 read/write r r r r/w r r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: port func- tion port func- tion port func- tion 1: sclk0 (o) so0 (o) txd0 (o) txd1 (o) txd0 (o) port p5 segment output control p5lcr (0x00ec5) 7 6 5 4 3 2 1 0 bit symbol p5lcr7 p5lcr6 p5lcr5 p5lcr4 p5lcr3 p5lcr2 p5lcr1 p5lcr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input/output port 1: lcd segment output (note1) note 1: when p5lcr is set to "1", the value set to ,p5cr has no meaning. tmp89fw20a 8. io ports 8.3 i/o port registers page 122 2012/5/18 ra000
port p5 input data p5prd (0x00012) 7 6 5 4 3 2 1 0 bit symbol p5prd7 p5prd6 p5prd5 p5prd4 p5prd3 p5prd2 p5prd1 p5prd0 read/write r r r r r r r r after reset * * * * * * * * function if the port is used in the input mode, the contents of the port are read. if not, "0" is read. table 8-13 p5prd read value set condtion p5prd read value p5cri p5fci 0 0 contents of port * 1 "0" 1 * "0" note 1: * : dont care note 2: i = 0 ~ 7 tmp89fw20a page 123 2012/5/18 ra000
8.3.6 port p6 (p67 ~ p60) port p6 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is al- so used as lcd segment output. table 8-14 port p6 p67 p66 p65 p64 p63 p62 p61 p60 secondary function seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 figure 8-8 port p6 tmp89fw20a 8. io ports 8.3 i/o port registers page 124 2012/5/18 ra000 internal data bus output latch (for each bit) p6dr write p6i r note1 : r = 100 (typ.) note2 : i = 0 to 7 peripheral functions p6prd read vdd input/output control (for each bit) p6cr write segment output control (for each bit) p6lcr write syscr1 syscr1 reset signal (reset 2) lcd spcr
port p6 output latch p6dr (0x00006) 7 6 5 4 3 2 1 0 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected 1: outputs h level when the output mode is selected port 6 input/output control p6cr (0x00f20) 7 6 5 4 3 2 1 0 bit symbol p6cr7 p6cr6 p6cr5 p6cr4 p6cr3 p6cr2 p6cr1 p6cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port input) 1: output mode(port output) port p6 segment output p6lcr (0x00ec6) 7 6 5 4 3 2 1 0 bit symbol p6lcr7 p6lcr6 p6lcr5 p6lcr4 p6lcr3 p6lcr2 p6lcr1 p6lcr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input/output port 1: lcd segment output (note1) note 1: when p6lcr is set to "1", the value set to ,p6cr has no meaning. port p6 input data p6prd (0x00013) 7 6 5 4 3 2 1 0 bit symbol p6prd7 p6prd6 p6prd5 p6prd4 p6prd3 p6prd2 p6prd1 p6prd0 read/write r r r r r r r r after reset * * * * * * * * function if the port is used in the input mode, the contents of the port are read. if not, "0" is read. table 8-15 p6prd read value set condi- tion p6prd read value p6cri 0 contents of port 1 "0" note 1: * : dont care note 2: i = 0 ~ 7 tmp89fw20a page 125 2012/5/18 ra000
8.3.7 port p7 (p77 ~ p70) port p7 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is al- so used as lcd segment output. table 8-16 port p7 p77 p76 p75 p74 p73 p72 p71 p70 secondary function seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 figure 8-9 port p7 tmp89fw20a 8. io ports 8.3 i/o port registers page 126 2012/5/18 ra000 internal data bus output latch (for each bit) p7dr write p7i r note1 : r = 100 (typ.) note2 : i = 0 to 7 peripheral functions p7prd read vdd input/output control (for each bit) p7cr write segment output control (for each bit) p7lcr write syscr1 syscr1 reset signal (reset 2) lcd spcr
port p7output latch p7dr (0x00007) 7 6 5 4 3 2 1 0 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected 1: outputs h level when the output mode is selected port p7 input/output control p7cr (0x00f21) 7 6 5 4 3 2 1 0 bit symbol p7cr7 p7cr6 p7cr5 p7cr4 p7cr3 p7cr2 p7cr1 p7cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port inptut) 1: output mode(port output) port p7 segment output control p7lcr (0x00ec7) 7 6 5 4 3 2 1 0 bit symbol p7lcr7 p7lcr6 p7lcr5 p7lcr4 p7lcr3 p7lcr2 p7lcr1 p7lcr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input/output port 1: lcdsegment output (note1) note 1: when p7lcr is set to "1", the value set to ,p7cr has no meaning. port p7 input data p7prd (0x00014) 7 6 5 4 3 2 1 0 bit symbol p7prd7 p7prd6 p7prd5 p7prd4 p7prd3 p7prd2 p7prd1 p7prd0 read/write r r r r r r r r after reset * * * * * * * * function if the port is used in the input mode, the contents of the port are read. if not, "0" is read. table 8-17 p7prd read value set con- dtion p7prd read value p7cri 0 contents of port 1 "0" note 1: * : dont care note 2: i = 0 ~ 7 tmp89fw20a page 127 2012/5/18 ra000
8.3.8 port p9 (p97 ~ p90) port p9 is an 7-bit input/output port that can be set to input or output for each bit individually and 1-bit in- put port, and it is also used as the timer counter input/output, the divider output and the uart input/output. p93 is an input port. when p96 is used as the divider output or p90 and p91 is used as the timer counter out- put , timer output select functiont is also needed. for details, refer to "1.3 peripheral input/output select func- tion". table 8-18 port p9 p97 p96 p95 p94 p93 p92 p91 p90 secondary function tc03 ppg03 pwm03 int3 tc02 ppg02 pwm02 dvo tc01 ppg01 pwm01 int2 tc00 ppg00 pwm00 int1 emg0 rxd1 ppgc02 txd1 ppgc01 ppga0 txd2 tcc0 tca0 rxd2 figure 8-10 port p9 tmp89fw20a 8. io ports 8.3 i/o port registers page 128 2012/5/18 ra000 internal data bus 0 1 s output latch (for each bit) p9dr write p9i r note1 : r = 100 (typ.) note2 : i = 0 to 2, 4 to 7 note3 : nch large current peripheral functions i/o selects tca0 tcc0 uart1 uart2 tc00 tc01 tc02 tc03 dvo external interrupt peripheral functions p9prd read function control (for each bit) p9prd read p9fc write vdd (note3) input/output control (for each bit) p9cr write p93 r syscr1 syscr1 reset signal (reset 2) syscr1 syscr1 reset signal (reset 2) spcr rxd2, tca0, tcc0 tc00, tc01, tc02, tc03, int1, int2, int3 rxd1, emg0 p91, p92, p94 to p97only ppg00, ppg01, ppg02, ppg03 pwm00, pwm01, pwm02, pwm03 ppgc01, ppgc02, ppga0 txd0, txd1, dvo spcr
p9 port output latch p9dr (0x00009) 7 6 5 4 3 2 1 0 bit symbol p97 p96 p95 p94 - p92 p91 p90 read/write r/w r/w r/w r/w r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: outputs l level when the output mode is selected outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. outputs h level when the output mode is selected. p9 port input/output conrol p9cr (0x00f23) 7 6 5 4 3 2 1 0 bit symbol p9cr7 p9cr6 p9cr5 p9cr4 - p9cr2 p9cr1 p9cr0 read/write r/w r/w r/w r/w r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function 0: input mode(port input) input mode(port input) tc03 (i) int3 (i) tc02 (i) tc01 (i) int2 (i) tc00 (i) int1 (i) - - tcc0 (i) tca0 (i) rxd2 (i) 1: output mode(port output) output mode(port output) ppg03 (o) pwm03 (o) ppg02 (o) pwm02 (o) dvo (o) ppg01 (o) pwm01 (o) ppg00 (o) pwm00 (o) ppgc02 (o) txd1 (o) ppgc01 (o) ppga0 (o) txd2 (o) - note:symbol "i" means secondary function input. symbol "o" means secondary function output. port p9 input data p9prd (0x00016) 7 6 5 4 3 2 1 0 bit symbol p9prd7 p9prd6 p9prd5 p9prd4 p9prd3 p9prd2 p9prd1 p9prd0 read/write r r r r r r r r after reset- function * * * * * * * * function if the port is in the input mode, the contents of the port are read. if not, "0" is read. table 8-19 p9prd read value set condition p9prd read value p9cri 0 contents of port 1 "0" note 1: * : dont care note 2: i = 0 ~ 7 tmp89fw20a page 129 2012/5/18 ra000
8.4 peripheral input/output select function on thetmp89fw20a the peripheral input/output pins and interrupt source assignment can be changed. inter- rupt source assignment can be changed by peripheral input/output select register1(itsel) and peripheral input/out- put select register2(sersel). figure 8-11 peripheral input/output select note: when peripheral function input/output select register is set ,setting for i/o port is also needed.for detail, re- fer to the chapter of i/o ports. tmp89fw20a 8. io ports 8.4 peripheral input/output select function page 130 2012/5/18 ra000 dvo tc023 sio1 i2c0 (dvo / ppg02 / pwm02) (sclk1 / sda0) (so1 / scl0) (si1) ppg02 / pwm02 dvo 0 1 0 1 sersel so1 si1 sclk1 sclk1 sda0 sda0 scl0 scl0 itsel 1 0 port external interrupt (int3) int3 0 1 itsel port (int3) port (int2) int2 0 1 itsel port (int2) port (int1) int1 0 1 itsel port (int1) port port port port p23 p25 p24 p96 p97 p54 p95 p53 p94 p52
figure 8-12 peripheral function input/output select note: when peripheral function input/output select register is set ,setting for i/o port is also needed.for detail, re- fer to the chapter of i/o ports. tmp89fw20a page 131 2012/5/18 ra000 tcc0 tca0 uart2 kwu uart0 sio0 tcb0 p91 (txd2 / ppga0 / ppgc01) p44 (txd2 / kwi0) p45 (rxd2 / kwi1) p90 (rxd2 / tcc0 / tca0) p53 (si0 / rxd0) p51 (rxd1 / rxd0) p93 (rxd1 / emg0) p50 (txd1 / txd0) p20 (txd0 / so0) p22 (sclk0 / tcb0 / ppgb0) p41 (tcb0) p52 (txd0 / so0) p54 (sclk0) p21 (si0 / rxd0) 0 1 0 1 0 1 1 0 00 01 10 11 1 0 1 0 sersel sersel port port p92 (txd1 / ppgc02) port port port txd2 rxd2 kwi0 kwi1 rxd0 txd0 txd1 si0 so0 uart1 rxd1 sclk0 ppgb0 sclk0 tcb0 ppga0 tca0 ppgc01 ppgc02 tcc0 emg0 sersel sersel sersel 1 0 0 1 0 1 0 1 sersel 1 0 sersel sersel 0 1 1 0 sersel 1 0 itsel itsel 1 0 port port port port port port port port port port
peripheral function input/output select register1 itsel (0x00fca) 7 6 5 4 3 2 1 0 bit symbol - - tcbsel dvosel itsel3 itsel2 itsel1 tcsel read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tcbsel tcb0 input port select 0: 1: p41input p22 input dvosel p96 port ouput select 0: 1: ppg02 / pwm02 output dvo output itsel3 int3 input port assignment 0: 1: p97 input p54 input itsel2 int2 input port assignment 0: 1: p95 input p53 input itsel1 int1 input port assignment 0: 1: p94 input p52 input tcsel p91port output select 0: 1: ppgc01 output ppga0 output note 1: the operation for changing itsel must be executed while the applicable peripheral operations are stopped. if itsel is switched during operation of these peripheral functions, each peripheral function may receive (transmit) unexpec- ted data and operate improperly. note 2: it is recommended to clear the interrupt latch for the applicable peripheral function immediately after changing itsel. tmp89fw20a 8. io ports 8.4 peripheral input/output select function page 132 2012/5/18 ra000
peripheral function input/output select register2 sersel (0x00fcb) 7 6 5 4 3 2 1 0 bit symbol tca0sel - srsel4 srsel3 srsel2 srsel1 srsel0 read/write r/w r/w r r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tca0sel 16-bit timer counter a0 input switch- ing 00: 01: 10: 11: p90 input (tca0) rxd0 input (also used as srsel1, 4) rxd1 input (also used as srsel3, 4) rxd2 input(also used as srsel2) srsel4,3 select uart1/uart0/tcc0 input/ output port p50 p51 p92 p93 00: txd1 rxd1 ppgc02 emg0 01: txd1 - txd1 rxd1 10: txd0 rxd0 ppgc02 emg0 11: txd0 rxd0 txd1 rxd1 srsel2 select uart2/tcc0/tca0 input/ output port p90 p91 p44 p45 0: tcc0 / tca0 ppgc01 / ppga0 txd2 rxd2 1: rxd2 txd2 kwi0 kwi1 srsel1 select uart0/sio0 input/output port p20 p21 p22 p52 p53 p54 0: txd0 rxd0 tcb0 / ppgb0 so0 si0 sclk0 1: so0 si0 sclk0 txd0 rxd0 - srsel0 select sio1/sbio0 input/output port select il28(interrupt source) p23 p24 p25 il28 0: sclk1 so1 si1 intsio1 1: sda0 scl0 - intsbi0 note 1: the operation for changing sersel must be executed while the applicable periphera operations are stopped. if ser- sel is switched during operation of these peripheral functions, each peripheral function may receive (transmit) unexpec- ted data and operate improperly. note 2: it is recommended to clear the interrupt latch for the applicable peripheral function immediately after changing ser- sel. interrupt latches are common to intsio1 and intsb10. therefore, if an interrupt occurs beforeor after ser- sel is switched, it is difficult to tell which function has caused the interrupt tmp89fw20a page 133 2012/5/18 ra000
tmp89fw20a 8. io ports 8.4 peripheral input/output select function page 134 2012/5/18 ra000
9. special function registers the tmp89fw20a adopts the memory mapped i/o system, and all peripheral hardware data control and trans- fer operations are performed through the special function registers (sfr). sfr1 is mapped on addresses 0x00000 to 0x0003f, sfr2 is mapped on addresses 0x00f00 to 0x00fff, and sfr3 is mapped on addresses 0x00e40 to 0x00ebf. 9.1 sfr1 (0x00000 to 0x0003f) table 9-1 sfr1 (0x00000 to 0x0003f) address register name address register name 0x00000 p0dr 0x00020 sio0sr 0x00001 p1dr 0x00021 sio0buf 0x00002 p2dr 0x00022 sbi0cr1 0x00003 reserved 0x00023 sbi0cr2/sbi0sr2 0x00004 p4dr 0x00024 i2c0ar 0x00005 p5dr 0x00025 sbi0dbr 0x00006 p6dr 0x00026 t00reg 0x00007 p7dr 0x00027 t01reg 0x00008 reserved 0x00028 t00pwm 0x00009 p9dr 0x00029 t01pwm 0x0000a reserved 0x0002a t00mod 0x0000b reserved 0x0002b t01mod 0x0000c reserved 0x0002c t001cr 0x0000d p0prd 0x0002d ta0dral 0x0000e p1prd 0x0002e ta0drah 0x0000f p2prd 0x0002f ta0drbl 0x00010 reserved 0x00030 ta0drbh 0x00011 p4prd 0x00031 ta0mod 0x00012 p5prd 0x00032 ta0cr 0x00013 p6prd 0x00033 ta0sr 0x00014 p7prd 0x00034 adccr1 0x00015 reserved 0x00035 adccr2 0x00016 p9prd 0x00036 adcdrl 0x00017 reserved 0x00037 adcdrh 0x00018 reserved 0x00038 dvocr 0x00019 reserved 0x00039 tbtcr 0x0001a uart0cr1 0x0003a eirl 0x0001b uart0cr2 0x0003b eirh 0x0001c uart0dr 0x0003c eire 0x0001d uart0sr 0x0003d eird 0x0001e td0buf/rd0buf 0x0003e reserved 0x0001f sio0cr 0x0003f psw note 1: do not access reserved addresses by the program. tmp89fw20a page 135 2012/5/18 ra000
9.2 sfr2 (0x00f00 to 0x00fff) table 9-2 sfr2 (0x00f00 to 0x00f7f) address register name address register name address register name address register name 0x00f00 reserved 0x00f20 p6cr 0x00f40 reserved 0x00f60 reserved 0x00f01 reserved 0x00f21 p7cr 0x00f41 reserved 0x00f61 reserved 0x00f02 reserved 0x00f22 reserved 0x00f42 reserved 0x00f62 reserved 0x00f03 reserved 0x00f23 p9cr 0x00f43 p2outcr 0x00f63 reserved 0x00f04 reserved 0x00f24 reserved 0x00f44 reserved 0x00f64 reserved 0x00f05 reserved 0x00f25 reserved 0x00f45 reserved 0x00f65 reserved 0x00f06 reserved 0x00f26 reserved 0x00f46 reserved 0x00f66 reserved 0x00f07 reserved 0x00f27 p0pu 0x00f47 reserved 0x00f67 reserved 0x00f08 reserved 0x00f28 p1pu 0x00f48 reserved 0x00f68 reserved 0x00f09 reserved 0x00f29 p2pud1 0x00f49 reserved 0x00f69 reserved 0x00f0a reserved 0x00f2a reserved 0x00f4a reserved 0x00f6a reserved 0x00f0b reserved 0x00f2b p4pu 0x00f4b reserved 0x00f6b reserved 0x00f0c reserved 0x00f2c reserved 0x00f4c reserved 0x00f6c reserved 0x00f0d reserved 0x00f2d reserved 0x00f4d reserved 0x00f6d reserved 0x00f0e reserved 0x00f2e reserved 0x00f4e reserved 0x00f6e reserved 0x00f0f reserved 0x00f2f reserved 0x00f4f reserved 0x00f6f reserved 0x00f10 reserved 0x00f30 reserved 0x00f50 reserved 0x00f70 sio1cr 0x00f11 reserved 0x00f31 reserved 0x00f51 reserved 0x00f71 sio1sr 0x00f12 reserved 0x00f32 reserved 0x00f52 reserved 0x00f72 sio1buf 0x00f13 reserved 0x00f33 reserved 0x00f53 reserved 0x00f73 reserved 0x00f14 reserved 0x00f34 p0fc 0x00f54 uart1cr1 0x00f74 poffcr0 0x00f15 reserved 0x00f35 reserved 0x00f55 uart1cr2 0x00f75 poffcr1 0x00f16 reserved 0x00f36 p2fc 0x00f56 uart1dr 0x00f76 poffcr2 0x00f17 reserved 0x00f37 reserved 0x00f57 uart1sr 0x00f77 poffcr3 0x00f18 reserved 0x00f38 p4fc 0x00f58 td1buf/rd1buf 0x00f78 reserved 0x00f19 reserved 0x00f39 p5fc 0x00f59 reserved 0x00f79 reserved 0x00f1a p0cr 0x00f3a reserved 0x00f5a uart2cr1 0x00f7a reserved 0x00f1b p1cr 0x00f3b reserved 0x00f5b uart2cr2 0x00f7b reserved 0x00f1c p2cr 0x00f3c reserved 0x00f5c uart2dr 0x00f7c sdwcr1 0x00f1d reserved 0x00f3d p9fc 0x00f5d uart2sr 0x00f7d sdwcr2 0x00f1e p4cr 0x00f3e reserved 0x00f5e td2buf/rd2buf 0x00f7e reserved 0x00f1f p5cr 0x00f3f reserved 0x00f5f reserved 0x00f7f reserved note 1: do not access reserved addresses by the program. tmp89fw20a 9. special function registers 9.2 sfr2 (0x00f00 to 0x00fff) page 136 2012/5/18 ra000
table 9-3 sfr2 (0x00f80 to 0x00fff) address register name address register name address register name address register name 0x00f80 reserved 0x00fa0 reserved 0x00fc0 reserved 0x00fe0 ill 0x00f81 reserved 0x00fa1 reserved 0x00fc1 reserved 0x00fe1 ilh 0x00f82 reserved 0x00fa2 reserved 0x00fc2 reserved 0x00fe2 ile 0x00f83 reserved 0x00fa3 reserved 0x00fc3 reserved 0x00fe3 ild 0x00f84 reserved 0x00fa4 reserved 0x00fc4 kwucr0 0x00fe4 reserved 0x00f85 reserved 0x00fa5 reserved 0x00fc5 reserved 0x00fe5 reserved 0x00f86 reserved 0x00fa6 reserved 0x00fc6 vdcr1 0x00fe6 reserved 0x00f87 reserved 0x00fa7 reserved 0x00fc7 vdcr2 0x00fe7 reserved 0x00f88 t02reg 0x00fa8 tb0dral 0x00fc8 rtccr 0x00fe8 reserved 0x00f89 t03reg 0x00fa9 tb0drah 0x00fc9 reserved 0x00fe9 reserved 0x00f8a t02pwm 0x00faa tb0drbl 0x00fca itsel 0x00fea reserved 0x00f8b t03pwm 0x00fab tb0drbh 0x00fcb sersel 0x00feb reserved 0x00f8c t02mod 0x00fac tb0mod 0x00fcc irstsr 0x00fec reserved 0x00f8d t03mod 0x00fad tb0cr 0x00fcd wuccr 0x00fed reserved 0x00f8e t023cr 0x00fae tb0sr 0x00fce wucdr 0x00fee reserved 0x00f8f reserved 0x00faf reserved 0x00fcf cgcr 0x00fef reserved 0x00f90 reserved 0x00fb0 reserved 0x00fd0 flscr1 0x00ff0 ilprs1 0x00f91 reserved 0x00fb1 reserved 0x00fd1 flscr2/flscrm 0x00ff1 ilprs2 0x00f92 reserved 0x00fb2 reserved 0x00fd2 reserved 0x00ff2 ilprs3 0x00f93 reserved 0x00fb3 reserved 0x00fd3 spcr 0x00ff3 ilprs4 0x00f94 reserved 0x00fb4 reserved 0x00fd4 wdctr 0x00ff4 ilprs5 0x00f95 reserved 0x00fb5 reserved 0x00fd5 wdcdr 0x00ff5 ilprs6 0x00f96 reserved 0x00fb6 reserved 0x00fd6 wdcnt 0x00ff6 ilprs7 0x00f97 reserved 0x00fb7 reserved 0x00fd7 wdst 0x00ff7 reserved 0x00f98 reserved 0x00fb8 reserved 0x00fd8 eintcr1 0x00ff8 reserved 0x00f99 reserved 0x00fb9 reserved 0x00fd9 eintcr2 0x00ff9 reserved 0x00f9a reserved 0x00fba reserved 0x00fda eintcr3 0x00ffa reserved 0x00f9b reserved 0x00fbb reserved 0x00fdb reserved 0x00ffb reserved 0x00f9c reserved 0x00fbc reserved 0x00fdc syscr1 0x00ffc reserved 0x00f9d reserved 0x00fbd reserved 0x00fdd syscr2 0x00ffd reserved 0x00f9e reserved 0x00fbe reserved 0x00fde syscr3 0x00ffe reserved 0x00f9f reserved 0x00fbf reserved 0x00fdf syscr4/syssr4 0x00fff reserved note 1: do not access reserved addresses by the program. tmp89fw20a page 137 2012/5/18 ra000
9.3 sfr3 (0x00e40 to 0x00eff) table 9-4 sfr3 (0x00e40 to 0x00ebf) address register name address register name address register name address register name 0x00e40 lcdbuf00 0x00e60 reserved 0x00e80 reserved 0x00ea0 tc0drch 0x00e41 lcdbuf01 0x00e61 reserved 0x00e81 reserved 0x00ea1 tc0drdl 0x00e42 lcdbuf02 0x00e62 reserved 0x00e82 reserved 0x00ea2 tc0drdh 0x00e43 lcdbuf03 0x00e63 reserved 0x00e83 reserved 0x00ea3 tc0drel 0x00e44 lcdbuf04 0x00e64 reserved 0x00e84 reserved 0x00ea4 tc0dreh 0x00e45 lcdbuf05 0x00e65 reserved 0x00e85 reserved 0x00ea5 tc0capal 0x00e46 lcdbuf06 0x00e66 reserved 0x00e86 reserved 0x00ea6 tc0capah 0x00e47 lcdbuf07 0x00e67 reserved 0x00e87 reserved 0x00ea7 tc0capbl 0x00e48 lcdbuf08 0x00e68 reserved 0x00e88 reserved 0x00ea8 tc0capbh 0x00e49 lcdbuf09 0x00e69 reserved 0x00e89 reserved 0x00ea9 reserved 0x00e4a lcdbuf10 0x00e6a reserved 0x00e8a reserved 0x00eaa reserved 0x00e4b lcdbuf11 0x00e6b reserved 0x00e8b reserved 0x00eab reserved 0x00e4c lcdbuf12 0x00e6c reserved 0x00e8c reserved 0x00eac reserved 0x00e4d lcdbuf13 0x00e6d reserved 0x00e8d reserved 0x00ead reserved 0x00e4e lcdbuf14 0x00e6e reserved 0x00e8e reserved 0x00eae reserved 0x00e4f lcdbuf15 0x00e6f reserved 0x00e8f reserved 0x00eaf reserved 0x00e50 reserved 0x00e70 reserved 0x00e90 reserved 0x00eb0 reserved 0x00e51 reserved 0x00e71 reserved 0x00e91 reserved 0x00eb1 reserved 0x00e52 reserved 0x00e72 reserved 0x00e92 reserved 0x00eb2 reserved 0x00e53 reserved 0x00e73 reserved 0x00e93 reserved 0x00eb3 reserved 0x00e54 reserved 0x00e74 reserved 0x00e94 reserved 0x00eb4 reserved 0x00e55 reserved 0x00e75 reserved 0x00e95 reserved 0x00eb5 reserved 0x00e56 reserved 0x00e76 reserved 0x00e96 reserved 0x00eb6 reserved 0x00e57 reserved 0x00e77 reserved 0x00e97 reserved 0x00eb7 reserved 0x00e58 reserved 0x00e78 reserved 0x00e98 tc0cr1 0x00eb8 reserved 0x00e59 reserved 0x00e79 reserved 0x00e99 tc0cr2 0x00eb9 reserved 0x00e5a reserved 0x00e7a reserved 0x00e9a tc0cr3 0x00eba reserved 0x00e5b reserved 0x00e7b reserved 0x00e9b tc0dral 0x00ebb reserved 0x00e5c reserved 0x00e7c lcdcr1 0x00e9c tc0drah 0x00ebc reserved 0x00e5d reserved 0x00e7d lcdcr2 0x00e9d tc0drbl 0x00ebd reserved 0x00e5e reserved 0x00e7e reserved 0x00e9e tc0drbh 0x00ebe reserved 0x00e5f reserved 0x00e7f reserved 0x00e9f tc0drcl 0x00ebf reserved note 1: do not access reserved addresses by the program. tmp89fw20a 9. special function registers 9.3 sfr3 (0x00e40 to 0x00eff) page 138 2012/5/18 ra000
table 9-5 sfr3 (0x00ec0 to 0x00eff) address register name address register name address register name address register name 0x00ec0 reserved 0x00ed0 reserved 0x00ee0 reserved 0x00ef0 reserved 0x00ec1 p1lcr 0x00ed1 reserved 0x00ee1 reserved 0x00ef1 reserved 0x00ec2 p2lcr 0x00ed2 p2pud2 0x00ee2 reserved 0x00ef2 reserved 0x00ec3 reserved 0x00ed3 reserved 0x00ee3 reserved 0x00ef3 reserved 0x00ec4 reserved 0x00ed4 reserved 0x00ee4 reserved 0x00ef4 reserved 0x00ec5 p5lcr 0x00ed5 reserved 0x00ee5 reserved 0x00ef5 reserved 0x00ec6 p6lcr 0x00ed6 reserved 0x00ee6 reserved 0x00ef6 reserved 0x00ec7 p7lcr 0x00ed7 reserved 0x00ee7 reserved 0x00ef7 reserved 0x00ec8 reserved 0x00ed8 reserved 0x00ee8 reserved 0x00ef8 reserved 0x00ec9 reserved 0x00ed9 reserved 0x00ee9 reserved 0x00ef9 reserved 0x00eca reserved 0x00eda reserved 0x00eea reserved 0x00efa reserved 0x00ecb reserved 0x00edb reserved 0x00eeb reserved 0x00efb reserved 0x00ecc reserved 0x00edc reserved 0x00eec reserved 0x00efc reserved 0x00ecd reserved 0x00edd reserved 0x00eed reserved 0x00efd reserved 0x00ece reserved 0x00ede reserved 0x00eee reserved 0x00efe reserved 0x00ecf reserved 0x00edf reserved 0x00eef reserved 0x00eff reserved note 1: do not access reserved addresses by the program. tmp89fw20a page 139 2012/5/18 ra000
tmp89fw20a 9. special function registers 9.3 sfr3 (0x00e40 to 0x00eff) page 140 2012/5/18 ra000
10. low power consumption function for peripherals the tmp89fw20a has low power consumption registers (poffcrn) that save power when specific peripher- al functions are unused. each bit of the low power consumption registers can be set to enable or disable each periph- eral function. (n = 0, 1, 2, 3) the basic clock supply to each peripheral function is disabled for power saving, by setting the corresponding bit of the low power consumption registers (poffcrn) to "0". (the disabled peripheral functions become unavail- able.) the basic clock supply to each peripheral function is enabled and the function becomes available by setting the corresponding bit of the low power consumption registers (poffcrn) to "1". after reset, the low power consumption registers (poffcrn) are initialized to "0", and thus the peripheral func- tions are unavailable. when each peripheral function is used for the first time, be sure to set the corresponding bit of the low power consumption registers (poffcrn) to "1" in the initial settings of the program (before operating the control register for the peripheral function). when a peripheral function is operating, the corresponding bit of the low power consumption registers (poffcrn) must not be changed to "0". if it is changed, the peripheral function may operate unexpectedly. tmp89fw20a page 141 2012/5/18 ra001
10.1 control the low power consumption function is controlled by the low power consumption registers (poffcrn). (n = 0, 1, 2, 3) low power consumption register 0 poffcr0 7 6 5 4 3 2 1 0 (0x00f74) bit symbol - - tc023en tc001en - tcc0en tcb0en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tcc0en tcc0 control 0 1 disable enable tcb0en tcb0 control 0 1 disable enable tca0en tca0 control 0 1 disable enable low power consumption register 1 poffcr1 7 6 5 4 3 2 1 0 (0x00f75) bit symbol - - - sbi0en - uart2en uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 sbi0en i2c0 control 0 1 disable enable uart2en uart2 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable low power consumption register 2 poffcr2 7 6 5 4 3 2 1 0 (0x00f76) bit symbol lcden - rtcen - - - sio1en sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 lcden lcd control 0 1 disable enable rtcen rtc control 0 1 disable enable sio1en sio1 control 0 1 disable enable sio0en sio0 control 0 1 disable enable tmp89fw20a 10. low power consumption function for peripherals 10.1 control page 142 2012/5/18 ra001
low power consumption register 3 poffcr3 7 6 5 4 3 2 1 0 (0x00f77) bit symbol - - int5en - int3en int2en int1en int0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 int5en int5 control 0 1 disable enable int3en int3 control 0 1 disable enable int2en int2 control 0 1 disable enable int1en int1 control 0 1 disable enable int0en int0 control 0 1 disable enable tmp89fw20a page 143 2012/5/18 ra001
tmp89fw20a 10. low power consumption function for peripherals 10.1 control page 144 2012/5/18 ra001
11. divider output ( dvo) this function outputs approximately 50% duty pulses that can be used to drive the piezoelectric buzzer or other device. 11.1 configuration figure 11-1 divider output tmp89fw20a page 145 2012/5/18 ra001 dvocr selector dvoen dvo pin dvock 2 a b c y d s fcgck/2 12 or fs/2 5 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 9
11.2 control the divider output is controlled by the divider output control register (dvocr). divider output control register dvocr (0x00038) 7 6 5 4 3 2 1 0 bit symbol - - - - - dv0en dvock read/write r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 dvoen enables/disables the divider output 0: disable the divider output 1: enable the divider output dvock selects the divider output frequency unit: [hz] normal 1/2, idle 1/2 mode slow1/2 sleep1 mode dv9ck=0 dv9ck=1 00 fcgck/2 12 fs/2 5 fs/2 5 01 fcgck/2 11 fs/2 4 fs/2 4 10 fcgck/2 10 fs/2 3 fs/2 3 11 fcgck/2 9 reserved reserved note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: dvocr is cleared to "0" when the operation is switched to stop or idle0/sleep0 mode. dvocr holds the value. note 3: when syscr1 is "1" in the normal 1/2 or idle 1/2 mode, the dvo frequency is subject to some fluctua- tions to synchronize fs and fcgck. note 4: bits 7 to 3 of dvocr are read as "0". tmp89fw20a 11. divider output ( 11.2 control page 146 2012/5/18 ra001
11.3 function select the divider output frequency at dvocr. the divider output is enabled by setting dvocr to "1". then, the rectangular waves selected by dvocr is output from dvo pin. it is disabled by clearing dvovr to "0". and dvo pin keeps "h" level. when the operation is changed to stop or idle0/sleep0 mode, dvocr is cleared to "0" and the dvo pin outputs the "h" level. the divider output source clock operates, regardless of the value of dvocr. therefore, the frequency of the first divider output after dvocr is set to "1" is not the frequency set at dvocr. when the operation is changed to the software, stop or idle0/sleep0 mode is activated and dvocr is cleared to "0", the frequency of the divider output is not the frequency set at dvocr. figure 11-2 divider output timing when the operation is changed from normal mode to slow mode or from slow mode to normal mode, the divider output frequency does not reach the expected value due to synchronization of the gear clock (fcgck) and the low-frequency clock (fs). example:2.441 khz pulse output (fcgck = 10.0 mhz) ld (dvocr), 0y00000100 ;dvock "00", dvoen "1" table 11-1 divider output frequency (example: fcgck = 10.0 mhz, fs = 32.768 khz) dvock divider output frequency [hz] normal 1/2, idle 1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 00 2.441 k 1.024 k 1.024 k 01 4.883 k 2.048 k 2.048 k 10 9.766 k 4.096 k 4.096 k 11 19.531 k reserved reserved tmp89fw20a page 147 2012/5/18 ra001 tbtcr divider output timing chart dvo output
tmp89fw20a 11. divider output ( 11.3 function page 148 2012/5/18 ra001
12. time base timer (tbt) the time base timer generates the time base for key scanning, dynamic display and other processes. it also pro- vides a time base timer interrupt (inttbt) in a certain cycle. 12.1 time base timer 12.1.1 configuration figure 12-1 time base timer configuration 12.1.2 control the time base timer is controlled by the time base timer control register (tbtcr). time base timer control register tbtcr (0x00039) 7 6 5 4 3 2 1 0 bit symbol - - - - tbten tbtck read/write r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 tbten enables/disables the time base tim- er interrupt requests 0: disables generation of interrupt request signals 1: enables generation of interrupt request signals tbtck selects the time base timer inter- rupt frequency unit: [hz] tbtck normal 1/2, idle 1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 000 fcgck/2 22 fs/2 15 fs/2 15 001 fcgck/2 20 fs/2 13 fs/2 13 010 fcgck/2 15 fs/2 8 reserved 011 fcgck/2 13 fs/2 6 reserved 100 fcgck/2 12 fs/2 5 reserved 101 fcgck/2 11 fs/2 4 reserved 110 fcgck/2 10 fs/2 3 reserved 111 fcgck/2 8 reserved reserved note 1: fcgck : gear clock [hz], fs : low-frequency clock [hz] note 2: when the operation is changed to the stop mode, tbtcr is cleared to "0" and tbtcr main- tains the value. note 3: tbtcr should be set when tbtcr is "0". tmp89fw20a page 149 2012/5/18 ra001 falling edge detector tbtcr source clock tbten tbtck 3 inttbt interrupt request selector idle0, sleep0 release request fcgck/2 22 or fs/2 15 fcgck/2 20 or fs/2 13 fcgck/2 15 or fs/2 8 fcgck/2 13 or fs/2 6 fcgck/2 12 or fs/2 5 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8
note 4: when syscr1 is "1" in the normal 1/2 or idle1/2 mode, the interrupt request is subject to some fluctua- tions to synchronize fs and fcgck. note 5: bits 7 to 4 of tbtcr are read as "0". 12.1.3 functions select the source clock frequency for the time base timer by tbtcr. tbtcr should be changed when tbtcr is "0". otherwise, the inttbt interrupt request is generated at un- expected timing. setting tbtcr to "1" causes interrupt request signals to occur at the falling edge of the source clock. when tbtcr is cleared to "0", no interrupt request signal will occur. when the operation is changed to the stop mode, tbtcr is cleared to "0". the source clock of the time base timer operates regardless of the tbtcr value. a time base timer interrupt is generated at the first falling edge of the source clock after a time base timer interrupt request is enabled. therefore, the period from when the time tbtcr is set to "1" to the time when the first interrupt request occurs is shorter than the frequency period set at tbtcr. figure 12-2 time base timer interrupt when the operation is changed from normal mode to slow mode or from slow mode to normal mode, the interrupt request will not occur at the expected timing due to synchronization of the gear clock (fcgck) and the low-frequency clock (fs). it is recommened that the operation mode is changed when tbtcr is "0". table 12-1 time base timer interrupt frequency (example: when fcgck = 10.0 mhz and fs = 32.768 khz) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 000 2.38 1 1 001 9.54 4 4 010 305.18 128 reserved 011 1220.70 512 reserved 100 2441.41 1024 reserved 101 4882.81 2048 reserved 110 9765.63 4096 reserved 111 39062.5 reserved reserved tmp89fw20a 12. time base timer (tbt) 12.1 time base timer page 150 2012/5/18 ra001 source clock time base timer enable interrupt period tbtcr inttbt interrupt request
example:set the time base timer interrupt frequency to fcgck/2 15 [hz] and enable interrupts. di ;imf 0 set (eirl). 5 ;set the interrupt enable register ei ;imf 1 ld (tbtcr), 0y00000010 ;set the interrupt frequency ld (tbtcr), 0y00001010 ;enable generation of interrupt request signals tmp89fw20a page 151 2012/5/18 ra001
tmp89fw20a 12. time base timer (tbt) 12.1 time base timer page 152 2012/5/18 ra001
13. 16-bit timer counter (tca) the tmp89fw20a contains 1 channels of high-performance 16-bit timer counters (tca). table 13-1 sfr address assignment taxdral (address) taxdrah (address) taxdrbl (address) taxdrbh (address) taxmod (address) taxcr (address) taxsr (address) low power consump- tion register timer counter a0 ta0dral (0x0002d) ta0drah (0x0002e) ta0drbl (0x0002f) ta0drbh (0x00030) ta0mod (0x00031) ta0cr (0x00032) ta0sr (0x00033) poffcr0 table 13-2 pin names timer input pin ppg output pin timer counter a0 tca0 pin ppga0 pin tmp89fw20a page 153 2012/5/18 rb002
13.1 configuration figure 13-1 timer counter a0 tmp89fw20a 13. 16-bit timer counter (tca) 13.1 configuration page 154 2012/5/18 rb002 ta0drah selector selector selector selector overflow match detection pulse width measurement mode pulse width measurement mode ppg mode reading and writing of ta0drah reading and writing of ta0dral ta0dral temporary buffer double buffer (16 bits) 16-bit up counter internal bus internal bus 01 0 0 0 1 1 1 comparator inttca0 interrupt request match detection count up count clear clear ta0s ta0drbh ta0mod ta0cr ta0sr decorder ta0ove ppga0 output timer f/f ta0ted edge detection 2 edge detection 1 edge detection 2 edge detection 1 edge detection 1 edge detection 2 edge detection 2 rising falling edge detection 1 falling rising ta0ted 0 1 edge detection 1 edge detection 2 en ta0cap ta0nc fcgck/2 10 or fs/2 3 fcgck/2 6 fcgck/2 2 fcgck/2 e a b c d 1 0 2 ta0ck ta0m ta0dbe ta0ted ta0mett ta0nc ta0ove ta0cap ta0mppg ta0cpfb ta0cpfa ta0ovf ta0s ta0tff y y s0 s1 s selector selector selector window mode event counter mode ppg mode tca0 pin input selector reading and writing of ta0drbh reading and writing of ta0drbl ta0drbl temporary buffer double buffer (16 bits) 01 0 0 0 1 1 1 external trigger input selection auto capture control capture control timer start control external trigger timer mode pulse width measurement mode capture control noise canceller 2 3 comparator ta0dbe ppg mode ta0dbe
13.2 control timer counter a0 is controlled by the low power consumption register (poffcr0), the timer counter a0 mode register (ta0mod), the timer counter a0 control register (ta0cr) and two 16-bit timer a0 registers (ta0dra and ta0drb). low power consumption register 0 poffcr0 7 6 5 4 3 2 1 0 (0x00f74) bit symbol - - tc023en tc001en - tcc0en tcb0en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tcc0en tcc0 control 0 1 disable enable tcb0en tcb0 control 0 1 disable enable tca0en tca0 control 0 1 disable enable tmp89fw20a page 155 2012/5/18 rb002
timer counter a0 mode register ta0mod 7 6 5 4 3 2 1 0 (0x00031) bit symbol ta0dbe ta0ted ta0mcap ta0mett ta0ck ta0m read/write r/w r/w r/w r/w r/w after reset 1 0 0 0 0 0 0 0 ta0dbe double buffer control 0 1 disable the double buffer enable the double buffer ta0ted external trigger input selection 0 1 rising edge/h level falling edge/l level ta0mcap pulse width measurement mode control 0 1 double edge capture single edge capture ta0mett external trigger timer mode control 0 1 trigger start trigger start & stop ta0ck timer counter 1 source clock se- lection normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode syscr1 ="0" syscr1 ="1" 00 fcgck/2 10 fs/2 3 fs/2 3 01 fcgck/2 6 fcgck/2 6 - 10 fcgck/2 2 fcgck/2 2 - 11 fcgck/2 fcgck/2 - ta0m timer counter 1 operation mode selection 000 timer mode 001 timer mode 010 event counter mode 011 ppg output mode (software start) 100 external trigger timer mode 101 window mode 110 pulse width measurement mode 111 note 1: fcgck, gear clock [hz]; fs, low-frequency clock [hz] note 2: set ta0mod in the stopped state (ta0cr="0"). writing to ta0mod is invalid during the operation (ta0cr="1"). tmp89fw20a 13. 16-bit timer counter (tca) 13.2 control page 156 2012/5/18 rb002
timer counter a0 control register ta0cr 7 6 5 4 3 2 1 0 (0x00032) bit symbol ta0ove ta0tff ta0nc - - ta0acap ta0mppg ta0s read/write r/w r/w r/w r r r/w r/w after reset 0 1 0 0 0 0 0 0 ta0ove overflow interrupt control 0 generate no inttca0 interrupt request when the counter overflow oc- curs. 1 generate an inttca0 interrupt request when the counter overflow oc- curs. ta0tff timer f/f control 0 1 clear set ta0nc noise canceller sampling interval setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode 00 no noise canceller no noise canceller 01 fcgck/2 - 10 fcgck/2 2 - 11 fcgck/2 8 fs/2 ta0acap auto capture function 0 1 disable the auto capture enable the auto capture ta0mppg ppg output control 0 1 continuous one-shot ta0s timer counter a start control 0 1 stop & counter clear start note 1: the auto capture can be used only in the timer, event counter, external trigger timer and window modes. note 2: set ta0tff, ta0ove and ta0nc in the stopped state (ta0s="0"). writing is invalid during the operation (ta0s="1"). note 3: when the stop mode is started, the start control (ta0s) is automatically cleared to "0" and the timer stops. set ta0s again to use the timer counter after the release of the stop mode. note 4: when a read instruction is executed on ta0cr, bits 3 and 2 are read as "0". note 5: do not set ta0nc to "01" or "10" when the slow 1/2 or sleep 1 mode is used. setting ta0nc to "01" or "10" stops the noise canceller and no signal is input to the timer. tmp89fw20a page 157 2012/5/18 rb002
timer counter a0 status register ta0sr 7 6 5 4 3 2 1 0 (0x00033) bit symbol ta0ovf - - - - - ta0cpfa ta0cpfb read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 ta0ovf overflow flag 0 1 no overflow has occurred. at least an overflow has occurred. ta0cpfa capture completion flag a 0 no capture operation has been executed. 1 at least a pulse width capture has been executed in the double-edge capture. ta0cpfb capture completion flag b 0 no capture operation has been executed. 1 at least a capture operation has been executed in the single-edge cap- ture. at least a pulse duty width capture has been executed in the double- edge capture. note 1: ta0ovf, ta0cpfa and ta0cpfb are cleared to "0" automatically after ta0sr is read. writing to ta0sr is invalid. note 2: when a read instruction is executed on ta0sr, bits 6 to 2 are read as "0". tmp89fw20a 13. 16-bit timer counter (tca) 13.2 control page 158 2012/5/18 rb002
timer counter a0 register ah ta0drah 15 14 13 12 11 10 9 8 (0x0002e) bit symbol ta0drah read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter a0 register al ta0dral 7 6 5 4 3 2 1 0 (0x0002d) bit symbol ta0dral read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter a0 register bh ta0drbh 15 14 13 12 11 10 9 8 (0x00030) bit symbol ta0drbh read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter a0 register bl ta0drbl 7 6 5 4 3 2 1 0 (0x0002f) bit symbol ta0drbl read/write r/w after reset 1 1 1 1 1 1 1 1 note 1: when a write instruction is executed on ta0dral (ta0drbl), the set value does not become effective immediately, but is temporarily stored in the temporary buffer. subsequently, when a write instruction is executed on the higher-lev- el register, ta0drah (ta0drbh), the 16-bit set values are collectively stored in the double buffer or ta0dral/h. when setting data to the timer counter a0 register, be sure to write the data into the lower level register and the high- er level in this order. note 2: the timer counter a0 register is not writable in the pulse width measurement mode. tmp89fw20a page 159 2012/5/18 rb002
13.3 low power consumption function timer counter a0 has the low power consumption register (poffcr0) that saves power consumption when the timer is not used. setting poffcr0 to "0" disables the basic clock supply to timer counter a0 to save power. note that this makes the timer unusable. setting poffcr0 to "1" enables the basic clock supply to timer coun- ter a0 and allows the timer to operate. after reset, poffcr0 is initialized to "0", and this makes the timer unusable. when using the tim- er for the first time, be sure to set poffcr0 to "1" in the initial setting of the program (before the tim- er control register is operated). do not change poffcr0 to "0" during the timer operation. otherwise timer counter a0 may oper- ate unexpectedly. tmp89fw20a 13. 16-bit timer counter (tca) 13.3 low power consumption function page 160 2012/5/18 rb002
13.4 timer function timer counter a0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse width measurement and programmable pulse generate (ppg) output modes. 13.4.1 timer mode in the timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regular- ly at specified times. 13.4.1.1 setting setting the operation mode selection ta0mod to "000" or "001" activates the timer mode. se- lect the source clock at ta0mod. setting ta0cr to "1" starts the timer operation. after the timer is started, writing to ta0mod and ta0cr becomes invalid. be sure to complete the required mode settings be- fore starting the timer. table 13-3 timer mode resolution and maximum time setting ta0mod source clock [hz] resolution maximum time setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 00 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 6.7s 16s 01 fcgck/2 6 fcgck/2 6 - 6.4s - 419.4ms - 10 fcgck/2 2 fcgck/2 2 - 400ns - 26.2ms - 11 fcgck/2 fcgck/2 - 200ns - 13.1ms - 13.4.1.2 operation setting ta0cr to "1" allows the 16-bit up counter to increment based on the selected internal source clock. when a match between the up-counter value and the value set to timer register a (ta0dra) is detected, an inttca0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter continues counting. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 13.4.1.3 auto capture the latest contents of the up counter can be taken into timer register b (ta0drb) by setting ta0cr to "1" (auto capture function). when ta0cr is "1", the current con- tents of the up counter can be read by reading ta0drbl. ta0drbh is loaded at the same time as ta0drbl is read. therefore, when reading the captured value, be sure to read ta0drbl and ta0drbh in this order. (the capture time is the timing when ta0drbl is read.) the auto capture func- tion can be used whether the timer is operating or stopped. when the timer is stopped, ta0drbl is read as "0x00". ta0drbh keeps the captured value after the timer stops, but it is cleared to "0x00" when ta0drbl is read while the timer is stopped. if the timer is started with ta0cr written to "1", the auto capture is enabled immediate- ly after the timer is started. note 1: the value set to ta0cr cannot be changed at the same time as ta0cr is rewrit- ten from "1" to "0". (this setting is invalid.) tmp89fw20a page 161 2012/5/18 rb002
13.4.1.4 register buffer configuration (1) temporary buffer the tmp89fw20a contains an 8-bit temporary buffer. when a write instruction is executed on ta0dral, the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. subsequently, when a write instruction is executed on ta0drah, the set value is stor- ed into the double buffer or ta0drah. at the same time, the set value in the temporary buffer is stor- ed into the double buffer or ta0dral. (this structure is designed to enable the set values of the low- er-level and higher-level registers simultaneously.) therefore, when setting data to ta0dra, be sure to write the data into ta0dral and ta0drah in this order. see figure 13-1 for the temporary buffer configuration. (2) double buffer in the tmp89fw20a, the double buffer can be used by setting ta0cr. setting ta0cr to "0" disables the double buffer. setting ta0cr to "1" enables the double buffer. see figure 13-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on ta0drah during the timer operation, the set val- ue is first stored into the double buffer, and ta0drah/l are not updated immediately. ta0drah/l compare the up counter value to the last set values. if the values are match- ed, an inttca0 interrupt request is generated and the double buffer set value is stored in ta0drah/l. subsequently, the match detection is executed using a new set value. when a read instruction is executed on ta0drah/l, the double buffer value (the last set value) is read, rather than the ta0drah/l values (the current effective values). when a write instruction is executed on ta0drah/l while the timer is stopped, the set value is immediately stored into both the double buffer and ta0drah/l. - when the double buffer is disabled when a write instruction is executed on ta0drah during the timer operation, the set val- ue is immediately stored into ta0drah/l. subsequently, the match detection is executed using a new set value. if the values set to ta0drah/l are smaller than the up counter value, the match detec- tion is executed using a new set value after the up counter overflows. therefore, the inter- rupt request interval may be longer than the selected time. if that is a problem, enable the dou- ble buffer. when a write instruction is executed on ta0drah/l while the timer is stopped, the set value is immediately stored into ta0drah/l. tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 162 2012/5/18 rb002
figure 13-2 timer mode timing chart tmp89fw20a page 163 2012/5/18 rb002 source clock counter timer start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah reflected by an interrupt reflected at the same time as data is written into ta0drah while the timer is stopped counter clear inttca0 interrupt request 234 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod when the double buffer is disabled (ta0mod=?0?) source clock counter timer start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r counter clear inttca0 interrupt request 234 mn-1 mn 01 mn 01 23 ta0drah ta0cr s r n temporary buffer (8 bits) s n temporary buffer (8 bits) s mn double buffer (16 bits) rs match detection match detection counter clear 01 mn-1 rs rs-1 ta0mod when the double buffer is enabled (ta0mod=?1?)
figure 13-3 timer mode timing chart (auto capture) tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 164 2012/5/18 rb002 source clock counter timer start ta0drbh is updated when ta0drbl is read read ta0drbl read ta0drbh read value 00h read value 00h ta0drbl ta0drbh ta0cr timer stop 18fd 0000 0001 0002 18fe 18ff 1900 1901 1902 1903 1904 1905 1906 0000 fd 00 01 00 18 02 fe ff 00 01 02 03 04 05 06 00 00 ta0mod read value feh read value 18h read value 00h read value 00h read value 18h
13.4.2 external trigger timer mode in the external trigger timer mode, the up counter starts counting when it is triggered by the input to the tca0 pin. 13.4.2.1 setting setting the operation mode selection ta0mod to "100" activates the external trigger timer mode. select the source clock at ta0mod. select the trigger edge at the trigger edge input selection ta0mod. setting ta0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode before- hand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 13.4.2.2 operation after the timer is started, when the selected trigger edge is input to the tca0 pin, the up counter incre- ments according to the selected source clock. when a match between the up counter value and the value set to timer register a (ta0dra) is detected, an inttca0 interrupt request is generated and the up coun- ter is cleared to "0x0000". after being cleared, the up counter continues counting. when ta0mod is "1" and the edge opposite to the selected trigger edge is detected, the up counter stops counting and is cleared to "0x0000". subsequently, when the selected trigger edge is detec- ted, the up counter restarts counting. in this mode, an interrupt request can be generated by detecting that the input pulse exceeds a certain pulse width. if ta0mod is "0", the detection of the selec- ted edge and the opposite edge is ignored during the period from the detection of the specified trigger edge and the start of counting through until the match detection. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 13.4.2.3 auto capture refer to "13.4.1.3 auto capture". 13.4.2.4 register buffer configuration refer to "13.4.1.4 register buffer configuration". tmp89fw20a page 165 2012/5/18 rb002
figure 13-4 external trigger timer timing chart tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 166 2012/5/18 rb002 source clock counter timer start counting start edge is invalid during counting counting start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear inttca0 interrupt request 23 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod tca0 pin input when the trigger is started (ta0mod=?0?) timer start counting start counting start counting start counting stop 1 0 n m ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear counter clear inttca0 interrupt request 23 mn-1 mn 01 rs 01 1 20 0 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod when the trigger is started and stopped (ta0mod=?1?) edge is invalid during counting source clock counter write to ta0dral write to ta0drah tca0 pin input
13.4.3 event counter mode in the event counter mode, the up counter counts up at the edge of the input to the tca0 pin. 13.4.3.1 setting setting the operation mode selection ta0mod to "010" activates the event counter mode. set the trigger edge at the external trigger input selection ta0mod. setting ta0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge for count- ing up. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode before- hand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 13.4.3.2 operation after the event counter mode is started, when the selected trigger edge is input to the tca0 pin, the up counter increments. when a match between the up counter value and the value set to timer register a (ta0dra) is detec- ted, an inttca0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter continues counting and counts up at each edge of the input to the tca0 pin. set- ting ta0cr to "0" during the operation causes the up counter to stop counting and be cleared to "0x0000". the maximum frequency to be supplied is fcgck/2 [hz] (in the normal 1/2 or idle 1/2 mode) or fs/ 2 [hz] (in the slow 1/2 or sleep 1 mode), and a pulse width of two machine cycles or more is re- quired at both the "h" and "l" levels. 13.4.3.3 auto capture refer to "13.4.1.3 auto capture". 13.4.3.4 register buffer configuration refer to "13.4.1.4 register buffer configuration". tmp89fw20a page 167 2012/5/18 rb002
figure 13-5 event count mode timing chart tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 168 2012/5/18 rb002 tca0 pin input counter timer start when the rising edge is selected (ta0mod=?0?) 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear inttca0 interrupt request 23 4 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1
13.4.4 window mode in the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tca0 pin (window pulse) and the internal clock. 13.4.4.1 setting setting the operation mode selection ta0mod to "101" activates the window mode. select the source clock at ta0mod. select the window pulse level at the trigger edge input selection ta0mod. setting ta0mod to "0" enables counting up as long as the window pulse is at the "h" level. setting ta0mod to "1" enables counting up as long as the window pulse is at the "l" level. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode before- hand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 13.4.4.2 operation after the operation is started, when the level selected at ta0mod is input to the tca0 pin, the up counter increments according to the source clock selected at ta0mod. when a match between the up counter value and the value set to timer register a (ta0dra) is detected, an in- ttca0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. the maximum frequency to be supplied must be slow enough for the program to analyze the count val- ue. define a frequency pulse that is sufficiently lower than the programmed internal source clock. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 13.4.4.3 auto capture refer to "13.4.1.3 auto capture". 13.4.4.4 register buffer configuration refer to "13.4.1.4 register buffer configuration". tmp89fw20a page 169 2012/5/18 rb002
figure 13-6 window mode timing chart tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 170 2012/5/18 rb002 source clock counter timer start count in the period of h level count in the period of h level 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write m reflected by writing to ta0drah counter clear inttca0 interrupt request 25 46 456 3 mn-1 mn 1 02 0 3 ta0drah ta0cr timer stop ta0mod tca0 pin input during the h-level counting (ta0mod=?0?)
13.4.5 pulse width measurement mode in the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the in- put to the tca0 pin and measures the input pulse width based on the internal clock. 13.4.5.1 setting setting the operation mode selection ta0mod to "110" activates the pulse width measure- ment mode. select the source clock at ta0mod. select the trigger edge at the trigger edge input selection ta0mod. setting ta0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge as a trig- ger to start the capture. the operation after capturing is determined by the pulse width measurement mode control ta0mod. setting ta0mod to "0" selects the double-edge capture. setting ta0mod to "1" selects the single-edge capture. the operation to be executed in case of an overflow of the up counter can be selected at the overflow in- terrupt control ta0cr. setting ta0ove to "1" makes an inttca0 interrupt request occur in case of an overflow. setting ta0ove to "0" makes no inttca0 interrupt request occur in case of an overflow. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode before- hand in port settings. the operation is started by setting ta0cr to "1". in this time, ta0dra and ta0drb regis- ter are initialized to "0x0000". after the timer is started, writing to ta0mod and ta0cr is dis- abled. be sure to complete the required mode settings before starting the timer. 13.4.5.2 operation after the timer is started, when the selected trigger edge (start edge) is input to the tca0 pin, in- ttca0 interrupt request is generated, and then the up counter increments according to the selected source clock. subsequently, when the edge opposite to the selected edge is detected, the up counter value is captured into ta0drb, an inttca0 interrupt request is generated, and ta0sr is set to "1". depending on the ta0mod setting, the operation differs as follows: ? double-edge capture (when ta0mod is "0") the up counter continues counting up after the edge opposite to the selected edge is detec- ted. subsequently, when the selected trigger edge is input, the up counter value is captured in- to ta0dra, an inttca0 interrupt request is generated, and ta0sr is set to "1". at this time, the up counter is cleared to "0x0000". ? single-edge capture (when ta0mod is "1") the up counter stops counting up and is cleared to "0x0000" when the edge opposite to the se- lected edge is detected. subsequently, when the start edge is input, inttca0 interrupt request is generated, and then the up counter restarts increment. when the up counter overflows during capturing, the overflow flag ta0sr is set to "1". at this time, an inttca0 interrupt request occurs if the overflow interrupt control ta0cr is set to "1". the capture completion flags (ta0sr and the overflow flag (ta0sr) are cleared to "0" automatically when ta0sr is read. tmp89fw20a page 171 2012/5/18 rb002
the captured value must be read from ta0drb (and also from ta0dra for the double-edge capture) before the next trigger edge is detected. if the captured value is not read, it becomes undefined. ta0dra and ta0drb must be read by using a 16-bit access instruction. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". note 1: after the timer is started, if the edge opposite to the selected trigger edge is detected first, no cap- ture is executed and no inttca0 interrupt request occurs. in this case, the capture starts when the se- lected trigger edge is detected next. figure 13-7 pulse width measurement mode timing chart tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 172 2012/5/18 rb002 source clock counter counter clear counter clear counter clear counter clear timer start count start count start after the timer is started, if the falling edge is detected first, no interrupt occurs. 1 0 ta0drbh, l inttca0 interrupt request 0 24 3 3 mn-1 mn 1 0 mn 20 ta0cr timer stop ta0mod tca0 pin input single-edge capture (ta0mod=?1?) after the timer is started, if the falling edge is detected first, no interrupt occurs. source clock counter timer start 1 0 ta0drbh, l inttca0 interrupt request 0 24 3 mn-1 mn mn+1 st-1 st mn 0 012 0 ta0drah, l st ta0cr timer stop ta0mod tca0 pin input double-edge capture (ta0mod=?0?) ta0sr ta0sr ta0sr read ta0drb read ta0dra read ta0sr read ta0sr read ta0sr ta0sr read ta0sr read ta0sr read ta0drb read
13.4.5.3 capture process figure 13-8 shows an example of the capture process for inttca0 interrupt subroutine. the capture edge or overflow state can be easily judged by status register (ta0sr). figure 13-8 example of capture process tmp89fw20a page 173 2012/5/18 rb002 reti ta0sr ta0sr ta0sr read error handling ta0drb read 1 overflow interrupt process for single-edge capture 0 (no overflow) 1 (capture) 0 no capture inttca0 interrupt subroutine inttca0 interrupt subroutin reti ta0sr ta0sr ta0sr read error handling ta0drb read 1 overflow interrupt process for double-edge capture 0 (no overflow) 1 (capture) 0 no capture 1 (capture) 0 no capture ta0sr ta0dra read capture value handling capture value handling
13.4.6 programmable pulse generate (ppg) mode in the ppg output mode, an arbitrary duty pulse is output by two timer registers. 13.4.6.1 setting setting the operation mode selection ta0mod to "011" activates the ppg output mode. se- lect the source clock at ta0mod. select continuous or one-shot ppg output at ta0cr. set the ppg output cycle at ta0dra and set the time until the output is reversed first at ta0drb. be sure to set register values so that ta0dra is larger than ta0drb. note that this mode uses the ppga0 pin. the ppga0 pin must be set to the output mode beforehand in port settings. set the initial state of the ppga0 pin at the timer flip-flop ta0cr. setting ta0cr to "1" selects the "h" level as the initial state of the ppga0 pin. setting ta0cr to "0" selects the "l" level as the initial state of the ppga0 pin. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.6.2 operation after the timer is started, the up counter increments . when a match between the up counter value and the value set to timer register b (ta0drb) is detec- ted, the ppga0 pin is changed to the "h" level if ta0cr is "0", or the ppga0 pin is changed to the "l" level if ta0cr is "1". subsequently, the up counter continues counting. when a match between the up counter value and the val- ue set to timer register a (ta0dra) is detected, the ppga0 pin is changed to the "l" level if ta0cr is "0", or the ppga0 pin is changed to the "h" level if ta0cr is "1". at this time, an inttca0 interrupt request occurs. if the ppg output control ta0cr is set to "1" (one-shot), ta0cr is automatically cleared to "0" and the timer stops. if ta0cr is set to "0" (continuous), the up counter is cleared to "0x0000" and continues counting and ppg output. when ta0cr is set to "0" (including the auto stop by the one-shot op- eration) during the ppg output, the ppga0 pin returns to the level set in ta0cr. ta0cr can be changed during the operation. changing ta0cr from "1" to "0" during the operation cancels the one-shot operation and enables the continuous operation. chang- ing ta0cr from "0" to "1" during the operation clears ta0cr to "0" and stops the timer automatically after the current pulse output is completed. timer registers a and b can be set to the double buffer. setting ta0cr to "1" enables the double buffer. when the values set to ta0dra and ta0drb are changed during the ppg output with the double buffer enabled, the writing to ta0dra and ta0drb will not immediately become effective but will become effective when a match between ta0dra and the up counter is detected. if the double buf- fer is disabled, the writing to ta0dra and ta0drb will become effective immediately. if the written val- ue is smaller than the up counter value, the up counter overflows. after a cycle, the counter match proc- ess is executed to reverse the output. tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 174 2012/5/18 rb002
13.4.6.3 register buffer configuration (1) temporary buffer the tmp89fw20a contains an 8-bit temporary buffer. when a write instruction is executed on ta0dral (ta0drbl), the data is first stored into this temporary buffer, whether the double buf- fer is enabled or disabled. subsequently, when a write instruction is executed on ta0drah (ta0drbh), the set value is stored into the double buffer or ta0drah (ta0drbh). at the same time, the set value in the temporary buffer is stored into the double buffer or ta0dral (ta0drbl). (this structure is designed to enable the set values of the lower-level register and the higher-level register simultaneously.) therefore, when setting data to ta0dra (ta0drb), be sure to write the data into ta0dral and ta0drah (ta0drbl and ta0drbh) in this order. see figure 13-1 for the temporary buffer configuration. (2) double buffer in the tmp89fw20a, the double buffer can be used by setting ta0cr. setting ta0cr to "0" disables the double buffer. setting ta0cr to "1" enables the double buffer. see figure 13-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on ta0drah (ta0drbh) during the timer opera- tion, the set value is first stored into the double buffer, and ta0drah/l are not updated im- mediately. ta0drah/l (ta0drbh/l) compare the last set values to the counter value. if a match is detected, an inttca0 interrupt request is generated and the double buffer set value is stored into ta0drah/l (ta0drbh/l). subsequently, the match detection is executed using a new set value. when a read instruction is executed on ta0drah/l (ta0drbh/l), the double buffer value (the last set value) is read, not the ta0drah/l (ta0drbh/l) values (the current ef- fective values). when a write instruction is executed on ta0drah/l (ta0drbh/l) while the timer is stopped, the set value is immediately stored into both the double buffer and ta0drah/l (ta0drbh/l). - when the double buffer is disabled when a write instruction is executed on ta0drah (ta0drbh) during the timer opera- tion, the set value is immediately stored in ta0drah/l (ta0drbh/l). subsequently, the match detection is executed using a new set value. if the values set to ta0drah/l (ta0drbh/l) are smaller than the up counter value, the up counter overflows and the match detection is executed using a new set value. as a re- sult, the output pulse width may be longer than the set time. if that is a problem, enable the double buffer. when a write instruction is executed on ta0drah/l (ta0drbh/l) while the timer is stopped, the set value is immediately stored into ta0drah/l (ta0drbh/l). tmp89fw20a page 175 2012/5/18 rb002
figure 13-9 ppg mode timing chart tmp89fw20a 13. 16-bit timer counter (tca) 13.4 timer function page 176 2012/5/18 rb002 source clock counter timer start 1 0 n m m (duty pulse) m (duty pulse) n (1 cycle) r (duty pulse) s (1 cycle) s r write to ta0dral, h write to ta0drbl, h ta0dral, h match detection match detection write n write s write m write r becomes the level set at ta0tff when the timer is stopped reflected by an interrupt request returns to the level set at ta0tff counter clear inttca interrupt request 2m 1 m+1 n 00 ta0drbl, h ta0cr timer stop match detection match detection counter clear 2r 1 r+1 r r+1 s 0 match detection ta0mod ppg0 pin output continuous (ta0cr=?0?) double buffer (ta0mod=?1?) r (duty pulse) source clock counter timer start 1 0 n m n (1 cycle) write to ta0dral, h write to ta0drbl, h ta0dral, h match detection match detection write n write m becomes the level set at ta0tff when the timer is stopped returns to the level set at ta0tff counter clear inttca interrupt request 2m m+1 n 0 ta0drbl, h ta0cr timer stops automatically ta0mod ppg0 pin output one-shot (ta0cr=?1?)
13.5 noise canceller the digital noise canceller can be used in the operation modes that use the tca0 pin. 13.5.1 setting when the digital noise canceller is used, the input level is sampled at the sampling intervals set at ta0cr. when the same level is detected three times consecutively, the level of the input to the tim- er is changed. setting ta0cr to any values than "00" allows the noise canceller to start operation, regardless of the ta0cr value. when the noise canceller is used, allow the timer to start after a period of time that is equal to four times the sampling interval after ta0cr is set has elapsed. this stabilizes the input signal. set ta0cr while the timer is stopped (ta0cr = "0"). when ta0cr is "1", writing is ignored. in the slow 1/2 or sleep 1 mode, setting ta0cr to "11" selects fs/2 as the source clock for the operation. setting ta0cr to "00" disables the noise canceller. setting ta0cr to "01" or "10" disables the tca0 pin input. table 13-4 noise cancel time ( fcgck = 10 [mhz] ) ta0nc sampling interval time removed as noise time regarded as signal 00 none - - 01 200 ns (2/fcgck) 600 ns or less 800 ns or more 10 400 ns (4/fcgck) 1.2 s or less 1.6 s or more 11 25.6 s (256/fcgck) 76.8 s or less 102.4 s or more tmp89fw20a page 177 2012/5/18 rb002
tmp89fw20a 13. 16-bit timer counter (tca) 13.5 noise canceller page 178 2012/5/18 rb002
14. 16-bit timer counter (tcb) the tmp89fw20a contains one channel of high-performance 16-bit timer counter (tcb0). table 14-1 sfr address assignment tbxdral (address) tbxdrah (address) tbxdrbl (address) tbxdrbh (address) tbxmod (address) tbxcr (address) tbxsr (address) low power consump- tion register timer counter b0 tb0dral (0x00fa8) tb0drah (0x00fa9) tb0drbl (0x00faa) tb0drbh (0x00fab) tb0mod (0x00fac) tb0cr (0x00fad) tb0sr (0x00fae) poffcr0 table 14-2 pin names timer input pin ppg output pin timer counter b0 tcb0 pin ppgb0 pin tmp89fw20a page 179 2012/5/18 ra000
14.1 configuration figure 14-1 timer counter b0 tmp89fw20a 14. 16-bit timer counter (tcb) 14.1 configuration page 180 2012/5/18 ra000 tb0drah selector selector selector selector overflow match detection pulse width measurement mode pulse width measurement mode ppg mode reading and writing of tb0drah reading and writing of tb0dral tb0dral temporary buffer double buffer (16 bits) 16-bit up counter internal bus internal bus 01 0 0 0 1 1 1 comparator inttcb0 interrupt request match detection count up count clear clear tb0s tb0drbh tb0mod tb0cr tb0sr decorder tb0dbe tb0dbe tb0ove ppgb0 output timer f/f tb0ted edge detection 2 edge detection 1 edge detection 2 edge detection 1 edge detection 1 edge detection 2 edge detection 2 rising falling edge detection 1 falling rising tb0ted 0 1 edge detection 1 edge detection 2 en tb0acap tb0nc fcgck/2 10 or fs/2 3 fcgck/2 6 fcgck/2 2 fcgck/2 e a b c d b a 2 tb0ck tb0m tb0dbe tb0ted tb0mett tb0nc tb0ove tb0acap tb0mppg tb0cpfb tb0cpfa tb0ovf tb0s tb0tff y y s0 s1 s selector selector selector event counter mode ppg mode ppg mode tcb0 pin input selector reading and writing of tb0drbh reading and writing of tb0drbl tb0drbl temporary buffer double buffer (16 bits) 01 0 0 0 1 1 1 external trigger input selection auto capture control counter read control capture control timer start control external trigger timer mode pulse width measurement mode capture control noise canceller 2 3 comparator
14.2 control timer counter b0 is controlled by the low power consumption register (poffcr01234), the timer counter b0 mode register (tb0mod), the timer counter b0 control register (tb0cr) and two 16-bit timer b0 registers (tb0dra and tb0drb). low power consumption register 0 poffcr0 7 6 5 4 3 2 1 0 (0x00f74) bit symbol - - tc023en tc001en - tcc0en tcb0en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tcc0en tcc0 control 0 1 disable enable tcb0en tcb0 control 0 1 disable enable tca0en tca0 control 0 1 disable enable tmp89fw20a page 181 2012/5/18 ra000
timer counter b0 mode register tb0mod 7 6 5 4 3 2 1 0 (0x00fac) bit symbol tb0dbe tb0ted tb0mcap tb0mett tb0ck tb0m read/write r/w r/w r/w r/w r/w after reset 1 0 0 0 0 0 0 0 tb0dbe double buffer control (tb0dra and tb0drb registers) 0 1 disable the double buffer enable the double buffer tb0ted external trigger input selection 0 1 rising edge/h level falling edge/l level tb0mcap pulse width measurement mode control 0 1 double edge capture single edge capture tb0mett external trigger timer mode control 0 1 trigger start trigger start & stop tb0ck timer counter 1 source clock se- lection normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode syscr1 ="0" syscr1 ="1" 00 fcgck/2 10 fs/2 3 fs/2 3 01 fcgck/2 6 fcgck/2 6 - 10 fcgck/2 2 fcgck/2 2 - 11 fcgck/2 fcgck/2 - tb0m timer counter 1 operation mode selection 000 timer mode 001 reserved 010 event counter mode 011 ppg output mode (software start) 100 external trigger timer mode 101 window mode 110 pulse width measurement mode 111 ppg output mode (external trigger start) note 1: fcgck, gear clock [hz]; fs, low-frequency clock [hz] note 2: set tb0mod in the stopped state (tb0cr="0"). writing to tb0mod is invalid during the operation (tb0cr="1"). tmp89fw20a 14. 16-bit timer counter (tcb) 14.2 control page 182 2012/5/18 ra000
timer counter b0 control register tb0cr 7 6 5 4 3 2 1 0 (0x00fad) bit symbol tb0ove tb0tff tb0nc - - tb0acap tb0mppg tb0s read/write r/w r/w r/w r w r/w r/w after reset 0 1 0 0 0 0 0 0 tb0ove overflow interrupt control 0 generate no inttcb0 interrupt request when the counter overflow oc- curs. 1 generate an inttcb0 interrupt request when the counter overflow oc- curs. tb0tff timer f/f control 0 1 clear set tb0nc noise canceller sampling interval setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode 00 no noise canceller no noise canceller 01 fcgck/2 - 10 fcgck/2 2 - 11 fcgck/2 8 fs/2 tb0acap auto capture function 0 1 disable the auto capture enable the auto capture tb0mppg ppg output control 0 1 continuous one-shot tb0s timer counter a start control 0 1 stop & counter clear start note 1: the auto capture can be used only in the timer, event counter, external trigger timer and window modes. note 2: set tb0tff, tb0ove and tb0nc in the stopped state (tb0s="0"). writing is invalid during the operation (tb0s="1"). note 3: when the stop mode is started, the start control (tb0s) is automatically cleared to "0" and the timer stops. set tb0s again to use the timer counter after the release of the stop mode. note 4: when a read instruction is executed on tb0cr, bits 3 and 2 are read as "0". note 5: do not set tb0nc to "01" or "10" when the slow 1/2 or sleep 1 mode is used. setting tb0nc to "01" or "10" stops the noise canceller and no signal is input to the timer. tmp89fw20a page 183 2012/5/18 ra000
timer counter b0 status register tb0sr 7 6 5 4 3 2 1 0 (0x00fae) bit symbol tb0ovf - - - - - tb0cpfa tb0cpfb read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 tb0ovf overflow flag 0 1 no overflow has occurred. at least an overflow has occurred. tb0cpfa capture completion flag a 0 no capture operation has been executed. 1 at least a pulse width capture has been executed in the double-edge capture. tb0cpfb capture completion flag b 0 no capture operation has been executed. 1 at least a capture operation has been executed in the single-edge cap- ture. at least a pulse duty width capture has been executed in the double- edge capture. note 1: tb0ovf, tb0cpfa and tb0cpfb are cleared to "0" automatically after tb0sr is read. writing to tb0sr is invalid. note 2: when a read instruction is executed on tb0sr, bits 6 to 3 are read as "0". timer counter b0 register ah tb0drah 15 14 13 12 11 10 9 8 (0x00fa9) bit symbol tb0drah read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter b0 register al tb0dral 7 6 5 4 3 2 1 0 (0x00fa8) bit symbol tb0dral read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter b0 register bh tb0drbh 15 14 13 12 11 10 9 8 (0x00fab) bit symbol tb0drbh read/write r/w after reset 1 1 1 1 1 1 1 1 timer counter b0 register bl tb0drbl 7 6 5 4 3 2 1 0 (0x00faa) bit symbol tb0drbl read/write r/w after reset 1 1 1 1 1 1 1 1 note 1: when a write instruction is executed on tb0dral (tb0drbl), the set value does not become effective imme- diately, but is temporarily stored in the temporary buffer. subsequently, when a write instruction is executed on the higher-level register, tb0drah (tb0drbh), the 16-bit set values are collectively stored in the double buf- fer or tb0dral/h. when setting data to the timer counter b0 register, be sure to write the data into the lower level register and the higher level in this order. note 2: the timer counter b0 register is not writable in the pulse width measurement mode. tmp89fw20a 14. 16-bit timer counter (tcb) 14.2 control page 184 2012/5/18 ra000
14.3 low power consumption function timer counter b0 has the low power consumption register (poffcr0) that saves power consumption when the timer is not used. setting poffcr0 to "0" disables the basic clock supply to timer counter b0 to save power. note that this makes the timer unusable. setting poffcr0 to "1" enables the basic clock supply to timer coun- ter b0 and allows the timer to operate. after reset, poffcr0 is initialized to "0", and this makes the timer unusable. when using the tim- er for the first time, be sure to set poffcr0 to "1" in the initial setting of the program (before the tim- er control register is operated). do not change poffcr0 to "0" during the timer operation. otherwise timer counter b0 may oper- ate unexpectedly. tmp89fw20a page 185 2012/5/18 ra000
14.4 timer function timer counter b0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse width measurement and programmable pulse generate (ppg) output modes. 14.4.1 timer mode in the timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regular- ly at specified times. 14.4.1.1 setting setting the operation mode selection tb0mod to "000" or "001" activates the timer mode. se- lect the source clock at tb0mod. setting tb0cr to "1" starts the timer operation. after the timer is started, writing to tb0mod and tb0cr becomes invalid. be sure to complete the required mode settings be- fore starting the timer. table 14-3 timer mode resolution and maximum time setting tb0mod source clock [hz] resolution maximum time setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 00 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 6.7s 16s 01 fcgck/2 6 fcgck/2 6 - 6.4s - 419.4ms - 10 fcgck/2 2 fcgck/2 2 - 400ns - 26.2ms - 11 fcgck/2 fcgck/2 - 200ns - 13.1ms - 14.4.1.2 operation setting tb0cr to "1" allows the 16-bit up counter to increment based on the selected internal source clock. when a match between the up-counter value and the value set to timer register a (tb0dra) is detected, an inttcb0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter continues counting. setting tb0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 14.4.1.3 auto capture the latest contents of the up counter can be taken into timer register b (tb0drb) by setting tb0cr to "1" (auto capture function). when tb0cr is "1", the current con- tents of the up counter can be read by reading tb0drbl. tb0drbh is loaded at the same time as tb0drbl is read. therefore, when reading the captured value, be sure to read tb0drbl and tb0drbh in this order. (the capture time is the timing when tb0drbl is read.) the auto capture func- tion can be used whether the timer is operating or stopped. when the timer is stopped, tb0drbl is read as "0x00". tb0drbh keeps the captured value after the timer stops, but it is cleared to "0x00" when tb0drbl is read while the timer is stopped. if the timer is started with tb0cr written to "1", the auto capture is enabled immediate- ly after the timer is started. note 1: the value set to tb0cr cannot be changed at the same time as tb0cr is rewrit- ten from "1" to "0". (this setting is invalid.) tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 186 2012/5/18 ra000
14.4.1.4 register buffer configuration (1) temporary buffer the tmp89fw20a contains an 8-bit temporary buffer. when a write instruction is executed on tb0dral, the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. subsequently, when a write instruction is executed on tb0drah, the set value is stor- ed into the double buffer or tb0drah. at the same time, the set value in the temporary buffer is stor- ed into the double buffer or tb0dral. (this structure is designed to enable the set values of the low- er-level and higher-level registers simultaneously.) therefore, when setting data to tb0dra, be sure to write the data into tb0dral and tb0drah in this order. see figure 14-1 for the temporary buffer configuration. (2) double buffer in the tmp89fw20a, the double buffer can be used by setting tb0cr. setting tb0cr to "0" disables the double buffer. setting tb0cr to "1" enables the double buffer. see figure 14-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on tb0drah during the timer operation, the set val- ue is first stored into the double buffer, and tb0drah/l are not updated immediately. tb0drah/l compare the up counter value to the last set values. if the values are match- ed, an inttcb0 interrupt request is generated and the double buffer set value is stored in tb0drah/l. subsequently, the match detection is executed using a new set value. when a read instruction is executed on tb0drah/l, the double buffer value (the last set value) is read, rather than the tb0drah/l values (the current effective values). when a write instruction is executed on tb0drah/l while the timer is stopped, the set value is immediately stored into both the double buffer and tb0drah/l. - when the double buffer is disabled when a write instruction is executed on tb0drah during the timer operation, the set val- ue is immediately stored into tb0drah/l. subsequently, the match detection is executed using a new set value. if the values set to tb0drah/l are smaller than the up counter value, the match detec- tion is executed using a new set value after the up counter overflows. therefore, the inter- rupt request interval may be longer than the selected time. if that is a problem, enable the dou- ble buffer. when a write instruction is executed on tb0drah/l while the timer is stopped, the set value is immediately stored into tb0drah/l. tmp89fw20a page 187 2012/5/18 ra000
figure 14-2 timer mode timing chart tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 188 2012/5/18 ra000 source clock counter timer start 1 0 n m write to tb0dral write to tb0drah tb0dral match detection write n write s write m write r reflected by writing to tb0drah reflected by writing to tb0drah reflected by an interrupt reflected at the same time as data is written into tb0drah while the timer is stopped counter clear inttcb0 interrupt request 234 mn-1 mn 01 rs 01 220 3 tb0drah tb0cr s r timer stop match detection counter clear rs-1 tb0mod when the double buffer is disabled (tb0mod=?0?) source clock counter timer start 1 0 n m write to tb0dral write to tb0drah tb0dral match detection write n write s write m write r counter clear inttcb0 interrupt request 234 mn-1 mn 01 mn 01 23 tb0drah tb0cr s r n temporary buffer (8 bits) s n temporary buffer (8 bits) s mn double buffer (16 bits) rs match detection match detection counter clear 01 mn-1 rs rs-1 tb0mod when the double buffer is enabled (tb0mod=?1?)
figure 14-3 timer mode timing chart (auto capture) tmp89fw20a page 189 2012/5/18 ra000 source clock counter timer start tb0drbh is updated when tb0drbl is read read tb0drbl read tb0drbh read value 00h read value 00h tb0drbl tb0drbh tb0cr timer stop 18fd 0000 0001 0002 18fe 18ff 1900 1901 1902 1903 1904 1905 1906 0000 fd 00 01 00 18 02 fe ff 00 01 02 03 04 05 06 00 00 tb0mod read value feh read value 18h read value 00h read value 00h read value 18h
14.4.2 external trigger timer mode in the external trigger timer mode, the up counter starts counting when it is triggered by the input to the tcb0 pin. 14.4.2.1 setting setting the operation mode selection tb0mod to "100" activates the external trigger timer mode. select the source clock at tb0mod. select the trigger edge at the trigger edge input selection tb0mod. setting tb0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge. note that this mode uses the tb0 input pin, and the tcb0 pin must be set to the input mode before- hand in port settings. the operation is started by setting tb0cr to "1". after the timer is started, writing to tb0mod and tb0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 14.4.2.2 operation after the timer is started, when the selected trigger edge is input to the tcb0 pin, the up counter incre- ments according to the selected source clock. when a match between the up counter value and the value set to timer register a (tb0dra) is detected, an inttcb0 interrupt request is generated and the up coun- ter is cleared to "0x0000". after being cleared, the up counter continues counting. when tb0mod is "1" and the edge opposite to the selected trigger edge is detected, the up counter stops counting and is cleared to "0x0000". subsequently, when the selected trigger edge is detec- ted, the up counter restarts counting. in this mode, an interrupt request can be generated by detecting that the input pulse exceeds a certain pulse width. if tb0mod is "0", the detection of the selec- ted edge and the opposite edge is ignored during the period from the detection of the specified trigger edge and the start of counting through until the match detection. setting tb0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 14.4.2.3 auto capture refer to "14.4.1.3 auto capture". 14.4.2.4 register buffer configuration refer to "14.4.1.4 register buffer configuration". tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 190 2012/5/18 ra000
figure 14-4 external trigger timer timing chart tmp89fw20a page 191 2012/5/18 ra000 source clock counter timer start counting start edge is invalid during counting counting start 1 0 n m write to tb0dral write to tb0drah tb0dral match detection write n write s write m write r reflected by writing to tb0drah reflected by writing to tb0drah counter clear inttcb0 interrupt request 23 mn-1 mn 01 rs 01 220 3 tb0drah tb0cr s r timer stop match detection counter clear rs-1 tb0mod tcb0 pin input when the trigger is started (tb0mod=?0?) timer start counting start counting start counting start counting stop 1 0 n m tb0dral match detection write n write s write m write r reflected by writing to tb0drah reflected by writing to tb0drah counter clear counter clear inttcb0 interrupt request 23 mn-1 mn 01 rs 01 1 20 0 tb0drah tb0cr s r timer stop match detection counter clear rs-1 tb0mod when the trigger is started and stopped (tb0mod=?1?) edge is invalid during counting source clock counter write to tb0dral write to tb0drah tcb0 pin input
14.4.3 event counter mode in the event counter mode, the up counter counts up at the edge of the input to the tcb0 pin. 14.4.3.1 setting setting the operation mode selection tb0mod to "010" activates the event counter mode. set the trigger edge at the external trigger input selection tb0mod. setting tb0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge for count- ing up. note that this mode uses the tb0 input pin, and the tcb0 pin must be set to the input mode before- hand in port settings. the operation is started by setting tb0cr to "1". after the timer is started, writing to tb0mod and tb0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 14.4.3.2 operation after the event counter mode is started, when the selected trigger edge is input to the tcb0 pin, the up counter increments. when a match between the up counter value and the value set to timer register a (tb0dra) is detec- ted, an inttcb0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter continues counting and counts up at each edge of the input to the tcb0 pin. set- ting tb0cr to "0" during the operation causes the up counter to stop counting and be cleared to "0x0000". the maximum frequency to be supplied is fcgck/2 [hz] (in the normal 1/2 or idle 1/2 mode) or fs/ 2 [hz] (in the slow 1/2 or sleep 1 mode), and a pulse width of two machine cycles or more is re- quired at both the "h" and "l" levels. 14.4.3.3 auto capture refer to "14.4.1.3 auto capture". 14.4.3.4 register buffer configuration refer to "14.4.1.4 register buffer configuration". tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 192 2012/5/18 ra000
figure 14-5 event count mode timing chart tmp89fw20a page 193 2012/5/18 ra000 tcb0 pin input counter timer start when the rising edge is selected (tb0mod=?0?) 1 0 n m write to tb0dral write to tb0drah tb0dral match detection write n write s write m write r reflected by writing to tb0drah reflected by writing to tb0drah counter clear inttcb0 interrupt request 23 4 mn-1 mn 01 rs 01 220 3 tb0drah tb0cr s r timer stop match detection counter clear rs-1
14.4.4 window mode in the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tcb0 pin (window pulse) and the internal clock. 14.4.4.1 setting setting the operation mode selection tb0mod to "101" activates the window mode. select the source clock at tb0mod. select the window pulse level at the trigger edge input selection tb0mod. setting tb0mod to "0" enables counting up as long as the window pulse is at the "h" level. setting tb0mod to "1" enables counting up as long as the window pulse is at the "l" level. note that this mode uses the tb0 input pin, and the tcb0 pin must be set to the input mode before- hand in port settings. the operation is started by setting tb0cr to "1". after the timer is started, writing to tb0mod and tb0cr is disabled. be sure to complete the required mode settings before start- ing the timer. 14.4.4.2 operation after the operation is started, when the level selected at tb0mod is input to the tcb0 pin, the up counter increments according to the source clock selected at tb0mod. when a match between the up counter value and the value set to timer register a (tb0dra) is detected, an inttcb0 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. the maximum frequency to be supplied must be slow enough for the program to analyze the count val- ue. define a frequency pulse that is sufficiently lower than the programmed internal source clock. setting tb0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". 14.4.4.3 auto capture refer to "14.4.1.3 auto capture". 14.4.4.4 register buffer configuration refer to "14.4.1.4 register buffer configuration". tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 194 2012/5/18 ra000
figure 14-6 window mode timing chart tmp89fw20a page 195 2012/5/18 ra000 source clock counter timer start count in the period of h level count in the period of h level 1 0 n m write to tb0dral write to tb0drah tb0dral match detection write n write m reflected by writing to tb0drah counter clear inttcb0 interrupt request 25 46 456 3 mn-1 mn 1 02 0 3 tb0drah tb0cr timer stop tb0mod tcb0 pin input during the h-level counting (tb0mod=?0?)
14.4.5 pulse width measurement mode in the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the in- put to the tcb0 pin and measures the input pulse width based on the internal clock. 14.4.5.1 setting setting the operation mode selection tb0mod to "110" activates the pulse width measure- ment mode. select the source clock at tb0mod. select the trigger edge at the trigger edge input selection tb0mod. setting tb0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge as a trig- ger to start the capture. the operation after capturing is determined by the pulse width measurement mode control tb0mod. setting tb0mod to "0" selects the double-edge capture. setting tb0mod to "1" selects the single-edge capture. the operation to be executed in case of an overflow of the up counter can be selected at the overflow in- terrupt control tb0cr. setting tb0ove to "1" makes an inttcb0 interrupt request occur in case of an overflow. setting tb0ove to "0" makes no inttcb0 interrupt request occur in case of an overflow. note that this mode uses the tb0 input pin, and the tcb0 pin must be set to the input mode before- hand in port settings. the operation is started by setting tb0cr to "1". in this time, tb0dra and tb0drb regis- ter are initialized to "0x0000". after the timer is started, writing to tb0mod and tb0cr is dis- abled. be sure to complete the required mode settings before starting the timer. 14.4.5.2 operation after the timer is started, when the selected trigger edge (start edge) is input to the tcb0 pin, inttcb0 interrupt request is generated, and then the up counter increments according to the selected source clock. subsequently, when the edge opposite to the selected edge is detected, the up counter value is captured into tb0drb, an inttcb0 interrupt request is generated, and tb0sr is set to "1". depending on the tb0mod setting, the operation differs as follows: ? double-edge capture (when tb0mod is "0") the up counter continues counting up after the edge opposite to the selected edge is detec- ted. subsequently, when the selected trigger edge is input, the up counter value is captured in- to tb0dra, an inttcb0 interrupt request is generated, and tb0sr is set to "1". at this time, the up counter is cleared to "0x0000". ? single-edge capture (when tb0mod is "1") the up counter stops counting up and is cleared to "0x0000" when the edge opposite to the se- lected edge is detected. subsequently, when the start edge is input, inttcb0 interrupt request is generated, and then the up counter restarts increment. when the up counter overflows during capturing, the overflow flag tb0sr is set to "1". at this time, an inttcb0 interrupt request occurs if the overflow interrupt control tb0cr is set to "1". the capture completion flags (tb0sr and the overflow flag (tb0sr) are cleared to "0" automatically when tb0sr is read. tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 196 2012/5/18 ra000
the captured value must be read from tb0drb (and also from tb0dra for the double-edge capture) before the next trigger edge is detected. if the captured value is not read, it becomes undefined. tb0dra and tb0drb must be read by using a 16-bit access instruction. setting tb0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0x0000". note 1: after the timer is started, if the edge opposite to the selected trigger edge is detected first, no cap- ture is executed and no inttcb0 interrupt request occurs. in this case, the capture starts when the se- lected trigger edge is detected next. figure 14-7 pulse width measurement mode timing chart 14.4.5.3 capture process figure 14-8 shows an example of the capture process for inttcb0 interrupt subroutine. the capture edge or overflow state can be easily judged by status register (tb0sr). tmp89fw20a page 197 2012/5/18 ra000 source clock counter counter clear counter clear counter clear counter clear timer start count start count start after the timer is started, if the falling edge is detected first, no interrupt occurs. 1 0 tb0drbh, l inttcb0 interrupt request 0 24 3 3 mn-1 mn 1 0 mn 20 tb0cr timer stop tb0mod tcb0 pin input single-edge capture (tb0mod=?1?) after the timer is started, if the falling edge is detected first, no interrupt occurs. source clock counter timer start 1 0 tb0drbh, l inttcb0 interrupt request 0 24 3 mn-1 mn mn+1 st-1 st mn 0 012 0 tb0drah, l st tb0cr timer stop tb0mod tcb0 pin input double-edge capture (tb0mod=?0?) tb0sr tb0sr tb0sr read tb0drb read tb0dra read tb0sr read tb0sr read tb0sr tb0sr read tb0sr read tb0sr read tb0drb read
figure 14-8 example of capture process tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 198 2012/5/18 ra000 reti tb0sr tb0sr tb0sr read error handling tb0drb read 1 overflow interrupt process for single-edge capture 0 (no overflow) 1 (capture) 0 no capture inttcb0 interrupt subroutine inttcb0 interrupt subroutin reti tb0sr tb0sr tb0sr read error handling tb0drb read 1 overflow interrupt process for double-edge capture 0 (no overflow) 1 (capture) 0 no capture 1 (capture) 0 no capture tb0sr tb0dra read capture value handling capture value handling
14.4.6 programmable pulse generate (ppg) mode in the ppg output mode, an arbitrary duty pulse is output by two timer registers. 14.4.6.1 setting setting the operation mode selection tb0mod to "011" or "111" activates the ppg output mode. setting tb0mod to "011" selects the software start, and setting it to "111" selects the ex- ternal trigger start (the external trigger start can be used only when tca2 is used). select the source clock at tb0mod. select continuous or one-shot ppg output at tb0cr. set the ppg output cycle at tb0dra and set the time until the output is reversed first at tb0drb. be sure to set register values so that tb0dra is larger than tb0drb. if you use the external trigger start, select the trigger edge at the trigger edge input selection tb0mod. setting tb0mod to "0" selects the rising edge. setting tb0mod to "1" selects the falling edge. note that this mode uses the tcb0 pin and the ppgb0 pin. the tcb0 pin must be set to the input mode and the ppgb0 pin must be set to the output mode beforehand in port settings. set the initial state of the ppgb0 pin at the timer flip-flop tb0cr. setting tb0cr to "1" selects the "h" level as the initial state of the ppgb0 pin. setting tb0cr to "0" selects the "l" level as the initial state of the ppgb0 pin. the operation is started by setting tb0cr to "1". after the timer is started, writing to tb0mod and tb0cr is disabled. be sure to complete the required mode settings be- fore starting the timer. 14.4.6.2 operation in the external trigger start mode, after the timer is started, when the selected trigger edge is input to the tcb0 pin, the up counter increments according to the selected source clock. in the software start mode, aafter the timer is started, the up counter increments immediately without waiting for the edge. when a match between the up counter value and the value set to timer register b (tb0drb) is detec- ted, the ppgb0 pin is changed to the "h" level if tb0cr is "0", or the ppgb0 pin is changed to the "l" level if tb0cr is "1". subsequently, the up counter continues counting. when a match between the up counter value and the val- ue set to timer register a (tb0dra) is detected, the ppgb0 pin is changed to the "l" level if tb0cr is "0", or the ppgb0 pin is changed to the "h" level if tb0cr is "1". at this time, an inttcb0 interrupt request occurs. if the ppg output control tb0cr is set to "1" (one-shot), tb0cr is automatically cleared to "0" and the timer stops. if tb0cr is set to "0" (continuous), the up counter is cleared to "0x0000" and continues counting and ppg output. when tb0cr is set to "0" (including the auto stop by the one-shot op- eration) during the ppg output, the ppgb0 pin returns to the level set in tb0cr. tb0cr can be changed during the operation. changing tb0cr from "1" to "0" during the operation cancels the one-shot operation and enables the continuous operation. chang- ing tb0cr from "0" to "1" during the operation clears tb0cr to "0" and stops the timer automatically after the current pulse output is completed. timer registers a and b can be set to the double buffer. setting tb0cr to "1" enables the dou- ble buffer. when the values set to tb0dra and tb0drb are changed during the ppg output with the dou- ble buffer enabled, the writing to tb0dra and tb0drb will not immediately become effective but will become effective when a match between tb0dra and the up counter is detected. if the double buffer is dis- tmp89fw20a page 199 2012/5/18 ra000
abled, the writing to tb0dra and tb0drb will become effective immediately. if the written value is smaller than the up counter value, the up counter overflows. after a cycle, the counter match process is exe- cuted to reverse the output. 14.4.6.3 register buffer configuration (1) temporary buffer the tmp89fw20a contains an 8-bit temporary buffer. when a write instruction is executed on tb0dral (tb0drbl), the data is first stored into this temporary buffer, whether the double buf- fer is enabled or disabled. subsequently, when a write instruction is executed on tb0drah (tb0drbh), the set value is stored into the double buffer or tb0drah (tb0drbh). at the same time, the set value in the temporary buffer is stored into the double buffer or tb0dral (tb0drbl). (this structure is designed to enable the set values of the lower-level register and the higher-level register simultaneously.) therefore, when setting data to tb0dra (tb0drb), be sure to write the data into tb0dral and tb0drah (tb0drbl and tb0drbh) in this order. see figure 14-1 for the temporary buffer configuration. (2) double buffer in the tmp89fw20a, the double buffer can be used by setting tb0cr. setting tb0cr to "0" disables the double buffer. setting tb0cr to "1" enables the double buffer. see figure 14-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on tb0drah (tb0drbh) during the timer opera- tion, the set value is first stored into the double buffer, and tb0drah/l are not updated im- mediately. tb0drah/l (tb0drbh/l) compare the last set values to the counter value. if a match is detected, an inttcb0 interrupt request is generated and the double buffer set value is stored into tb0drah/l (tb0drbh/l). subsequently, the match detection is executed using a new set value. when a read instruction is executed on tb0drah/l (tb0drbh/l), the double buffer value (the last set value) is read, not the tb0drah/l (tb0drbh/l) values (the current ef- fective values). when a write instruction is executed on tb0drah/l (tb0drbh/l) while the timer is stopped, the set value is immediately stored into both the double buffer and tb0drah/l (tb0drbh/l). - when the double buffer is disabled when a write instruction is executed on tb0drah (tb0drbh) during the timer opera- tion, the set value is immediately stored in tb0drah/l (tb0drbh/l). subsequently, the match detection is executed using a new set value. if the values set to tb0drah/l (tb0drbh/l) are smaller than the up counter value, the up counter overflows and the match detection is executed using a new set value. as a re- sult, the output pulse width may be longer than the set time. if that is a problem, enable the double buffer. when a write instruction is executed on tb0drah/l (tb0drbh/l) while the timer is stopped, the set value is immediately stored into tb0drah/l (tb0drbh/l). tmp89fw20a 14. 16-bit timer counter (tcb) 14.4 timer function page 200 2012/5/18 ra000
figure 14-9 ppg mode timing chart tmp89fw20a page 201 2012/5/18 ra000 source clock counter timer start 1 0 n m m (duty pulse) m (duty pulse) n (1 cycle) r (duty pulse) s (1 cycle) s r write to tb0dral, h write to tb0drbl, h tb0dral, h match detection match detection write n write s write m write r becomes the level set at tb0tff when the timer is stopped reflected by an interrupt request returns to the level set at tb0tff counter clear inttcb0 interrupt request 2m 1 m+1 n 00 tb0drbl, h tb0cr timer stop match detection match detection counter clear 2r 1 r+1 r r+1 s 0 match detection tb0mod ppg0 pin output continuous (tb0cr=?0?) double buffer (tb0mod=?1?) r (duty pulse) source clock counter timer start 1 0 n m n (1 cycle) write to tb0dral, h write to tb0drbl, h tb0dral, h match detection match detection write n write m becomes the level set at tb0tff when the timer is stopped returns to the level set at tb0tff counter clear inttcb0 interrupt request 2m m+1 n 0 tb0drbl, h tb0cr timer stops automatically tb0mod ppg0 pin output one-shot (tb0cr=?1?)
14.5 noise canceller the digital noise canceller can be used in the operation modes that use the tcb0 pin. 14.5.1 setting when the digital noise canceller is used, the input level is sampled at the sampling intervals set at tb0cr. when the same level is detected three times consecutively, the level of the input to the tim- er is changed. setting tb0cr to any values than "00" allows the noise canceller to start operation, regardless of the tb0cr value. when the noise canceller is used, allow the timer to start after a period of time that is equal to four times the sampling interval after tb0cr is set has elapsed. this stabilizes the input signal. set tb0cr while the timer is stopped (tb0cr = "0"). when tb0cr is "1", writ- ing is ignored. in the slow 1/2 or sleep 1 mode, setting tb0cr to "11" selects fs/2 as the source clock for the operation. setting tb0cr to "00" disables the noise canceller. setting tb0cr to "01" or "10" disables the tcb0 pin input. table 14-4 noise cancel time ( fcgck = 10 [mhz] ) tb0nc sampling interval time removed as noise time regarded as signal 00 none - - 01 200 ns (2/fcgck) 600 ns or less 800 ns or more 10 400 ns (4/fcgck) 1.2 s or less 1.6 s or more 11 25.6 s (256/fcgck) 76.8 s or less 102.4 s or more tmp89fw20a 14. 16-bit timer counter (tcb) 14.5 noise canceller page 202 2012/5/18 ra000
15. 10-bit timer/counter (tcc) the tmp89fw20a contains 1 channels of high-performance 10-bit timer counters (tcc). the 10-bittimer/counterc0 has one trigger input (tcc0) for start/stop/clear/capture of the counter.timer has two ppg outputs (ppgc01,ppgc02) that can perform synchronous operation or individual operation.timer has one emergency input(emg0) for stop ppg output. table 15-1 sfr address assignment (the1) tcxcr1 (address) tcxcr2 (address) tcxcr3 (address) timer/counter c0 tc0cr1 (0x00e98) tc0cr2 (0x00e99) tc0cr3 (0x00e9a) table 15-2 sfr address assignment(the2) tcxdra (address) tcxdrb (address) tcxdrc (address) tcxdrd (address) tcxdre (address) tcxcapa (address) tcxcapb (address) low power consumption register (address) timer/counter c0 tc0dra (0x00e9c) (0x00e9b) tc0drb (0x00e9e) (0x00e9d) tc0drc (0x00ea0) (0x00e9f) tc0drd (0x00ea2) (0x00ea1) tc0dre (0x00ea4) (0x00ea3) tc0capa (0x00ea6) (0x00ea5) tc0capb (0x00ea8) (0x00ea7) poffcr0 (0x00f74) table 15-3 pin names timer input pin ppg output pin ppg output pin emg input pin timer/counterc0 tcc0 pin ppgc01 pin ppgc02 pin emg0 pin tmp89fw20a page 203 2012/5/18 ra000
15.1 configuration figure 15-1 10-bit timer/counter c0 tmp89fw20a 15. 10-bit timer/counter (tcc) 15.1 configuration page 204 2012/5/18 ra000 10-bit up counter compare register e a b c y d s compare register d compare register c compare register b compare register a tc0cr1 tc0cr2 tc0capa tc0capb tc0cr3 noise canceller emergency output stop control edge detection ppg output control comparator tc0dra tc0drb tc0drc tc0drd tc0dre transfer control capture control inttcc0t interrupt request fcgck fcgck/2 fcgck/2 2 fcgck/2 3 inttcc0p interrupt request intemg0 interrupt request emergency stop tccck tgram start/ clear emgf csidis cstc tccst stm cntbf trgsel emgf cstc emgie emgr ppgc2oe ppgc1oe tccout csidis ncrsel tcc0 pin emg0 pin ppgc02 pin ppgc01 pin ppgc2ini ppgc1ini ppgc1ini/ ppgc2ini tccout outpg
15.2 control timer/counter c0 is controlled by low power consumption registers (poffcr0),timer/counter control register 1 (tc0cr1), timer/counter control register 2(tc0cr2), timer/counter control register 3 (tc0cr3), 10-bit dead time 1 setup register (tc0dra), pulse width 1 setup register (tc0drb), period setup register (tc0drc), dead time 2 setup register (tc0drd), pulse width 2 setup register (tc0dre), and two capture value registers (tc0ca- pa and tc0capb). low power consumption register 0 poffcr0 7 6 5 4 3 2 1 0 (0x00f74) bit symbol - - tc023en tc001en - tcc0en tcb0en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tcc0en tcc0 control 0 1 disable enable tcb0en tcb0 control 0 1 disable enable tca0en tca0 control 0 1 disable enable tmp89fw20a page 205 2012/5/18 ra000
timer/counter c0 control register 1 tc0cr1 7 6 5 4 3 2 1 0 (0x00e98) bit symbol trgam trgsel ppgc2ini ppgc1ini ncrsel tccck read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 trgam trigger edge acceptance control 0: 1: always accept trigger edges. (refer to the setting of tc0cr2) trgsel select a trigger start edge. 0: 1: start on trigger falling edge. start on trigger rising edge. ppgc2ini specify the initial value of ppg2 output. 0: 1: low (positive logic) high (negative logic) ppgc1ini specify the initial value of ppg1 output. 0: 1: low (positive logic) high (negative logic) ncrsel select the duration of noise elimi- nation for tcc0 input (after passing through the flip-flop). 00: 01: 10: 11: eliminate pulses shorter than 16/fcgck [s] as noise. eliminate pulses shorter than 8/fcgck [s] as noise. eliminate pulses shorter than 4/fcgck [s] as noise. do not eliminate noise. (note) tccck select a source clock 00: 01: 10: 11: fcgck [hz] fcgck/2 [hz] fcgck/2 2 [hz] fcgck/2 3 [hz] note:due to the circuit configuration, a pulse shorter than 1/fcgck may be eliminated as noise or accepted as a trig- ger. timer/counter c0 control register 2 tc0cr2 7 6 5 4 3 2 1 0 (0x00e99) bit symbol emgr emgie ppgc2oe ppgc1oe cstc tccout read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 emgr cancel the emergency output stop state. 0: 1: - cancel the emergency output stop state. (upon canceling the state,this bit is automatically cleared to 0.) emgie enable/disable input on the emg0 pin. 0: 1: disable input. enable input. ppgc2oe trigger edge accept control during the ppgc02 output. when tc0cr1 is "0" when tc0cr1 is "1" 0: 1: always accept trigger edges. always accept trigger edges. always accept trigger edges. do not accept trigger edges dur- ing active period. ppgc1oe trigger edge accept control during the ppgc01 output. 0: 1: always accept trigger edges. always accept trigger edges. always accept trigger edges. do not accept trigger edges dur- ing active period. cstc select a count start mode. 00: 01: 10: 11: command start and capture mode command start and trigger start mode. trigger start mode reserved tccout select an output waveform mode. 00: 01: 10: 11: ppgc01/ppgc02 independent output reserved output with variable duty ratio output with 50% duty ratio tmp89fw20a 15. 10-bit timer/counter (tcc) 15.2 control page 206 2012/5/18 ra000
timer/counter c0 control register 3 tc0cr3 7 6 5 4 3 2 1 0 (0x00e9a bit symbol - - emgf cntbf csidis stm tccst read/write r r r r r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 emgf emergency output stop flag 0: 1: operating normally output stopped in emergency cntbf counting status flag 0: 1: counting stopped counting in progress csidis disable the first interrupt at upon a command start. 0: allow a periodic interrupt (inttcc0p) to occur in the first period upon a command start. 1: do not allow a periodic interrupt (inttcc0p) to occur in the first peri- od upon a command start. stm select the state when stopped. select continuous or one-time out- put. tccst = "0" tccst = "1" 00: immediately stop and clear the counter with the output initialized. continuous output 01: immediately stop and clear the counter with the output initialized. continuous output 10: stop the counter after completing output in the current period. one-time output 11: reserved tccst start/stop the timer. 0: 1: stop start note 1: the tc0cr1 and tc0cr2 registers should not be rewritten after a timer start (when tccst is "1"). note 2: before attempting to modify the tc0cr1 or tc0cr2, clear tccst and then check that cntbf = 0 to determine that the timer is stopped. note 3: the tccst bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. its value does not change automatically when counting starts or stops note 4: in command start and capture mode or command start and trigger start mode, writing 1 to tccst causes the timer to restart immediately. it means that rewriting any bit other than tccst in the tc0cr3 after a command start cau- ses the rewriting of tccst, resulting in the timer being restarted (ppg output is started from the initial state). when tccst is set to 1, rewriting the tc0cr3 (using a bit manipulation or ld instruction) clears the counter and restarts the timer. note 5: tc0cr2 is always read as 0 even after 1 is written. note 6: data registers are not updated by merely modifying the output mode with tc0cr2. after modifying the out- put mode, reconfigure data registers tc0dra to tc0dre. ensure that the data registers are written in an appropri- ate order because they are not enabled until the upper byte of the tc0drc is written. note 7: when a read instruction is executed on tc0cr3, bits 7 and 6 are read as "0". tmp89fw20a page 207 2012/5/18 ra000
dead time 1 setup register ah tc0drah 15 14 13 12 11 10 9 8 (0x00e9c) bit symbol tc0drah read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 dead time 1 setup register al tc0dral 7 6 5 4 3 2 1 0 (0x00e9b) bit symbol tc0dral read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 pulse width 1 setup register bh tc0drbh 15 14 13 12 11 10 9 8 (0x00e9e) bit symbol tc0drah read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 pulse width 1 setup register bl tc0drbl 7 6 5 4 3 2 1 0 (0x00e9d) bit symbol tc0dral read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 period setup register ch tc0drch 15 14 13 12 11 10 9 8 (0x00ea0) bit symbol tc0drch read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 period setup register cl tc0drcl 7 6 5 4 3 2 1 0 (0x00e9f) bit symbol tc0drcl read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tmp89fw20a 15. 10-bit timer/counter (tcc) 15.2 control page 208 2012/5/18 ra000
dead time 2 setup register dh tc0drdh 15 14 13 12 11 10 9 8 (0x00ea2) bit symbol tc0drdh read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 dead time 2 setup register dl tc0drdl 7 6 5 4 3 2 1 0 (0x00ea1) bit symbol tc0drdl read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 pulse width 2 setup register eh tc0dreh 15 14 13 12 11 10 9 8 (0x00ea4) bit symbol tc0dreh read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 pulse width 2 setup register el tc0drel 7 6 5 4 3 2 1 0 (0x00ea3) bit symbol tc0drel read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note 1: data registers tc0dra to tc0dre have double-stage configuration, consisting of a data register that stores data writ- ten by an instruction and a compare register to be compared with the counter. note 2: when writing data to data registers tc0dra to tc0dre, first write the lower byte and then the upper byte. note 3: unused bits (bits 10 to 15) in the upper bytes of data registers tc0dra to tc0dre are not assigned specific regis- ter functions. these bits are always read as 0 even when a 1 is written. note 4: values read from data registers tc0dra to tc0dre may differ from the actual ppg output waveforms due to their dou- ble-stage configuration. note 5: data registers are not updated by merely modifying the output mode with tc0cr2. after modifying the out- put mode, reconfigure data registers tc0dra to tc0dre. ensure that the data registers are written in an appropri- ate order because they are not enabled until the upper byte of the tc0drc is written. tmp89fw20a page 209 2012/5/18 ra000
rising-edge capture value register ah tc0capah 15 14 13 12 11 10 9 8 (0x00ea6) bit symbol tc0capah read/write r r r r r r r r after reset 0 0 0 0 0 0 * * rising-edge capture value register al tc0capal 7 6 5 4 3 2 1 0 (0x00ea5) bit symbol tc0capal read/write r r r r r r r r after reset * * * * * * * * rising-edge capture value register bh tc0capbh 15 14 13 12 11 10 9 8 (0x00ea8) bit symbol tc0capbh read/write r r r r r r r r after reset 0 0 0 0 0 0 * * rising-edge capture value register bl tc0capbl 7 6 5 4 3 2 1 0 (0x00ea7) bit symbol tc0capbl read/write r r r r r r r r after reset * * * * * * * * note 1: capture registers (tc0capa and tc0capb) must be read in the following order: lower byte of the tc0capa, up- per byte of the tc0capa, lower byte of the tc0capb, upper byte of the tc0capb. note 2: the next captured data is not updated by reading the tc0capa only. the tc0capb must also be read. note 3: it is possible to read the tc0capb only. read the lower byte first. note 4: if a capture edge is not detected within a period, the previous capture value is maintained in the next period. note 5: if more than one capture edge is detected within a period, the capture value for the edge detected last is valid in the next period. note 6: when a read instruction is executed on tc0capa and tc0capb, bits 15 to 10 are read as "0". tmp89fw20a 15. 10-bit timer/counter (tcc) 15.2 control page 210 2012/5/18 ra000
15.3 low power consumption function timer counter c0 has the low power consumption register (poffcr0) that saves power consumption when the timer is not used. setting poffcr0 to "0" disables the basic clock supply to timer counter c0 to save power. note that this makes the timer unusable. setting poffcr0 to "1" enables the basic clock supply to timer coun- ter c0 and allows the timer to operate. after reset, poffcr0 is initialized to "0", and this makes the timer unusable. when using the tim- er for the first time, be sure to set poffcr0 to "1" in the initial setting of the program (before the tim- er control register is operated). do not change poffcr0 to "0" during the timer operation. otherwise timer counter c0 may oper- ate unexpectedly. tmp89fw20a page 211 2012/5/18 ra000
15.4 configuring control and data registers configure control and data registers in the following order: 1. configure mode settings: tc0cr1, tc0cr2 2. configure data registers (dead time, pulse width):tc0dra, tc0drb, tc0drd, tc0dre (only those re- quired for selected mode) 3. configure data registers (period): tc0drc 4. configure timer start/stop:tc0cr3 ? data registers have double-stage configuration, consisting of a data register that stores data written by an instruction and a compare register to be compared with the counter. ? data stored in a data register is processed according to the output mode specified in the tc0cr2,transferred to the compare register, and then used for comparison with the up counter. ? data registers required for the specified output mode are used for data register processing and transfer to the compare register. ensure that the output mode is specified in the tc0cr2 before configur- ing data registers. ? writing data to the upper byte of the tc0drc causes a data transfer request to be issued for data in data registers tc0dra to tc0dre. if a counter match or clear occurs while that request is valid, the data is transferred to the compare register and becomes valid for comparison. ? if a data register is written more than once within a period, the data in the data register that was set when the upper byte of the tc0drc was written is valid as data for the next period. the data in the data regis- ter written last in the first period will be valid for the period that follows the next period. tmp89fw20a 15. 10-bit timer/counter (tcc) 15.4 configuring control and data registers page 212 2012/5/18 ra000
figure 15-2 example configuration of control/data registers (1) figure 15-3 example configuration of control/data registers (2) tmp89fw20a page 213 2012/5/18 ra000 if data is rewritten more than once within a period, the data written first is valid in the next period. valid in next period period (1) tc0dra tc0drb tc0drc period (2) period (3) period (4) a1 b1 c1 a2 b2 c2 a3 b3 c3 previous data is maintained if data is not rewritten within the period. period (1) tc0dra tc0drb tc0drc period (2) period (3) period (4) period (5) a1 b1 c1 execute write instruction. a5 c7 a1 b1 c1 a2 b1 c2 a3 b2 c5 a5 b2 c7 a2 c2 a4 c6 a3 c5 b2 c4 c3 execute write instruction. a6 b3 c8 a7 b4 c9 a6 b3 c8 if data is rewritten more than once within a period, the data written last is valid in the period following the next period. execute more than one data write instruction. no data write execute write instruction. execute write instruction. data valid in each period execute write instruction. execute write instruction. if tc0drc is written in the next period period (1) tc0dra tc0drb tc0drc period (2) period (3) period (4) period (5) period (6) a1 b1 c1 a1 b1 c1 a1 b1 c1 a3 b3 c3 a1 b1 c1 a2 b2 c2 c3 a3 b3 a3 b3 c3 a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c3 a4 b4 c3 no data write more than one data write more than one data write data valid in each period
15.5 features 15.5.1 programmable pulse generator output (ppg output) the ppgc01 and ppgc02 pins provide ppg outputs. the output waveform mode for ppg outputs is speci- fied with tc0cr2 and their waveforms are controlled by comparing the contents of the 10-bit up counter with the data set in data registers (tc0dra to tc0dre). three output waveform modes are avail- able:50% duty mode, variable duty mode, and ppgc01/ ppgc02 independent mode. 15.5.1.1 50% duty mode (1) description with a period specified in the tc0drc, the ppgc01 and ppgc02 pins provide waveforms hav- ing a pulse width (active duration) that equals a half the period. the ppgc01 output is active at the beginning of a period and becomes inactive at half the peri- od. the ppgc02 output is inactive at the beginning of a period, becomes active at half the period, and remains active until the end of the period. if a dead time is specified in the tc0dra, the pulse width (active duration) is shortened by the dead time. (2) register settings tc0cr2 = 11, tc0dra = dead time, tc0drc = period (3) valid range for data register values ? period: 0x002 tc0drc 0x400 (writing 0x400 to tc0drc results in 0x000 being read from it) when the value set in the tc0drc is an odd number, the ppgc02 pulse width is one count longer than the ppgc01 pulse width. ? dead time tc0dra: 0x000 tc0dra < (tc0drc 2) to specify no dead time, set the tc0dra to 0x000. tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 214 2012/5/18 ra000
figure 15-4 example operation in 50% duty mode: command and capture start, positive log- ic, continuous output 15.5.1.2 variable duty mode (1) description with a period specified in the tc0drc and a pulse width in the tc0drb, the ppgc01 pin pro- vides a waveform having the specified pulse width while the ppgc02 pin provides a waveform hav- ing a pulse width that equals (tc0drc . tc0drb). the ppgc01 output is active at the beginning of a period, remains active during the pulse width specified in the tc0drb, after which it is inactive until the end of the period. the ppgc02 output is inactive at the beginning of a period, remains inactive during the pulse width specified in the tc0drb,after which it is active until the end of the period, that is, during the pulse width of (tc0drc .tc0drb). if a dead time is specified in the tc0dra, the pulse width (active duration) is shortened by the dead time. (2) register settings tc0cr2 = 10 tc0dra = dead time, tc0drb = pulse width, tc0drc = period (3) valid range for data register values ? period: 0x002 tc0drb + tc0dra < tc0drc 0x400 (writing 0x400 to tc0drc results in 0x000 being read from it.) ? pulse width: tmp89fw20a page 215 2012/5/18 ra000 s, 0 m s m ' s 1 m s/2 s, 0 2 13 s/2+1 s/2+m counter period dead time source clock ppgc01 output m: dead time dead time (tc0dra) period (tc0drc) pulse width (tc0drc / 2) pulse width (tc0drc / 2) dead time (tc0dra) m: dead time s: period active duration active duration ppgc02 output inttcc0t interrupt request inttcc0p interrupt request
0x001 tc0drb < tc0drc ? dead time: 0x000 tc0dra < tc0drb 0x000 tc0dra < (tc0drc ? tc0drb) (to specify no dead time, set the tc0dra to 0x000.) figure 15-5 example operation in variable duty mode: command and capture start, posi- tive logic, continuous output 15.5.1.3 ppgc01/ppgc02 independent mode (1) description for the ppgc01 output, specify the dead time in the tc0dra and pulse width in the tc0drb. for the ppgc02 output, specify the dead time in the tc0drd and pulse width in the tc0dre. with a common period specified in the tc0drc, the ppgc01 and ppgc02 pins provide wave- forms having the specified pulse widths. the ppgc01 output is active at the beginning of a period, remains active during the pulse width specified in the tc0drb, after which it is inactive until the end of the period. the ppgc02 output is active at the beginning of a period, remains active during the pulse width specified in the tc0dre, after which it is inactive until the end of the period. if a dead time is specified in the tc0dra for the ppgc01 output or in the tc0drd for the ppgc02 output, the pulse width (active duration) is shortened by the dead time. (2) register settings tc0cr2 = 00, tc0drc = period, tc0dra = ppgc01 dead time, tc0drb = ppgc01 pulse width, tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 216 2012/5/18 ra000 s, 0 m s m ' s 1 m n s, 0 2 13 n+1 n+m counter period dead time n n ' pulse width source clock ppgc01 output m: dead time dead time (tc0dra) period (tc0drc) pulse width (tc0drc-tc0drb) pulse width (tc0drb) dead time (tc0dra) m: dead time s: period n: pulse width active duration active duration ppgc02 output inttcc0t interrupt request inttcc0p interrupt request
tc0drd = ppgc02 dead time, tc0dre = ppgc02 pulse width (3) valid range for data register values ? period: 0x002 tc0drc 0x400 (writing 0x400 to tc0drc results in 0x000 being read from it.) ? pulse width: 0x001 tc0drb 0x400 (writing 0x400 to tc0drb results in 0x000 being read from it.) 0x001 tc0dre 0x400 (writing 0x400 to tc0dre results in 0x000 being read from it.) ? dead time: 0x000 tc0dra 0x3ff, where tc0dra < tc0drb tc0drc 0x000 tc0drd 0x3ff, where tc0drd < tc0dre tc0drc (to specify no dead time, write 0x000) 1. settings for a duty ratio of 0% 0x002 tc0drc tc0dra 0x3ff ( ppgc01 output) 0x002 tc0drc tc0drd 0x3ff ( ppgc02 output) 2. settings for a duty ratio greater than 0%, up to 100% 0x000 tc0dra < tc0drb tc0drc 0x400 ( ppgc01 output) 0x000 tc0drd < tc0dre tc0drc 0x400 ( ppgc02 output) tmp89fw20a page 217 2012/5/18 ra000 period 0% duty period 100% duty
figure 15-6 example operation in ppgc01/ppgc02 independent mode: command and cap- ture start, positive logic, continuous output 15.5.2 starting a count a count can be started by using a command or tcc0 pin input. 15.5.2.1 command start and capture mode(tc0cr2="00") (1) description writing a 1 to tc0cr3 causes the current count to be cleared and the counter to start counting. once the count has reached a specified period, the counter is cleared. the counter subse- quently restarts counting if tc0cr3 specifies continuous mode; it stops counting if tc0cr3 specifies one-time mode. writing a 1 to tc0cr3 before the count reaches a period causes the counter to be cleared, after which it operates as specified with tc0cr3. the count values at the rising and falling edges on the tcc0 pin can be stored in capture registers (for more information of the capture, see 1.5.5.3 trigger capture .) tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 218 2012/5/18 ra000 0 m s m ' s 1 m t u s, 0 2 13 n counter period dead time n n ' pulse width source clock ppgc01 output m: dead time ppgc01 dead time (tc0dra) period (tc0drc) ppgc02 pulse width (tc0dre) ppgc02 dead time (tc0drd) ppgc01 pulse width (tc0drb) s: period u: pulse width t: dead time n: pulse width active duration active duration ppgc02 output inttcc0t interrupt request inttcc0p interrupt request t t ' dead time u u ' pulse width
(2) register settings - tc0cr2 = 00 command start and capture mode - tc0cr3 continuous/one-time output - tc0cr3 = 1 starts counting figure 15-7 example operation in command start and capture mode 15.5.2.2 command start and trigger start mode(tc0cr2="01") (1) description writing a 1 to tc0cr3 causes the current count to be cleared and the counter to start counting. the operation is the same as that in command start and capture mode if there is no trigger input on the tcc0 pin. if an edge specified with the start edge selection field (tc0cr1) appears on the tcc0 pin,however, the timer starts counting. the counter is cleared and stopped while the tcc0 pin is driven to the specified clear/stop level. if the tcc0 pin is at the clear/stop level when a count start command is issued (1 is written to tc0cr3), counting does not start (inttcc0p does not occur) until a trigger start edge appears, causing inttcc0t to occur (a trigger input takes precedence over a command start). note:for more information on the acceptance of a trigger, see 15.5.4 trigger start/stop accept- ance mode . (2) register settings - tc0cr2 = 01 command start and trigger start mode - tc0cr1 = trigger selection - tc0cr3 continuous/one-time output - tc0cr3 = 1 starts counting tmp89fw20a page 219 2012/5/18 ra000 tccst = 1 count start (command)) count cleared start count cleared start count cleared restart ppgc01 output ppg output with a period specified with tc0drc ppg output with a period specified with tc0drc ppg output with a period specified with tc0drc
figure 15-8 example operation in command start and trigger start mode 15.5.2.3 trigger start mode(tc0cr2="10") (1) description if an edge specified with the start edge selection field (tc0cr1) appears on the tcc0 pin, the timer starts counting. the counter is cleared and stopped while the tcc0 pin is driv- en to the specified clear/stop level. in trigger start mode, writing a 1 to tc0cr3 is ignored and does not initialize the ppg output. note:for more information on the acceptance of a trigger, see 15.5.4 trigger start/stop accept- ance mode. (2) register settings - tc0cr2 = 10 trigger start mode - tc0cr1 = trigger selection - tc0cr3 continuous/one-time output - tc0cr3 = 1 starts waiting for a trigger on the tcc0 pin tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 220 2012/5/18 ra000 count start (command) count cleared start count cleared count start ppgc01 output tc0cr1 (start on falling edge) tcc0 input (signal after noise elimination) period (tc0drc) count stopped ppg output with a period specified with tc7drc if there is no trigger count stops with a trigger (high level). count starts with a trigger (falling edge).
figure 15-9 example operation in trigger start mode 15.5.3 trigger capture 15.5.3.1 description when counting starts in command start and capture mode, the count values at the rising and falling edges of the tcc0 pin input are captured and stored in capture registers tc0capa and tc0capb,respec- tively. the captured data is first stored in the capture buffer. at the end of the period, the data is transferred from the capture buffer to the capture register. if a trigger input does not appear within a period, the data cap- tured in the previous period remains in the capture buffer and is transferred to the capture register at the end of the period. if more than one trigger edge is detected within a period, the data captured last is writ- ten to the capture register. captured data must be read in the following order: lower byte of capture register a (tc0capal),up- per byte of capture register a (tc0capah), lower byte of capture register b (tc0capbl), and upper byte of capture register b (tc0capbh). note that reading only the rising-edge captured data (tc0ca- pa) does not update the next captured data. the falling-edge captured data (tc0capb) must also be read. an attempt to read a captured value from a register other than the upper byte of the tc0capb causes the capture registers to enter protected state, in which captured data cannot be updated. reading a value from the upper byte of the tc0capb cancels that state, re-enabling the updating of captured data (the tc0capa and tc0capb are read as a single set of operation). note that the protected state may be still effective immediately after the counter starts. ensure that a dum- my read of capture registers is performed in the first period to cancel the protected state. the capture feature of the tcc0 assumes that a capture trigger (rising or falling edge) appears within a period. captured data is updated (an edge is detected) only when the timer is operating (tc0cr3 = 1). if a timer stop command (tc0cr3 = 0) is written within a period, cap- tured data will be undefined. captured data is not updated after a one-time stop command is written. in one-time stop mode, no trigger is accepted after a stop command is given. tmp89fw20a page 221 2012/5/18 ra000 count start count stopped count stopped count start count cleared count cleared ppgc01 output (example) tcc0 output (signal after noise elimination) tc0cr1 tc0cr1 after a command is set, counting does not start until a specified trigger appears. count start count stopped count start command set command set count cleared ppgc01 output (example) tcc0 output (signal after noise elimination) after a command is set, counting does not start until a specified trigger appears.
15.5.3.2 register settings - tc0cr2 = 00 command start and capture mode - tc0cr3 continuous/one-time output - tc0cr3 = 1 starts counting figure 15-10 example operation in trigger capture mode 15.5.4 trigger start/stop acceptance mode 15.5.4.1 selecting an input signal logic for the tcc0 pin (trigger input) the logic for an input trigger signal on the tcc0 pin can be specified using tc0cr1 . ? tc0cr1 = 0: counting starts on the falling edge. the counter is cleared and stop- ped while the tcc0 pin is high. tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 222 2012/5/18 ra000 ab cd ac xac ybd bd capture registers 1 period rising edge falling edge rising edge falling edge captured values read (c and d read) 1 period tcc0 output (signal after noise elimination) captured values read (a and b read) captured values read (data read skipped) capture buffers capture registers capture buffers a b c d a1 b1 c1 a2 c2 a c2 cc1 a1 x c2 cc1 a1 y a2 db1 d ba2 db1 1 period aptured values read (c and d read) 1 period 1 period 1 period tcc0 output (signal after noise elimination) captured values read (a and b read) captured values read (data read skipped) started reading other than upper capb in this period
? tc0cr1 = 1: counting starts on the rising edge. the counter is cleared and stop- ped while the tcc0 pin is low. figure 15-11 trigger input signal when tc0cr1 is set to 0 to select a falling-edge trigger, a falling edge detected on the tcc0 pin causes the counter to start counting and a high level on the tcc0 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tcc0 pin input is high. when tc0cr1 is set to 1 to select a rising-edge trigger, a rising edge detected on the tcc0 pin causes the counter to start counting and a low level on the tcc0 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tcc0 pin input is low. in one-time stop mode, the counter accepts a stop trigger but does not accept a start trigger (when a stop trigger is accepted within a period, the output is immediately initialized and the counter is stopped). all triggers (start and stop) are ignored when the timer is stopped (tc0cr3 = 0). 15.5.4.2 specifying whether triggers are always accepted or ignored when ppg outputs are active the tc0cr1 specifies whether triggers from the tcc0 pin are always accepted or ignored when the ppg output is active. ? tc0cr1 = 0 triggers from the tcc0 pin are always accepted regardless of whether ppgc01 and ppgc02 outputs are active or inactive. a trigger starts or clears/stops the timer and deacti- vates ppgc01 and ppgc02 outputs. ? tc0cr1 = 1 after tc0cr2 setting to "1" ,triggers from the tcc0 pin are accepted only when ppgc01 and ppgc02 outputs are inactive.a trigger starts or clears/stops the timer. trig- gers are ignored when ppgc01 and ppgc02 outputs are active.tiggers are always accept the output of ppgc01 and ppgc02 when tc0cr2 is set in "0" (x = 1, 2). tmp89fw20a page 223 2012/5/18 ra000 count started count cleared count started tcc0 pin input counter operating counter stopped counter operating counter operating counter operating trgsel = 0 count started count cleared count started tcc0 pin input counter stopped trgsel = 1 count cleared tcc0 pin input ppgc0 pin output counting stop mode with the outputs at the end of the period count cleared initial value one-time mode
figure 15-12 start and clear/stop triggers on the tc7 pin: falling-edge trigger (counting stopped at high level), triggers always accepted 15.5.4.3 ignoring triggers when ppg outputs are active setting trgam to 1 specifies that triggers are ignored when ppg outputs are active; trigger edges detec- ted when ppgc01 and ppgc02 outputs are inactive are accepted and cause the counter to be cleared and stopped. if a trigger is detected when ppgc01 and ppgc02 outputs are active, the counter does not stop im- mediately but continues counting until the outputs become inactive. if the trigger signal level is a stop lev- el when the outputs become inactive, the counter is cleared/stopped and waits for a next start trigger. if out- put is enabled for both ppgc01 and ppgc02, triggers are accepted only when both ppgc01 and ppgc02 outputs are inactive. figure 15-13 start triggers on the tcc0 pin: falling-edge trigger (counting stopped at high level), triggers ignored when ppg outputs are active 15.5.5 configuring how the timer stops setting tc0cr3 to 0 causes the timer to stop with the specified output state according to the set- ting of tc0cr3. tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 224 2012/5/18 ra000 tcc0 pin input ppgc01 pin output (positive logic) ppgc02 pin output (positive logic) inttcc0t interrupt request inttcc0p interrupt request counter operating counter operating counter operating counter operating counter stopped counter stopped counter stopped count started count started count started count started end of a period count cleared count cleared count cleared tcc0 pin input (signal after noise elimination) ppgc01 (positive logic) ppgc02 (positive logic) inttcc0t interrupt request triggers not accepted inttcc0p interrupt request counter operating counter operating counter operating counter stopped counter stopped a trigger detected when ppgc01 and pgc02 are inactive causes the counter to stop or start. a trigger detected when ppgc01 or ppgc02 is active does not cause the counter to stop. a high level of the trigger input causes the counter to stop when ppgc01 and ppgc02 become inactive. a trigger detected when ppgc01 or ppgc02 is active does not cause the counter to stop or restart.
15.5.5.1 counting stopped with the outputs initialized when tc0cr3 is set to 00, the counter stops immediately with the ppgc01 and ppgc02 out- puts initialized to the values specified with ppgc1ini and ppgc2ini. 15.5.5.2 counting stopped with the outputs maintained when tc0cr3 is set to 01, the counter stops immediately with the current ppgc01 and ppgc02 output states maintained to restart the counter from the maintained state (tc0cr3 = 01), set tc0cr3 to 1. the counter is restarted with the initial output values, specified with ppgc1ini and ppgc2ini. 15.5.5.3 counting stopped with the outputs initialized at the end of the period when tc0cr3 is set to 10, the counter continues counting until the end of the current period and then stops. if a stop trigger is detected before the end of the period, however, the counter stops imme- diately. tc0cr1 and tc0cr2 must not be rewritten before the counter stops completely. the tc0cr3 can be read to determine whether the counter has stopped. 15.5.6 one - time/continuous output mode 15.5.6.1 one-time output mode starting the timer (tc0cr3 = 1) with tc0cr3 set to 10 specifies one-time output mode. in this mode, the timer stops counting at the end of a period. for a trigger start, the counter is stopped until a trigger is detected. a specified trigger restarts count- ing and the counter stops at the end of the period or when a stop trigger is detected, after which it waits for a trigger again. for a command start, the counter is stopped until tc0cr3 is reset to 1. tc0cr1 and tc0cr2 must not be rewritten before the counter stops completely. the tc0cr3 can be read to determine whether the counter has stopped. tc0cr3 remains set to 1 after the counter is stopped. when tc0cr3 is set to 1, setting tc0cr3 to 10 clears the counter, which then re- starts counting from the beginning in one-time output mode. 15.5.6.2 continuous output mode starting the timer (tc0cr3 = 1) with tc0cr3 set to 00 or 01 specifies continuous out- put mode. in this mode, the timer outputs specified waveforms continuously. tmp89fw20a page 225 2012/5/18 ra000
figure 15-14 immediately stopping and clearing the counter with the outputs initialized (tc0cr3 = 00) figure 15-15 immediately stopping and clearing the counter with the outputs maintained (tc0cr3 = 01) tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 226 2012/5/18 ra000 count started tccst = 1 stm = 00 output enabled ppgc1oe / ppgc2oe = 1 stop command tccst = 0 ppgc01 pin output (positive logic) ppgc1ini = 0 ppgc02 pin output (negative logic) ppgc2ini = 1 the counter is forcibly stopped and cleared, with the outputs initialized. stop command tccst = 0 ppgc01 pin output (positive logic) ppgc1ini = 0 ppgc02 pin output (negative logic) ppgc2ini = 1 count started tccst = 1 stm = 01 output enabled ppgc1oe / ppgc2oe = 1 the counter is forcibly stopped and cleared, with the outputs
figure 15-16 stopping the counter at the end of the period (tc0cr3 = 10) figure 15-17 stopping the counter at the end of the period (tc0cr3 = 10), tc0cr3 = 1 one - time output mode 15.5.7 ppg output control (initial value/output logic, enabling/disabling output) 15.5.7.1 specifying initial values and output logic for ppg outputs the tc0cr1 specify the initial values of ppgc01 and ppgc02 outputs as well as their output logic. (1) positive logic output setting the bit to 0 specifies that the output is initially low and driven high upon a match be- tween the counter value and specified dead time. (2) negative logic output setting the bit to 1 specifies that the output is initially high and driven low upon a match be- tween the counter value and specified dead time. 15.5.7.2 enabling or disabling ppg outputs the setting of the i/o port specify whether ppg outputs are enabled or disabled.when outputs are disa- bled, no ppg waveforms appear while the counter is operating, allowing the ppgc01 and ppgc02 pins to be used as normal input/output pins. tmp89fw20a page 227 2012/5/18 ra000 count started tccst = 1 stm = 00 or 01 1 period 1 period count stopped output enabled ppgc1oe / ppgc2oe = 1 stop command tccst = 0 stm = 10 ppgc01 pin output (positive logic) ppgc1ini = 0 ppgc02 pin output (negative logic) ppgc2ini = 1 after a stop command is executed, the counter continues counting until the end of the period. count started tccst = 1 stm = 10 1 period output enabled ppgc1oe / ppgc2oe = 1 count stopped at the end of the period ppgc01 pin output (positive logic) ppgc1ini = 0 ppgc02 pin output (negative logic) ppgc2ini = 1 the counter stops at the end of the period and then waits for a command start or a
15.5.7.3 using the tcc0 as a normal timer/counter the tcc0 can be used as a normal timer/counter when ppg outputs are disabled using the setting of the i/o port.in that case, use an inttcc0p interrupt, which occurs upon a match with the value speci- fied in the data register (tc0drc). setting count start mode (tc0cr2) in command start and cap- ture mode. figure 15-18 using the tcc0 as a normal timer/counter (when tc0cr3is "1") 15.5.8 eliminating noise from the tcc0 pin input a digital noise canceller eliminates noise from the input signal on the tcc0 pin. the digital noise canceller uses a sampling clock of fcgck/4, fcgck/2 or fcgck, as specified with tc0cr1, and samples the signal five times. it accepts a level input which is continuous at least over the period of time required for five samplings. any level input which does not continue over the period of time required for five samplings is canceled as noise. table 15-4 noise canceller settings tc0cr1 sampling frequency (number of samplings) pulse width always assumed as noise pulse width always assumed as signal at 8 mhz at 16 mhz at 8 mhz at 16 mhz 00 fcgck/4 (5 times) 16/fcgck [s] 2 [s] 1 [s] 20/fcgck [s] 2.5 [s] 1.25 [s] 01 fcgck/2 (5 times) 8/fcgck [s] 1 [s] 500 [ns] 10/fcgck [s] 1.25 [s] 0.625 [s] 10 fcgck (5 times) 4/fcgck [s] 0.5 [s] 250 [ns] 5/fcgck [s] 0.625 [s] 0.3125 [s] 11 (none) none - - (1/fcgck) tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 228 2012/5/18 ra000 n 01234 n/01234567 counter source clock tc0drc inttcc0p interrupt request match detected start
figure 15-19 noise canceller operation ? when tc0cr1 = 00, a tcc0 input level after passing through the f/f is always can- celed if its duration is 16/fcgck [s] or less and always assumed as a signal if its duration is 20/ fcgck [s] or greater. after the input signal supplied on the tcc0 pin passes through the f/f, there is a delay between 21/fcgck [s] and 24/fcgck [s] before the ppg outputs vary. ? when tc0cr1 = 01, a tcc0 input level after passing through the f/f is always can- celed if its duration is 8/fcgck [s] or less and always assumed as a signal if its duration is 10/fcgck [s] or greater. after the input signal supplied on the tcc0 pin passes through the f/f, there is a de- lay between 13/fcgck [s] and 14/fcgck [s] before the ppg outputs vary. ? when tc0cr1 = 10, a tcc0 input level after passing through the f/f is always can- celed if its duration is 4/fcgck [s] or less and always assumed as a signal if its duration is 5/fcgck [s] or greater. after the input signal supplied on the tcc0 pin passes through the f/f, there is a de- lay of 5/fcgck [s] before the ppg outputs vary. ? when tc0cr1 = 11, a pulse shorter than 1/fcgck may be assumed as a signal or can- celed as noise in the first-stage f/f. ensure that input signal pulses are longer than 1/fc. after the in- put signal supplied on the tcc0 pin passes through the f/f, there is a delay of 4/fcgck [s] before the ppg outputs vary. note 1: if the pin input level changes while the specified noise elimination threshold is being modified, the noise canceller may assume noise as a pulse or cancel a pulse as noise. note 2: if noise occurs in synchronization with the internal sampling timing consecutively, it may be assumed as a signal. note 3: the signal supplied on the tcc0 pin requires 1/fcgck [s] or less to pass through the f/f. 15.5.9 interrupts the tcc0 supports three interrupt sources. tmp89fw20a page 229 2012/5/18 ra000 fcgck fcgck/2 a fter noise elimination fcgck/4 when ncrsel = 00 when ncrsel = 01 when ncrsel = 10 pulses of 5/fc or longer are assumed as a signal. pulses of 10/fc or longer are assumed as a signal. pulses of 4/fc or shorter are canceled. pulses of 8/fc or shorter are canceled. pulses of 16/fc or shorter are canceled. tcc0 pin input (after passing through f/f) 1 2 3 4 5 1 2 3 4 5 1 2 3 4 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 b a z s a b z c noise canceller edge detection ppg output control f/f tcc0 input fcgck ppgc output sampling clock fcgck fcgck/2 fcgck/4 ncrsel ncrsel = 11 pulses of 20/fc or longer are assumed as a signal.
15.5.9.1 inttcc0t (trigger start interrupt) a trigger interrupt (inttcc0t) occurs when the counter starts upon the detection of a trigger edge speci- fied with tc0cr1. this interrupt does not occur with a trigger edge for clearing the count. a trig- ger edge detected in trigger capture mode does not cause an interrupt. a start trigger causes an interrupt even when the counter is stopped in emergency. figure 15-20 trigger start interrupt 15.5.9.2 inttcc0p (period interrupt) a period interrupt (inttcc0p) occurs when the counter starts with a command and when the counter is cleared with the specified counter period (tc0drc) reached, that is, at the end of a period. a match with the set period causes an interrupt even when the counter is stopped in emergency. figure 15-21 period interrupt if a command start is specified (1 is written in tc0cr3) when the tcc0 pin is at a stop lev- el, the counter does not start (inttcc0p does not occur); a subsequent trigger start edge causes the coun- ter to start and inttcc0t to occur. 15.5.9.3 intemg0 (emergency output stop interrupt) an emergency output stop interrupt (intemg0) occurs when the emergency output stop circuit oper- ates to stop ppg outputs in emergency tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 230 2012/5/18 ra000 x 0 1 2 m-2 m-1 0 1 2 0 1 2 counter tcc0 input inttcc0t interrupt request inttcc0p interrupt request ppgc output count started cleared cleared 1 period cleared upon match tc7drc x 1 2 m-2 m-2 m-1 m, 0 1 2 m-1 m, 0 counter inttcc0t interrupt request inttcc0p interrupt request ppgc output 1 period timer stopped command start command stop stop at the end of period clear upon match tc7drc 1 period csidis specifies whether the first inttcc0p occurs.
15.5.10 emergency ppg output stop feature setting tc0cr2 to 1 enables the emergency ppg output stop feature (enables the emg0 pin in- put). a low level input detected on the emg0 pin causes an emg interrupt (intemg0) to occur with the ppg waveforms initialized (as specified with ppgc1ini and ppgc2ini). (emergency ppg output stop) this feature only disables ppg outputs without stopping the counter. use the emg interrupt handler rou- tine to stop the timer. note:ensure that a low level on the emg0 pin continues for at least 4/fcgck [s]. the emergency ppg out- put stop feature may not operate normally with a low level shorter than 4/fcgck [s]. figure 15-22 emg0 pin 15.5.10.1 enabling/disabling input on the emg0 pin setting tc0cr2 to 1 enables input on the emg0 pin and setting the bit to 0 disables input on the pin. (initially, tc0cr2 is set to 0, disabling an emergency output stop ( emg0 pin) input.) the input signal on the emg0 pin is valid only when its shared port pin is placed in input mode. en- sure that the shared port pin is placed in input mode before attempting to enable the emg0 pin input. the emg0 pin input is sampled using a high-frequency clock. the emergency ppg output stop feature does not operate normally if the high-frequency clock is stopped. 15.5.10.2 monitoring the emergency ppg output stop state when the emergency ppg output stop feature activates, the tc0cr3 is set to 1. 1 read from emgf indicates that ppg outputs are disabled by the emergency ppg output stop feature. 15.5.10.3 emg interrupt an emg interrupt (intemg0) occurs when an emergency ppg output stop input is accepted. to use an intemg0 interrupt for some processing, ensure that the interrupt is enabled beforehand. when the emg0 pin is low with tc0ct2 set to 1 ( emg0 pin input enabled), an attempt to can- cel the emergency ppg output stop state results in an interrupt being generated again, with the emergen- cy ppg output stop state reestablished. an intemg interrupt occurs whenever a stop input is accepted when tc0cr2 = 1, regard- less of whether the timer is operating. tmp89fw20a page 231 2012/5/18 ra000 f/f f/f f/f sampling s q r emg interrupt (intemg0) ppg circuit output emg0 pin emgie tccst stm emgf (status flag) ppgc1ini ppgc2ini ppgc01 output ppgc02 output tc0cr1 tc0cr3 tc0cr2 emgr i/o port
15.5.10.4 canceling the emergency ppg output stop state to cancel the emergency ppg output stop state, ensure that the input on the emg0 pin is high, set tc0cr3 to 0 and tc0cr3 to 00 to stop the timer, and then set tc0cr2 to 1. setting emgr to 1 cancels the stop state only when tccst = 0 and tc0cr3 = 00; ensure that tc0cr3 = 0 and tc0cr3 = 00 before setting tc0cr2 to 1. if the input on the emg0 pin is low and tc0cr2 = 1 when the emergency ppg output stop state is canceled,the timer re-enters the emergency ppg output stop state and an intemg interrupt occurs. 15.5.10.5 restarting the timer after canceling the emergency ppg output stop state to restart the timer after canceling the emergency ppg output stop state, reconfigure the control regis- ters (tc0cr1, tc0cr2, tc0cr3) before restarting the timer. the timer cannot restart in the emergency ppg output stop state. monitor the emergency ppg output stop state and cancel the state before reconfiguring the control registers to restart the timer. ensure that the control registers are reconfigured according to the appropriate procedure for configuring timer opera- tion control. 15.5.10.6 response time between emg0 pin input and ppg outputs being initialized the time between a low level input being detected on the emg0 pin and the ppg outputs being initial- ized is up to 4/fcgck [s]. figure 15-23 timing between emg0 pin input being detected and ppg outputs being disa- bled 15.5.11 tcc0 operation and microcontroller operating mode the tcc0 operates when the microcontroller is placed in normal1, normal2, idle1, or idle2 mode. if the mode changes from normal or idle to stop, slow, or sleep while the tcc0 is operat- ing, the tcc0 is initialized and stops operating. tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 232 2012/5/18 ra000 ppgc pin output emg0 pin input tc0cr2 4/fcgck [s] tc0cr3 tc0cr3 tc0cr3 (state monitor) intemg0 interrupt request tc0cr2 specified with an instruction emergency stop output initialized forcibly initial output state emergency stop input share port in input mode emgr = 1, protection feature enabled emgf = 1, emergency output stop state emergency output stop state tccst = 1, timer operating stm = 01, timer operating (continuous mode) emgr = 1, cancel emergency output stop state 00 tccst = 0
to change the microcontroller operating mode from normal to stop, slow, or sleep, ensure that the tcc0 timer is stopped before attempting to execute a mode change instruction. to change the mode from stop, slow, or sleep to normal to restart the tcc0, reconfigure all reg- isters according to the appropriate tcc0 operation procedure. 15.5.12 considerations for using the development tools of tcc0 when stopped a program by the break of the debugger, tcc0 suspend ppg output,and change to initial val- ue depend on tc0cr1 setting. when the break is released, ppg output is restar- ted from the point at which it was suspended. the setting of development tools can continue ppg output dur- ing break. for detail refer to the instruction manual of the development tools. tmp89fw20a page 233 2012/5/18 ra000
tmp89fw20a 15. 10-bit timer/counter (tcc) 15.5 features page 234 2012/5/18 ra000
16. 8-bit timer counter (tc0) the tmp89fw20a contains 4 channels of high-performance 8-bit timer counters (tc0). each timer can be used for time measurement and pulse output with a prescribed width. two 8-bit timer counters are cascadable to form a 16-bit timer. this chapter describes 2 channels of 8-bit timer counters 00 and 01. for 8-bit timer counters 02 and 03, replace the sfr addresses and pin names as shown in table 16-1 and table 16-2. table 16-1 sfr address assignment 16-bit mode t0xreg (address) t0xpwm (address) t0xmod (address) t0xxcr (address) low power consumption register timer counter 00 lower t00reg (0x00026) t00pwm (0x00028) t00mod (0x0002a) t001cr (0x0002c) poffcr0 timer counter 01 higher t01reg (0x00027) t01pwm (0x00029) t01mod (0x0002b) timer counter 02 lower t02reg (0x00f88) t02pwm (0x00f8a) t02mod (0x00f8c) t023cr (0x00f8e) poffcr0 timer counter 03 higher t03reg (0x00f89) t03pwm (0x00f8b) t03mod (0x00f8d) table 16-2 pin names timer input pin pwm output pin ppg output pin timer counter 00 tc00 pin pwm0 pin ppg0 pin timer counter 01 tc01 pin pwm1 pin ppg1 pin timer counter 02 tc02 pin pwm2 pin ppg2 pin timer counter 03 tc03 pin pwm3 pin ppg3 pin tmp89fw20a page 235 2012/5/18 ra005
16.1 configuration figure 16-1 8-bit timer counters 00 and 01 tmp89fw20a 16. 8-bit timer counter (tc0) 16.1 configuration page 236 2012/5/18 ra005 t01reg selector selector selector selector reading and writing of t01reg reading and writing of t01pwm t01pwm internal bus 01 0 0 0 1 1 1 comparator comparator 8-bit up counter 8-bit up counter comparator comparator t00reg dbe1 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fcgck or fs/2 2 i a b c d e f g h y s0 s1 1 0 y s 0 1 y s 1 0 y s selector selector selector selector overflow clear count up count up clear overflow timer/event count modes 8/16-bit ppg mode reading and writing of t00reg reading and writing of t00pwm t00pwm double buffer double buffer double buffer double buffer 01 0 0 0 1 1 1 inttc01 interrupt request ppg1 pwm1 pin output tff1 internal bus t01mod t001cr 2 tck1 ein1 tff0 tcm0 dbe0 dbe1 tcm1 tff1 outand tcas tc00run tc01run t00mod tck0 ein0 2 2 2 tc00 pin input fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fcgck or fs/2 2 i a b c d e f g h y s0 s1 tc01 pin input 8-bit pwm mode counter f/f 12-bit pwm mode 8-bit pwm mode counter 12-bit pwm mode timer/event count modes 8-bit ppg mode tcas tcas tcas inttc00 interrupt request 16-bit ppg mode ppg0 pwm0 pin output f/f 1 0 y s outand tff0
16.2 control 16.2.1 timer counter 00 the timer counter 00 is controlled by the timer counter 00 mode register (t00mod) and two 8-bit timer reg- isters (t00reg and t00pwm). timer register 00 t00reg 15 14 13 12 11 10 9 8 (0x00026) bit symbol t00reg read/write r/w after reset 1 1 1 1 1 1 1 1 timer register 00 t00pwm 7 6 5 4 3 2 1 0 (0x00028) bit symbol t00pwm read/write r/w after reset 1 1 1 1 1 1 1 1 note 1: for the configuration of t00pwm in the 8-bit and 12-bit pwm modes, refer to "16.4.3 8-bit pulse width modulation (pwm) output mode" and "16.4.7 12-bit pulse width modulation (pwm) output mode". tmp89fw20a page 237 2012/5/18 ra005
timer counter 00 mode register t00mod 7 6 5 4 3 2 1 0 (0x0002a) bit symbol tff0 dbe0 tck0 ein0 tcm0 read/write r/w r/w r/w r/w r/w after reset 1 1 0 0 0 0 0 0 tff0 timer f/f0 control 0 1 clear set dbe0 double buffer control 0 1 disable the double buffer enable the double buffer tck0 operation clock selection normal1/2 or idle1/2 mode slow1/2 or sleep1 mode syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 001 fcgck/2 10 fs/2 3 fs/2 3 010 fcgck/2 8 fcgck/2 8 - 011 fcgck/2 6 fcgck/2 6 - 100 fcgck/2 4 fcgck/2 4 - 101 fcgck/2 2 fcgck/2 2 - 110 fcgck/2 fcgck/2 - 111 fcgck fcgck fs/2 2 ein0 selection for using external source clock 0 1 select the internal clock as the source clock. select an external clock as the source clock. (the falling edge of the tc00 pin) tcm0 operation mode selection 00 8-bit timer/event counter modes 01 8-bit timer/event counter modes 10 8-bit pulse width modulation output (pwm) mode 11 8-bit programmable pulse generate (ppg) mode note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: set t00mod while the timer is stopped. writing data into t00mod is invalid during the timer operation. note 3: in the 8-bit timer/event modes, the tff0 setting is invalid. in this mode, when the pwm0 and ppg0 pins are set as the function output pins in the port setting, the pins always output the "h" level. note 4: when ein0 is set to "1" and the external clock input is selected as the source clock, the tck0 setting is ignored. note 5: when the t001cr bit is "1", timer 00 operates in the 16-bit mode. the t00mod setting is invalid and timer 00 cannot be used independently in this mode. when the pwm0 and ppg0 pins are set to the function output pins in the port setting, the pins always output the "h" level. note 6: when the 16-bit mode is selected at t001cr, the timer start is controlled at t001cr. timer 00 is not started by writing data into t001cr. tmp89fw20a 16. 8-bit timer counter (tc0) 16.2 control page 238 2012/5/18 ra005
16.2.2 timer counter 01 timer counter 01 is controlled by timer counter 01 mode register (t01mod) and two 8-bit timer registers (t01reg and t01pwm). timer register 01 t01reg 15 14 13 12 11 10 9 8 (0x00027) bit symbol t01reg read/write r/w after reset 1 1 1 1 1 1 1 1 timer register 01 t01pwm 7 6 5 4 3 2 1 0 (0x00029) bit symbol t01pwm read/write r/w after reset 1 1 1 1 1 1 1 1 note 1: for the configuration of t00pwm in the 8-bit and 12-bit pwm modes, refer to "16.4.3 8-bit pulse width modulation (pwm) output mode" and "16.4.7 12-bit pulse width modulation (pwm) output mode". tmp89fw20a page 239 2012/5/18 ra005
timer counter 01 mode register t01mod 7 6 5 4 3 2 1 0 (0x0002b) bit symbol tff1 dbe1 tck1 ein1 tcm1 read/write r/w r/w r/w r/w r/w after reset 1 1 0 0 0 0 0 0 tff1 timer f/f1 control 0 1 clear set dbe1 double buffer control 0 1 disable the double buffer enable the double buffer tck1 operation clock selection normal1/2 or idle1/2 mode slow1/2 or sleep1 mode syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 001 fcgck/2 10 fs/2 3 fs/2 3 010 fcgck/2 8 fcgck/2 8 - 011 fcgck/2 6 fcgck/2 6 - 100 fcgck/2 4 fcgck/2 4 - 101 fcgck/2 2 fcgck/2 2 - 110 fcgck/2 fcgck/2 - 111 fcgck fcgck fs/2 2 ein1 selection for using external source clock 0 1 select the internal clock as the source clock. select an external clock as the source clock. (the falling edge of the tc01 pin) tcm1 operation mode selection t001cr="0" (8-bit mode) t001cr="1" (16-bit mode) 00 8-bit timer/event counter modes 16-bit timer/event counter modes 01 8-bit timer/event counter modes 16-bit timer/event counter modes 10 8-bit pulse width modulation out- put (pwm) mode 12-bit pulse width modulation out- put (pwm) mode 11 8-bit programmable pulse gener- ate (ppg) mode 16-bit programmable pulse gener- ate (ppg) mode note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: set t01mod while the timer is stopped. writing data into t01mod is invalid during the timer operation. note 3: in the 8-bit timer/event modes, the tff1 setting is invalid. in this mode, when the pwm1 and ppg1 pins are set as the function output pins in the port setting, the pins always output the "h" level. note 4: when ein1 is set to "1" and the external clock input is selected as the source clock, the tck1 setting is ignored. tmp89fw20a 16. 8-bit timer counter (tc0) 16.2 control page 240 2012/5/18 ra005
16.2.3 common to timer counters 00 and 01 timer counters 00 and 01 have the low power consumption register (poffcr0) and timer 00 and 01 con- trol registers in common. low power consumption register 0 poffcr0 7 6 5 4 3 2 1 0 (0x00f74) bit symbol - - tc023en tc001en - tcc0en tcb0en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tcc0en tcc0 control 0 1 disable enable tcb0en tcb0 control 0 1 disable enable tca0en tca0 control 0 1 disable enable tmp89fw20a page 241 2012/5/18 ra005
timer counter 01 control register t001cr 7 6 5 4 3 2 1 0 (0x0002c) bit symbol - - - - outand tcas t01run t00run read/write r r r r r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 outand timers 00 and 01 output control 0 output the timer 00 output from the pwm0 and ppg0 pins and the tim- er 01 output from the pwm1 and ppg1 pins. 1 output a pulse that is a logical anded product of the outputs of timers 00 and 01 from the pwm1 and ppg1 pins. tcas timers 00 and 01 cascade control 0 1 use timers 00 and 01 independently (8-bit mode). cascade timers 00 and 01 (16-bit mode). t01run timer 01 control timers 00/01 control (16-bit mode) 0 1 stop and clear the counter start t00run timer 00 control 0 1 stop and clear the counter start note 1: when stop mode is started, t00run and t01run are cleared to "0" and the timers stop. set t001cr again to use timers 00 and 01 after stop mode is released. note 2: when a read instruction is executed on t001cr, bits 7 to 4 are read as "0". note 3: when outand is "1", output is obtained from the pwm1 and ppg1 pins only. there is no timer output to the pwm0 and ppg0 pins. if the pwm0 and ppg0 pins are set as the function output pins in the port setting, the pins al- ways output "h". note 4: outand and tcas can be changed only when both tc01run and tc00run are "0". when either tc01run or tc00run is "1" or both are "1", the register values remain unchanged by executing write instructions on outand and tcas. outand and tcas can be changed at the same time as tc01run and tc00run are changed from "0" to "1". tmp89fw20a 16. 8-bit timer counter (tc0) 16.2 control page 242 2012/5/18 ra005
16.2.4 operation modes and usable source clocks the operations modes of the 8-bit timers and the usable source clocks are listed below. table 16-3 operation modes and usable source clocks (normal1/2 and idle1/2 modes) tck0 000 001 010 011 100 101 110 111 tc0i pin input operation mode fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fcgck 8-bit timer modes 8-bit timer - 8-bit event counter - - - - - - - - 8-bit pwm - 8-bit ppg - 16-bit timer modes 16-bit timer - 16-bit event counter - - - - - - - - 12-bit pwm 16-bit ppg note 1: : usable, -: unusable note 2: set the source clock in the 16-bit modes on the tc01 side (tck1). note 3: when the low-frequency clock, fs, is not oscillating, it must not be selected as the source clock. if fs is selected when it is not oscillating, no source clock is supplied to the timer, and the timer remains stopped. note 4: i=0, 1 (i=0 only in the 16-bit modes) note 5: the operation modes of the 8-bit timers and the usable source clocks are listed below. table 16-4 operation modes and usable source clocks (slow1/2 and sleep1 modes) tck0 000 001 010 011 100 101 110 111 tc0i pin input operation mode fs/2 4 fs/2 3 - - - - - fs/2 2 8-bit timer modes 8-bit timer - - - - - - 8-bit event counter - - - - - - - - 8-bit pwm - - - - - - 8-bit ppg - - - - - - 16-bit timer modes 16-bit timer - - - - - - 16-bit event counter - - - - - - - - 12-bit pwm - - - - - 16-bit ppg - - - - - note 1: : usable, -: unusable note 2: set the source clock in the 16-bit modes on the tc01 side (tck1). note 3: i=0, 1 (i=0 only in the 16-bit modes) tmp89fw20a page 243 2012/5/18 ra005
16.3 low power consumption function timer counters 00 and 01 have the low power consumption registers (poffcr0) that save power when the timers are not used. setting poffcr0 to "0" disables the basic clock supply to timer counters 00 and 01 to save pow- er. note that this renders the timers unusable. setting poffcr0 to "1" enables the basic clock sup- ply to timer counters 00 and 01 and allows the timers to operate. after reset, poffcr0 are initialized to "0", and this makes the timers unusable. when using the timers for the first time, be sure to set poffcr0 to "1" in the initial setting of the program (before the timer control registers are operated). do not change poffcr0 to "0" during the timer operation. otherwise timer counters 00 and 01 may operate unexpectedly. tmp89fw20a 16. 8-bit timer counter (tc0) 16.3 low power consumption function page 244 2012/5/18 ra005
16.4 functions timer counters tc00 and tc01 have 8-bit modes in which they are used independently and 16-bit modes in which they are cascaded. the 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse width modulation output (pwm) mode and the 8-bit programmable pulse generated output (ppg) mode. the 16-bit modes include four operation modes; the 16-bit timer mode, the 16-bit event counter mode, the 12- bit pwm mode and the 16-bit ppg mode. 16.4.1 8-bit timer mode in the 8-bit timer mode, the up-counter counts up using the internal clock, and interrupts can be generated reg- ularly at specified times. the operation of tc00 is described below, and the same applies to the operation of tc01. (replace tc00- by tc01-). 16.4.1.1 setting tc00 is put into the 8-bit timer mode by setting t00mod to "00" or "01", t001cr to "0" and t00mod to "0". select the source clock at t00mod. set the count value to be used for the match detection as an 8-bit value at the timer register t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod be- comes invalid. be sure to complete the required mode settings before starting the timer. 16.4.1.2 operation setting t001cr to "1" allows the 8-bit up counter to increment based on the selected inter- nal source clock. when a match between the up counter value and the t00reg set value is detected, an inttc00 interrupt request is generated and the up counter is cleared to "0x00". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x00". 16.4.1.3 double buffer the double buffer can be used for t00reg by setting t00mod. the double buffer is disa- bled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is executed on t00reg during the timer operation, the set value is initially stored in the double buffer, and t00reg is not immediately updated. t00reg com- pares the previous set value with the up counter value. when the values match, an inttc00 in- terrupt request is generated and the double buffer set value is stored in t00reg. subsequent- ly, the match detection is executed using a new set value. when a write instruction is executed on t00reg while the timer is stopped, the set value is immediately stored in both the double buffer and t00reg. ? when the double buffer is disabled when a write instruction is executed on t00reg during the timer operation, the set value is immediately stored in t00reg. subsequently, the match detection is executed using a new set value. if the value set to t00reg is smaller than the up counter value, the match detection is execu- ted using a new set value after the up counter overflows. therefore, the interrupt request inter- val may be longer than the selected time. if the value set to t00reg is equal to the up coun- tmp89fw20a page 245 2012/5/18 ra005
ter value, the match detection is executed immediately after data is written into t00reg. there- fore, the interrupt request interval may not be an integral multiple of the source clock (figure 16-3). if these are problems, enable the double buffer. when a write instruction is executed on t00reg while the timer is stopped, the set value is immediately stored in t00reg. when a read instruction is executed on t00reg, the last value written into t00reg is read out, regard- less of the t00mod setting. table 16-5 8-bit timer mode resolution and maximum time setting t00mod source clock [hz] resolution maximum time setting normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8s 488.2s 52.2ms 124.5ms 001 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 26.1ms 62.3ms 010 fcgck/2 8 fcgck/2 8 - 25.6s - 6.5ms - 011 fcgck/2 6 fcgck/2 6 - 6.4s - 1.6ms - 100 fcgck/2 4 fcgck/2 4 - 1.6s - 408s - 101 fcgck/2 2 fcgck/2 2 - 400ns - 102s - 110 fcgck/2 fcgck/2 - 200ns - 51s - 111 fcgck fcgck fs/2 2 100ns 122.1s 25.5s 31.1ms (example) operate tc00 in the 8-bit timer mode with the operation clock of fcgck/2 2 [hz] and generate interrupts at 64 s intervals (fcgck = 10 mhz) ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xe8 ; selects the 8-bit timer mode and fcgck/2 2 ld (t00reg),0xa0 ; sets the timer register (64s / (2 2 /fcgck) = 0xa0) set (t001cr).0 ; starts tc00 tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 246 2012/5/18 ra005
figure 16-2 timer mode timing chart figure 16-3 operation when t00reg and the up counter have the same value tmp89fw20a page 247 2012/5/18 ra005 source clock counter timer start 1 0 m write to t00reg match detection write m write n reflected by writing to t00reg reflected by writing to t00reg reflected by an interrupt reflected at the same time as data is written into t00reg while the timer is stopped counter clear inttc00 interrupt request 234 m-1 m 01 n 01 220 3 t00reg t001cr n timer stop match detection counter clear n-1 t00mod when the double buffer is disabled (t00mod=?0?) source clock counter timer start 1 0 m write to t00reg match detection write m write n counter clear inttc00 interrupt request 234 m-1 m 01 m 01 23 t00reg t001cr n m double buffer n match detection match detection counter clear 01 m-1 n n-1 t00mod when the double buffer is enabled (t00mod=?1?) source clock counter n-4 n-5 n-2 n write to t00reg write n-2 inttc00 interrupt request n-3 n-2 0 1 2 t00reg match detection counter clear t00mod
16.4.2 8-bit event counter mode in the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the tc00 or tc01 pin. the operation of tc00 is described below, and the same applies to the operation of tc01. 16.4.2.1 setting tc00 is put into the 8-bit event counter mode by setting t00mod to "00", t001cr to "0" and t00mod to "1". set the count value to be used for the match detection as an 8-bit val- ue at the timer register t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod be- comes invalid. be sure to complete the required mode settings before starting the timer. 16.4.2.2 operation setting t001cr to "1" allows the 8-bit up counter to increment at the falling edge of the tc00 pin. when a match between the up-counter value and the t00reg set value is detected, an inttc00 interrupt request is generated and the up counter is cleared to "0x00". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x00". the maximum frequency to be supplied is fcgck/2 2 [hz] (in normal1/2 or idle1/2 mode) or fs/24 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two machine cycles or more is required at both the "h" and "l" levels. 16.4.2.3 double buffer refer to "16.4.1.3 double buffer". (example) operate tc00 in the 8-bit event counter mode and generate an interrupt each time 16 falling edges are de- tected at the tc00 pin. ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xc4 ; selects to the 8-bit event counter mode ld (t00reg),0x10 ; sets the timer register set (t001cr).0 ; starts tc00 tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 248 2012/5/18 ra005
figure 16-4 event counter mode timing chart tmp89fw20a page 249 2012/5/18 ra005 tc00 pin input counter timer start when the double buffer is disabled (t00mod=?0?) 1 0 m write to t00reg match detection write m write n reflected by writing to t00reg reflected by writing to t00reg counter clear inttc00 interrupt request 23 4 m-1 m 01 n 01 220 3 t00reg t001cr n timer stop match detection counter clear n-1
16.4.3 8-bit pulse width modulation (pwm) output mode the pulse-width modulated pulses with a resolution of 7 bits are output in the 8-bit pwm mode. an addition- al pulse can be added to the 2 n-th duty pulse. this enables pwm output with a resolution nearly equiva- lent to 8 bits. (n=1, 2, 3...) the operation of tc00 is described below, and the same applies to the operation of tc01. 16.4.3.1 setting tc00 is put into the 8-bit pwm mode by setting t00mod to "10" and t001cr to "0". set t00mod to "0" and select the clock at t00mod. set the count value to be used for the match detection and the additional pulse value at the pwm register t00pwm. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod be- comes invalid. be sure to complete the required mode settings before starting the timer. in the 8-bit pwm mode, the t00pwm register is configured as follows: timer register 00 t00pwm 7 6 5 4 3 2 1 0 (0x00028) bit symbol pwmduty pwmad read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 timer register 01 t01pwm 7 6 5 4 3 2 1 0 (0x00029) bit symbol pwmduty pwmad read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 pwmduty is a 7-bit register used to set the duty pulse width value (the time before the first output change) in a cycle (128 counts of the source clock). pwmad is a register used to set the additional pulse. when pwmad is "1", an additional pulse that cor- responds to 1 count of the source clock is added to the 2 n-th duty pulse (n=1, 2, 3...). in other words, the 2 n-th duty pulse has the output of pwmduty+1. the additional pulse is not added when pwmad is "0". tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 250 2012/5/18 ra005
figure 16-5 pwm0 pulse output set the initial state of the pwm0 pin at t00mod. setting t00mod to "0" selects the "l" level as the initial state of the pwm0 pin. setting t00mod to "1" selects the "h" level as the initial state of the pwm0 pin. if the pwm0 pin is set as the function output pin in the port setting while the timer is stopped, the value of t00mod is output to the pwm0 pin. table 16-6 shows the list of output levels of the pwm0 pin. table 16-6 list of output levels of pwm0 pin tff0 pwm0 pin output level before the start of operation (initial state) t00pwm matched (after the addi- tional pulse) overflow operation stop- ped (initial state) 0 l h l l 1 h l h h and by setting "1" to t001cr bit, a logical product (and) pulse of tc00 and tc01s out- put can be output to pwm0 pin. by using this function, the remote-control waveform can be created eaily. 16.4.3.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the lower 7 bits of the up counter value and the value set to t00pwm is detected, the output of the pwm0 pin is reversed. when t00mod is "0", the pwm0 pin changes from the "l" to "h" level. when t00mod is "1", the pwm0 pin changes from the "h" to "l" level. if t00pwm is "1", an additional pulse that corresponds to 1 count of the source clock is add- ed at the 2 n-th match detection (n=1, 2, 3...). in other words, the pwm0 pin output is reversed at the tim- ing of t00pwm+1. when t00mod is "0", the period of the "l" level becomes lon- ger than the value set to t00 by 1 source clock. when t00mod is "1", the peri- od of the "h" level becomes longer than the value set to t00pwm by 1 source clock. this function allows two cycles of output pulses to be handled with a resolution nearly equivalent to 8 bits. no additional pulse is inserted when t00pwm is "0". subsequently, the up counter continues counting up. when the up counter value reaches 128, an over- flow occurs and the up counter is cleared to "0x00". at the same time, the output of the pwm0 pin is re- versed. when t00mod is "0", the pwm0 pin changes from the "h" to "l" level. when tmp89fw20a page 251 2012/5/18 ra005 t00pwm timer start additional pulse (duty pulse width) 128 counts (cycle width) 128 counts (cycle width) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 pwm0 pin output (tff0=?1?) t00pwm (duty pulse width) additional pulse additional pulse pwm0 pin output (tff0=?0?) inttc00 interrupt request
t00mod is "1", the pwm0 pin changes from the "l" to "h" level. if the 2 n-th overflow oc- curs at this time, an inttc00 interrupt request is generated. (no interrupt request is generated at the 2 n-th -1 overflow.) subsequently, the up counter continues counting up. when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x00". the pwm0 pin returns to the level selected at t00mod. (example) operate tc00 in the 8-bit pwm mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 11.6 s (fcgck = 10 mhz) (actually, output a total duty pulse of 23.2 s in 2 cycles (51.2 s)) set (p9fc).4 ; sets p9fc4 to "1" set (p9cr).4 ; sets p9cr4 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xf2 ; selects the 8-bit pwm mode and fcgck/2 ld (t00pwm),0x74 ; sets the timer register (duty pulse) ; (11.6s 2) / (2/fcgck) = 0x74 set (t001cr).0 ; starts tc00 figure 16-6 8-bit pwm mode timing chart tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 252 2012/5/18 ra005 source clock counter timer start 1 0 m m m (duty pulse) 128 counts (cycle 1) 128 counts (cycle 2) 128 counts (cycle 3) 128 counts (cycle 4) rs rs write to t00pwm double buffer write m write r write s becomes the level selected at tff0 while the timer is stopped reflected by an interrupt request interrupt request reflected by an interrupt request returns to the level selected at tff0 inttc00 interrupt request 1 m+1 m0 t00pwm t00pwm t001cr no interrupt request is generated no interrupt request is generated 128 timer stop match detection m+1 m 1 0 128 r+1 r 1 0 128 r+1 r 1 00 128 match detection match detection counter clear overflow overflow overflow counter clear counter clear counter clear t00mod pwm0 pin output when the double buffer is enabled (t00mod=?1?) m (duty pulse) r (duty pulse) r+1 (duty pulse) additional pulse match detection
16.4.3.3 double buffer the double buffer can be used for t00pwm by setting t00mod. the double buffer is disa- bled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is executed on t00pwm during the timer operation, the set value is first stored in the double buffer, and t00pwm is not updated immediately. t00pwm com- pares the previous set value with the up counter value. when the 2 n-th overflow occurs, an inttc00 interrupt request is generated and the double buffer set value is stored in t00pwm. subsequently, the match detection is executed using a new set value. when a read instruction is executed on t00pwm, the value in the double buffer (the last set value) is read out, not the t00pwm value (the currently effective value). when a write instruction is executed on t00pwm while the timer is stopped, the set value is immediately stored in both the double buffer and t00pwm. ? when the double buffer is disabled when a write instruction is executed on t00pwm during the timer operation, the set value is immediately stored in t00pwm. subsequently, the match detection is executed using a new set value. if the value set to t00pwm is smaller than the up counter value, the pwm0 pin is not reversed until the up counter overflows and a match detection is executed using a new set val- ue. if the value set to t00pwm is equal to the up counter value, the match detection is execu- ted immediately after data is written into t00pwm. therefore, the timing of changing the pwm0 pin may not be an integral multiple of the source clock (figure 16-7). similarly, if t00pwm is set during the additional pulse output, the timing of changing the pwm0 pin may not be an integral multiple of the source clock. if these are problems, enable the double buffer. when a write instruction is executed on t00pwm while the timer is stopped, the set value is immediately stored in t00pwm. figure 16-7 operation when t00pwm and the up counter have the same value tmp89fw20a page 253 2012/5/18 ra005 source clock counter n-4 n-5 n-2 n write to t00pwm write n-2 pwm0 pin output n-3 n-2 n-1 n t00pwm match detection t00mod
table 16-7 resolutions and cycles in the 8-bit pwm mode t00mod source clock [hz] resolution 7-bit cycle (period 2) normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8s 488.2s 26.2ms (52.4ms) 62.5ms (125ms) 001 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 13.1ms (26.2ms) 31.3ms (62.5ms) 010 fcgck/2 8 fcgck/2 8 - 25.6s - 3.3ms (6.6ms) - 011 fcgck/2 6 fcgck/2 6 - 6.4s - 819.2s (1638.4s) - 100 fcgck/2 4 fcgck/2 4 - 1.6s - 204.8s (409.6s) - 101 fcgck/2 2 fcgck/2 2 - 400ns - 51.2s (102.4s) - 110 fcgck/2 fcgck/2 - 200ns - 25.6s (51.2s) - 111 fcgck fcgck fs/2 2 100ns 122.1s 12.8s (25.6s) 15.6ms (31.3ms) tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 254 2012/5/18 ra005
16.4.4 8-bit programmable pulse generate (ppg) output mode in the 8-bit ppg mode, the pulses with arbitrary duty and cycle are output by using the t00reg and t00pwm registers. by setting the t001cr register, a pulse that is a logical anded product of the tc00 and tc01 outputs can be output to the tc01 pin. this function facilitates the generation of remote-controlled wave- forms, for example. the operation of tc00 is described below, and the same applies to the operation of tc01. 16.4.4.1 setting tc00 is put into the 8-bit ppg mode by setting t00mod to "11" and t001cr to "0". set t00mod to "0" and select the clock at t00mod. set the duty pulse width at t00pwm and the cycle width at t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod be- comes invalid. be sure to complete the required mode settings before starting the timer. figure 16-8 ppg0 pulse output set the initial state of the ppg0 pin at t00mod. setting t00mod to "0" selects the "l" level as the initial state of the ppg0 pin. setting t00mod to "1" selects the "h" level as the initial state of the ppg0 pin. if the ppg0 pin is set as the function output pin in the port setting while the timer is stopped, the value of t00mod is output to the ppg0 pin. table 16-8 shows the list of out- put levels of the ppg0 pin. table 16-8 list of output levels of ppg0 pin tff0 ppg0 pin output level before the start of operation (initial state) t00pwm matched t00reg matched operation stop- ped (initial state) 0 l h l l 1 h l h h setting the t001cr bit to "1" allows the ppg0 pin to output a pulse that is a logical an- ded product of the tc00 and tc01 outputs. tmp89fw20a page 255 2012/5/18 ra005 t00pwm timer start (duty pulse) (duty pulse) (1 cycle) (1 cycle) t00reg ppg0 pin output (tff0=?0?) ppg0 pin output (tff0=?1?) timer stop t00pwm t00reg
16.4.4.2 operation setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the internal up counter value and the value set to t00pwm is detected, the output of the ppg0 pin is reversed. when t00mod is "0", the ppg0 pin changes from the "l" to "h" level. when t00mod is "1", the ppg0 pin changes from the "h" to "l" level. subsequently, the up counter continues counting up. when a match between the up counter value and t00reg is detected, the output of the ppg0 pin is reversed again. when t00mod is "0", the ppg0 pin changes from the "h" to "l" level. when t00mod is "1", the ppg0 pin changes from the "l" to "h" level. at this time, an inttc00 interrupt request is generated. when t001cr is set to "0" during the operation, the up counter is stopped and cleared to "0x00". the ppg0 pin returns to the level selected at t00mod. 16.4.4.3 double buffer the double buffer can be used for t00pwm and t00reg by setting t00mod. the double buf- fer is disabled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is executed on t00pwm (t00reg) during the timer operation, the set value is first stored in the double buffer, and t00pwm (t00reg) is not updated imme- diately. t00pwm (t00reg) compares the previous set value with the up counter value. when an inttc00 interrupt request is generated, the double buffer set value is stored in t00pwm (t00reg). subsequently, the match detection is executed using a new set value. when a read instruction is executed on t00pwm (t00reg), the value in the double buffer (the last set value) is read out, not the t00pwm (t00reg) value (the currently effective value). when a write instruction is executed on t00pwm (t00reg) while the timer is stopped, the set value is immediately stored in both the double buffer and t00pwm (t00reg). ? when the double buffer is disabled when a write instruction is executed on t00pwm (t00reg) during the timer operation, the set value is immediately stored in t00pwm (t00reg). subsequently, the match detection is executed using a new set value. if the value set to t00pwm (t00reg) is smaller than the up counter value, the ppg0 pin is not reversed until the up counter overflows and a match detec- tion is executed using a new set value. if the value set to t00pwm (t00reg) is equal to the up counter value, the match detection is executed immediately after data is written into t00pwm (t00reg). therefore, the timing of changing the ppg0 pin may not be an integral multiple of the source clock (figure 16-10). if these are problems, enable the double buffer. when a write instruction is executed on t00pwm (t00reg) while the timer is stopped, the set value is immediately stored in t00pwm (t00reg). tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 256 2012/5/18 ra005
(example) operate tc00 in the 8-bit ppg mode with the operation clock of fcgck/2 and output the 8s duty pulse in 32s cycles (fcgck = 10 mhz) set (p9fc).4 ; sets p9fc4 to "1" set (p9cr).4 ; sets p9cr4 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xf3 ; selects the 8-bit ppg mode and fcgck/2 ld (t00reg),0xa0 ; sets the timer register (cycle) ; 32s / (2/fcgck) = 0xa0 ld (t00pwm),0x28 ; sets the timer register (duty pulse) ; 8s / (2/fcgck) = 0x28 set (t001cr).0 ; starts tc00 figure 16-9 8-bit ppg mode timing chart tmp89fw20a page 257 2012/5/18 ra005 source clock counter timer start 1 0 m m m (duty pulse) p (1 cycle) s (1 cycle) s (1 cycle) w (1 cycle) rt rs write to t00pwm double buffer match detection write m write r write t becomes the level selected at tff0 while the timer is stopped returns to the level selected at tff0 inttc00 interrupt request 1 m+1 m0 t00pwm t001cr ps w write to t00reg double buffer write p write s write w p timer stop match detection r+1 r 1 0 s r+1 r 1 0 s t+1 t 1 00 w match detection match detection counter clear counter clear counter clear counter clear t00mod ppg0 pin output when the double buffer is enabled (t00mod=?1?) r (duty pulse) r (duty pulse) t (duty pulse) ps w t00reg match detection match detection match detection
figure 16-10 operation when t00pwm (t00reg) and the up counter have the same value tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 258 2012/5/18 ra005 source clock counter n-4 n-5 n-2 n write to t00pwm (t00reg) write n-2 ppg0 pin output n-3 n-2 n-1 n t00pwm (t00reg) match detection t00mod
16.4.5 16-bit timer mode in the 16-bit timer mode, tc00 and tc01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit timer. 16.4.5.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit mode. the 16-bit timer mode is activated by setting t01mod to "00" or "01" and t01mod to "0". select the source clock at t01mod. set the count value to be used for the match detection as a 16-bit value at the timer registers t00reg and t01reg. set the lower 8 bits of the 16-bit value at t00reg and the higher 8 bits at t01reg. (here- inafter, the 16-bit value specified by the combined setting of t01reg and t00reg is indicated as t01 +00reg.) the timer register settings are reflected on the double buffer or t01+00reg when a write instruc- tion is executed on t01reg. be sure to execute the write instructions on t00reg and t01reg in this or- der. (when data is written to the high-order register, the set values of the low-order and high-order regis- ters become effective at the same time.) set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod be- comes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) 16.4.5.2 operations setting t001cr to "1" allows the 16-bit up counter to increment based on the selected inter- nal source clock. when a match between the up counter value and the t00+01reg set value is detected, an inttc01 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x0000". 16.4.5.3 double buffer the double buffer can be used for t01+00reg by setting t01mod. the double buffer is dis- abled by setting t01mod to "0" or enabled by setting t01mod to "1". ? when the double buffer is enabled when write instructions are executed on t00reg and t01reg in this order during the tim- er operation, the set value is first stored in the double buffer, and t01+00reg is not updated im- mediately. t01+00reg compares the previous set value with the up counter value. when the val- ues are matched, an inttc01 interrupt request is generated and the double buffer set value is stored in t01+00reg. subsequently, the match detection is executed using a new set value. when write instructions are executed on t00reg and t01reg in this order while the tim- er is stopped, the set value is immediately stored in both the double buffer and t01+00reg. ? when the double buffer is disabled when write instructions are executed on t00reg and t01reg in this order during the tim- er operation, the set value is immediately stored in t01+00reg. subsequently, the match detec- tion is executed using a new set value. if the value set to t01+00reg is smaller than the up counter value, the match detection is exe- cuted using a new set value after the up counter overflows. therefore, the interrupt request inter- tmp89fw20a page 259 2012/5/18 ra005
val may be longer than the selected time. if the value set to t01+00reg is equal to the up coun- ter value, the match detection is executed immediately after data is written into t01+00reg. therefore, the interrupt request interval may not be an integral multiple of the source clock. if these are problems, enable the double buffer. when write instructions are executed on t00reg and t01reg in this order while the tim- er is stopped, the set value is immediately stored in t01+00reg. when a read instruction is executed on t01+00reg, the last value written into t01+00reg is read out, regardless of the t00mod setting. (example) operate tc00 and tc01 in the 16-bit timer mode with the operation clock of fcgck/2 [hz] and generate inter- rupts at 96 s intervals (fcgck = 10 mhz) ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf0 ; selects the 16-bit timer mode and fcgck/2 ld (t00reg),0xe0 ; sets the timer register (96s / (2/fcgck) = 0x1e0) ld (t01reg),0x01 ; sets the timer register ld (t001cr),0x06 ; starts tc00 and tc001 (16-bit mode) tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 260 2012/5/18 ra005
figure 16-11 16-bit timer counter timing chart tmp89fw20a page 261 2012/5/18 ra005 source clock counter timer start 1 0 write to t00reg write m write r reflected by writing to t01reg reflected by writing to t01reg reflected by an interrupt reflected simultaneously by writing to t01reg while the timer is stopped counter clear inttc01 interrupt request 234 km-1 km 01 sr 01 220 3 t001cr timer stop counter clear km write to t01reg match detection write k write s write to t01reg write k write s t01+00reg sr sr-1 t01mod when the double buffer is disabled (t01mod=?0?) source clock counter timer start 1 0 km write to t00reg match detection write m write r counter clear inttc01 interrupt request 234 km-1 km 01 km 01 23 t01+00reg t001cr sr km double buffer sr match detection match detection counter clear 01 km-1 sr sr-1 t01mod when the double buffer is enabled (t01mod=?1?) reflected by writing to t01reg match detection
table 16-9 16-bit timer mode resolution and maximum time setting t01mod source clock [hz] resolution maximum time setting normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8s 488.2s 13.4s 32s 001 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 6.7s 16s 010 fcgck/2 8 fcgck/2 8 - 25.6s - 1.7s - 011 fcgck/2 6 fcgck/2 6 - 6.4s - 419.4ms - 100 fcgck/2 4 fcgck/2 4 - 1.6s - 104.9ms - 101 fcgck/2 2 fcgck/2 2 - 400ns - 26.2ms - 110 fcgck/2 fcgck/2 - 200ns - 13.1ms - 111 fcgck fcgck fs/2 2 100ns 122.1s 6.6ms 8s tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 262 2012/5/18 ra005
16.4.6 16-bit event counter mode in the 16-bit event counter mode, the up counter counts up at the falling edge of the input to the tc00 pin. tc00 and tc01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit timer. 16.4.6.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit timer mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit timer mode. the 16-bit timer mode is activated by setting t01mod to "00" or "01" and t01mod to "1". set the count value to be used for the match detection as a 16-bit value at the timer registers t00reg and t01reg. set the lower 8 bits of the 16-bit value at t00reg and set the higher 8 bits at t01reg. (here- inafter, the 16-bit value specified by the combined setting of t01reg and t00reg is indicated as t01 +00reg.) the timer register settings are reflected on the double buffer or t01+00reg when a write instruc- tion is executed on t01reg. be sure to execute the write instructions on t00reg and t01reg in this or- der. (when data is written to the high-order register, the set values of the low-order and high-order regis- ters become effective at the same time.) set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod be- comes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) 16.4.6.2 operations setting t001cr to "1" allows the 16-bit up counter to increment at the falling edge of the tc00 pin. when a match between the up counter value and the t00+01reg set value is detected, an inttc01 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x0000". the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two machine cycles or more is required at both the "h" and "l" levels. 16.4.6.3 double buffer refer to 16.4.5.3. tmp89fw20a page 263 2012/5/18 ra005
(example) operate tc00 and tc01 in the 16-bit event counter mode and generate an interrupt each time the 384th fall- ing edge is detected at the tc00 pin ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xc4 ; selects the 16-bit event counter mode ld (t00reg),0x80 ; sets the timer register ld (t01reg),0x10 ; sets the timer register ld (t001cr),0x06 ; starts tc00 and tc001 (16-bit mode) figure 16-12 16-bit event counter mode timing chart tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 264 2012/5/18 ra005 tc00 pin input counter timer start when the double buffer is disabled (t01mod=?0?) 1 0 km write to t00reg match detection write m write s reflected by writing to t01reg reflected by writing to t01reg counter clear write to t01reg write k write r inttc00 interrupt request 23 4 km-1 km 01 rs 01 220 3 t01+00reg t001cr rs timer stop match detection counter clear counter clear rs-1 tc00 pin input counter timer start when the double buffer is enabled (t01mod=?1?) 1 0 km write to t00reg match detection write m write s reflected by writing to t01reg reflected by writing to t01reg counter clear write to t01reg write k write r inttc00 interrupt request 23 4 km-1 km 01 km 01 21 3 t01+00reg t001cr rs km double buffer rs m a t c h d e t e c t i o n counter clear counter clear km-1 rs 0 rs-1 m a t c h d e t e c t i o n reflected by an interrupt
16.4.7 12-bit pulse width modulation (pwm) output mode in the 12-bit pwm output mode, tc00 and tc01 are cascaded to output the pulse-width modulated pulses with a resolution of 8 bits. an additional pulse of 4 bits can be inserted, which enables pwm output with a res- olution nearly equivalent to 12 bits. 16.4.7.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit timer mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit timer mode. the 12-bit pwm mode is selected by setting t01mod to "10". to use the internal clock as the source clock, set t01mod to "0" and select the clock at t01mod. to use an exter- nal clock as the source clock, set t01mod to "1". set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod be- comes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) set the count value to be used for the match detection and the additional pulse value as a 12-bit value at the timer registers t00pwm and t01pwm. set bits 11 to 8 of the 12-bit value at the lower 4 bits of t01pwm and set bits 7 to 0 at t00pwm. refer to the following table for the register configuration. here- inafter, the 12-bit value specified by the combined setting of t00pwm and t01pwm is indicated as t01 +00pwm. the timer register settings are reflected on the double buffer or t01+00pwm when a write in- struction is executed on t01pwm. be sure to execute the write instructions on t00pwm and t01pwm in this order. (when data is written to the high-order register, the set values of the low-order and high-or- der registers become effective at the same time.) timer register 00 t00pwm 7 6 5 4 3 2 1 0 (0x00028) bit symbol pwmdutyl pwmad3 pwmad2 pwmad1 pwmad0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 timer register 01 t01pwm 7 6 5 4 3 2 1 0 (0x00029) bit symbol pwmdutyh read/write r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 bits 7 to 4 of t01pwm are not used in the 12-bit pwm mode. however, data can be written to these bits of t01pwm and the written values are read out as they are when the bits are read. normally, set these bits to "0". pwmdutyh and pwmdutyl are 4-bit registers. they are combined to set an 8-bit value of duty pulse width (time before the first change in the output) for one cycle (256 counts of the source clock). here- inafter, an 8-bit value specified by the combined setting of pwmdutyh and pwmdutyl is indicated as pwmduty. pwmad3 to 0 are the additional pulse setting register. additional pulses can be inserted in specific cy- cles of the duty pulse by setting each bit to "1". the additional pulses are inserted in the positions listed tmp89fw20a page 265 2012/5/18 ra005
in table 16-10. pwmad 3 to 0 can be combined to specify the number of times of inserting the addition- al pulses in 16 cycles to any number from 1 to 16. examples of inserting additional pulses are shown in fig- ure 16-13. table 16-10 cycles in which additional pulses are inserted cycles in which additional pulses are inserted among cycles 1 to 16 pwmad0="1" 9 pwmad1="1" 5, 13 pwmad2="1" 3, 7, 11, 15 pwmad3="1" 2, 4, 6, 8, 10, 12, 14, 16 set the initial state of the pwm1 pin at t01mod. setting t01mod to "0" selects the "l" level as the initial state of the pwm1 pin. setting t01mod to "1" selects the "h" level as the initial state of the pwm1 pin. if the pwm1 pin is set as the function output pin in the port setting while the timer is stopped, the value of t01mod is output to the pwm1 pin. table 16-11 shows the list of output levels of the pwm1 pin. table 16-11 list of output levels of pwm1 pin tff1 pwm1pin output level before the start of operation (initial state) pwmduty matched (after the addi- tional pulse) overflow operation stop- ped (initial state) 0 l h l l 1 h l h h tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 266 2012/5/18 ra005
figure 16-13 examples of inserting additional pulses 16.4.7.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the lower 8 bits of the up counter value and the value set to pwmduty is detected, the output of the pwm1 pin is reversed. when t01mod is "0", the pwm1 pin changes from the "l" to "h" level. when t01mod is "1", the pwm1 pin changes from the "h" to "l" level. if any of pwmad3 to 0 is "1", an additional pulse that corresponds to 1 count of the source clock is in- serted in specific cycles of the duty pulse. in other words, the pwm1 pin output is reversed at the timing of pwmduty+1. when t00mod is "0", the period of the "l" level becomes longer than the val- ue set to pwmduty by 1 source clock. when t00mod is "1", the period of the "h" level be- comes longer than the value set to pwmduty by 1 source clock. this function allows 16 cycles of out- put pulses to be handled with a resolution nearly equivalent to 12 bits. no additional pulse is inserted when pwmad3 to 0 are all "0". subsequently, the up counter continues counting up. when the up counter value reaches 256, an over- flow occurs and the up counter is cleared to "0x00". at the same time, the output of the pwm1 pin is re- versed. when t01mod is "0", the pwm1 pin changes from the "h" to "l" level. when t01mod is "1", the pwm1 pin changes from the "l" to "h" level. at this time, an inttc00 in- terrupt request is generated (an inttc00 interrupt request is generated each time an overflow occurs.) an inttc01 interrupt request is generated at the 16 n-th overflow (n=1, 2, 3...). subsequently, the up counter continues counting up. tmp89fw20a page 267 2012/5/18 ra005 timer start additional pulse 1234567891011121314151617 pwm1 pin output (tff1=?1?) timer stop timer stop pwm1 pin output (tff1=?0?) inttc00 interrupt request inttc01 interrupt request cycle when pwmad1=?1? additional pulse timer start 1234567891011121314151617 pwm1 pin output (tff1=?1?) pwm1 pin output (tff1=?0?) inttc00 interrupt request inttc01 interrupt request cycle when pwmad0 = ?1? and pwmad2 = ?1? additional pulse additional pulse additional pulse additional pulse additional pulse
when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x00". the pwm1 pin returns to the level selected at t01mod. when an external source clock is selected, input the clock at the tc00 pin. the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two machine cycles or more is required at both the "h" and "l" levels. figure 16-14 pwm1 pin output 16.4.7.3 double buffer the double buffer can be used for t01+00pwm by setting t01mod. the double buffer is dis- abled by setting t01mod to "0" or enabled by setting t01mod to "1". ? when the double buffer is enabled when write instructions are executed on t00pwm and t01pwm in this order during the tim- er operation, the set value is first stored in the double buffer, and t01+00pwm is not updated immediately. t01+00pwm compares the previous set value with the up counter value. when the 16 n-th overflow occurs, an inttc01 interrupt request is generated and the double buf- fer set value is stored in t01+00pwm. subsequently, the match detection is executed using a new set value. when a read instruction is executed on t01+00pwm (t00reg), the value in the double buf- fer (the last set value) is read out, not the t01+00pwm value (the currently effective value). when write instructions are executed on t00pwm and t01pwm in this order while the tim- er is stopped, the set value is immediately stored in both the double buffer and t01+00pwm. ? when the double buffer is disabled when write instructions are executed on t00pwm and t01pwm in this order during the tim- er operation, the set value is immediately stored in t01+00pwm. subsequently, the match detec- tion is executed using a new set value. if the value set to t01+00pwm is smaller than the up counter value, the pwm1 pin is not reversed until the up counter overflows and a match detec- tion is executed using a new set value. if the value set to t01+00pwm is equal to the up coun- ter value, the match detection is executed immediately after data is written into t01+00pwm. therefore, the timing of changing the pwm1 pin may not be an integral multiple of the source clock. similarly, if t01+00pwm is set during the additional pulse output, the timing of changing the pwm1 pin may not be an integral multiple of the source clock. if these are prob- lems, enable the double buffer. when write instructions are executed on t00pwm and t01pwm in this order while the tim- er is stopped, the set value is immediately stored in t01+00pwm. tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 268 2012/5/18 ra005 pwmduty timer start additional pulse (1 source clock) (duty pulse width) 256 counts (cycle width) 256 counts (cycle width) pwm1 pin output (tff0=?1?) pwmduty (duty pulse width) pwm1 pin output (tff0=?0?)
(example) operate tc00 and tc01 in the 12-bit pwm mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 14.0625 s in 51.2s cycles (fcgck = 10 mhz) (actually, output a duty pulse of 225 s in total in 16 cycles (819.2 s)) set (p9fc).5 ; sets p9fc5 to "1" set (p9cr).5 ; sets p9cr5 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf2 ; selects the 12-bit pwm mode and fcgck/2 ld (t00pwm),0x65 ; sets the timer register (duty pulse) ; (14.0625s 16) / (2/fcgck) = 0x465 ld (t01pwm),0x04 ; sets the timer register (duty pulse) ld (t001cr),0x06 ; starts tc00 and tc01 figure 16-15 12-bit pwm mode timing chart tmp89fw20a page 269 2012/5/18 ra005 source clock counter timer start 1 0 km (0001) km km (duty pulse) 256 counts (cycle 1) 256 counts (cycle 2) 256 counts (cycle 9) 256 counts (cycle 16) (cycle 17) rs (0011) rs write to t00pwm double buffer match detection write m (0001) write s (0011) becomes the level selected at tff1 while the timer is stopped interrupt request interrupt request interrupt request write to t01pwm write k write r inttc00 interrupt request inttc01 interrupt request 1 km +1 km km +1 km km +1 km km +1 km 0 0001 0011 pwmduty pwmad3 to 0 t001cr 256 match detection 1 0 256 1 0 256 rs 1 0 256 match detection match detection counter clear overflow overflow overflow counter clear counter clear counter clear t01mod pwm1 pin output when the double buffer is enabled (t01mod=?1?) km (duty pulse) km (duty pulse) km+1 (duty pulse) rs (duty pulse) additional pulse interrupt request
table 16-12 resolutions and cycles in the 12-bit pwm mode t01mod source clock [hz] resolution 8-bit cycle (period 16) normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8s 488.2s 52.4ms (838.9ms) 125ms (2000ms) 001 fcgck/2 10 fs/2 3 fs/2 3 102.4s 244.1s 26.2ms (419.4ms) 62.5ms (1000ms) 010 fcgck/2 8 fcgck/2 8 - 25.6s - 6.6ms (104.9ms) - 011 fcgck/2 6 fcgck/2 6 - 6.4s - 1.6ms (26.2ms) - 100 fcgck/2 4 fcgck/2 4 - 1.6s - 409.6s (6.6ms) - 101 fcgck/2 2 fcgck/2 2 - 400ns - 102.4s (1.6ms) - 110 fcgck/2 fcgck/2 - 200ns - 51.2s (819.2s) - 111 fcgck fcgck fs/2 2 100ns 122.1s 25.6s (409.6s) 31.3ms (500ms) tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 270 2012/5/18 ra005
16.4.8 16-bit programmable pulse generate (ppg) output mode in the 16-bit ppg mode, tc00 and tc01 are cascaded to output the pulses that have a resolution of 16 bits and arbitrary pulse width and duty. two 16-bit registers, t01+00reg and t01+00pwm, are used to out- put the pulses. this enables output of longer pulses than an 8-bit timer. 16.4.8.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit mode. the 16-bit ppg mode is selected by setting t01mod to "11". to use the internal clock as the source clock, set t01mod to "0" and select the clock at t01mod. to use an exter- nal clock as the source clock, set t01mod to "1". set t01mod to "1" to use the double buffer. set the count value that corresponds to a cycle as a 16-bit value at the timer registers t01reg and t00reg. set the count value that corresponds to a duty pulse as a 16-bit value at t01pwm and t00pwm (hereinafter, the 16-bit value specified by the combined setting of t01reg and t00reg is indi- cated as t01+00reg, and the 16-bit value specified by the combined setting of t01pwm and t00pwm is indicated as t01+00pwm). the timer register settings are reflected on the double buffer or t01 +00pwm and t01+00reg when a write instruction is executed on t01pwm. be sure to execute the write instructions on t00reg, t01reg and t00pwm before executing a write instruction on t01pwm. (when data is written to t01pwm, the set values of the four timer registers become effective at the same time.) set the initial state of the ppg1 pin at t01mod. setting t01mod to "0" selects the "l" level as the initial state of the ppg1 pin. setting t01mod to "1" selects the "h" level as the initial state of the ppg1 pin. if the ppg1 pin is set as the function output pin in the port setting while the timer is stopped, the value of t01mod is output to the ppg1 pin. table 16-13 shows the list of out- put levels of the ppg1 pin. table 16-13 list of output levels of ppg1 pin tff1 ppg1 pin output level before the start of operation (initial state) t01+00pwm matched t01+00reg matched operation stop- ped (initial state) 0 l h l l 1 h l h h 16.4.8.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the up counter value and the value set to t01+00pwm is detected, the out- put of the ppg1 pin is reversed. when t01mod is "0", the ppg1 pin changes from the "l" to "h" level. when t01mod is "1", the ppg1 pin changes from the "h" to "l" level. at this time, an inttc00 interrupt request is generated. the up counter continues counting up. when a match between the up counter value and the value set to t01+00reg is detected, the output of the ppg1 pin is reversed again. when t01mod is "0", the ppg1 pin changes from the "h" to "l" level. when t01mod is "1", the ppg1 pin changes from the "l" to "h" level. at this time, an inttc01 interrupt request is generated and the up counter is cleared to "0x0000". tmp89fw20a page 271 2012/5/18 ra005
when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x0000". the ppg1 pin returns to the level selected at t01mod. when an external source clock is selected, input the clock at the tc00 pin. the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two machine cycles or more is required at both the "h" and "l" levels. 16.4.8.3 double buffer the double buffer can be used for t01+00pwm and t01+00reg by setting t01mod. the dou- ble buffer is enabled by setting t01mod to "0" or disabled by setting t01mod to "1". ? when the double buffer is enabled when a write instruction is executed on t01pwm after write instructions are executed on t00reg, t01reg and t00pwm during the timer operation, the set values are first stored in the double buffer, and t01+00pwm and t01+00reg are not updated immediately. t01 +00pwm and t01+00reg compare the previous set values with the up counter value. when a match between the up counter value and the t01+00reg set value is detected, an inttc01 interrupt request is generated and the double buffer set values are stored in t01+00pwm and t01+00reg. subsequently, the match detection is executed using new set values. when a write instruction is executed on t01pwm after write instructions are executed on t00reg, t01reg and t00pwm while the timer is stopped, the set values are immediately stor- ed in both the double buffer and t01+00pwm and t01+00reg. ? when the double buffer is disabled when a write instruction is executed on t01pwm after write instructions are executed on t00reg, t01reg and t00pwm during the timer operation, the set values are immediately stor- ed in t01+00pwm and t01+00reg. subsequently, the match detection is executed using new set values. if the value set to t01+00pwm or t01+00reg is smaller than the up counter value, the ppg1 pin is not reversed until the up counter overflows and a match detection is executed us- ing a new set value. if the value set to t01+00pwm or t01+00reg is equal to the up coun- ter value, the match detection is executed immediately after data is written into t01+00pwm and t01+00reg. therefore, the timing of changing the ppg1 pin may not be an integral mul- tiple of the source clock. if these are problems, enable the double buffer. when a write instruction is executed on t01pwm after write instructions are executed on t00reg, t01reg and t00pwm while the timer is stopped, the set values are immediately stor- ed in t01+00pwm and t01+00reg. when read instructions are executed on t01+00pwm and t01+00reg, the last value written into t01 +00reg is read out, regardless of the t00mod setting. tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 272 2012/5/18 ra005
(example) operate tc00 and tc01 in the 16-bit ppg mode with the operation clock of fcgck/2 and output the 68s du- ty pulse in 96s cycles (fcgck = 10 mhz) set (p9fc).5 ; sets p9fc5 to "1" set (p9cr).5 ; sets p9cr5 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf3 ; selects the 8-bit ppg mode and fcgck/2 ld (t00reg),0xe0 ; sets the timer register (cycle) ld (t01reg),0x01 ; sets the timer register (cycle) ; 96s / (2/fcgck) = 0x01e0 ld (t00pwm),0x54 ; sets the timer register (duty pulse) ld (t01pwm),0x01 ; sets the timer register (duty pulse) ; 68s / (2/fcgck) = 0x0154 ld (t001cr),0x06 ; starts tc00 and tc01 tmp89fw20a page 273 2012/5/18 ra005
figure 16-16 16-bit ppg output mode timing chart tmp89fw20a 16. 8-bit timer counter (tc0) 16.4 functions page 274 2012/5/18 ra005 source clock counter timer start 1 0 gh gh gh (duty pulse) ab (cycle 1) cd (cycle 1) cd (cycle 1) ef (cycle 1) km qr km qr write to t00pwm double buffer match detection write h write m write r becomes the level selected at tff1 while the timer is stopped returns to the level selected at tff1 write to t01pwm write g write k write q inttc00 interrupt request inttc00 interrupt request 1 gh +1 km +1 gh 0 t01+00pwm t001cr ab cd ef write to t01reg double buffer write a write c write e write to t00reg write b write d write f ab timer stop match detection km km +1 km qr +1 qr 1 0 cd 1 0 cd 1 00 ef match detection counter clear counter clear counter clear counter clear t01mod ppg1 pin output when the double buffer is enabled (t01mod=?1?) km (duty pulse) km (duty pulse) qr (duty pulse) ab cd ef t01+00reg match detection match detection match detection match detection match detection
17. real time clock (rtc) the real time clock is a function that generates interrupt requests at certain intervals using the low-frequency clock. the number of interrupts is counted by the software to realize the clock function. the real time clock can be used only in the operation modes where the low-frequency clock oscillates, except for sleep0. 17.1 configuration figure 17-1 real time clock 17.2 control the real time clock is controlled by following resisters. low power consumption register 2 poffcr2 7 6 5 4 3 2 1 0 (0x00f76) bit symbol lcden - rtcen - - - sio1en sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 lcden lcd control 0 1 disable enable rtcen rtc control 0 1 disable enable sio1en sio1 control 0 1 disable enable sio0en sio0 control 0 1 disable enable tmp89fw20a page 275 2012/5/18 ra000 rtcsel rtcrun intrtc interrupt request fs (32.768 khz) rtccr selector binary counter 2 15 /fs 2 14 /fs 2 13 /fs 2 12 /fs 2 11 /fs 2 10 /fs 2 9 /fs 2 8 /fs
real time clock control register rtccr (0x00fc8) 7 6 5 4 3 2 1 0 bit symbol - - - - rtcsel rtcrun read/write r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 rtcsel selects the interrupt generation interval 000 : 2 15 /fs (1.000 [s] @fs=32.768khz) 001 : 2 14 /fs (0.500 [s] @fs=32.768khz) 010 : 2 13 /fs (0.250 [s] @fs=32.768khz) 011 : 2 12 /fs (125.0 [ms] @fs=32.768khz) 100 : 2 11 /fs (62.50 [ms] @fs=32.768khz) 101 : 2 10 /fs (31.25 [ms] @fs=32.768khz) 110 : 2 9 /fs (15.62 [ms] @fs=32.768khz) 111 : 2 8 /fs (7.81 [ms] @fs=32.768khz) rtcrun enables/disables the real time clock opera- tion 0 : disable 1 : enable note 1: fs: low-frequency clock [hz] note 2: rtccr can be rewritten only when rtccr is "0". if data is written into rtccr when rtccr is "1", the existing data remains effective. rtccr can be rewritten at the same time as enabling the real time clock, but it cannot be rewritten at the same time as disabling the real time clock. note 3: if the real time clock is enabled and when 1) syscr2 is cleared to "0" to stop the low-frequency clock oscillation circuit or 2) the operation is changed to the stop mode or the sleep0 mode, the data in rtccr is maintained and rtccr is cleared to "0". 17.3 function 17.3.1 low power consumption function real time clock has the low power consumption registers (poffcr2) that save power when the real time clock is not being used. setting poffcr2 to "0" disables the basic clock supply to real time clock to save power. note that this renders the real time clock unusable. setting poffcr2 to "1" enables the basic clock sup- ply to real time clock and allows the real time clock to operate. after reset, poffcr2 are initialized to "0", and this renders the real time clock unusable. when using the real time clock for the first time, be sure to set poffcr2 to "1" in the initial set- ting of the program (before the real time clock control registers are operated). do not change poffcr2 to "0" during the real time clock operation. otherwise real time clock may operate unexpectedly. 17.3.2 enabling/disabling the real time clock operation setting rtccr to "1" enables the real time clock operation. setting rtccr to "0" disables the real time clock operation. rtccr is cleared to "0" just after reset release. 17.3.3 selecting the interrupt generation interval the interrupt generation interval can be selected at rtccr. tmp89fw20a 17. real time clock (rtc) 17.3 function page 276 2012/5/18 ra000
rtccr can be rewritten only when rtccr is "0". if data is written into rtccr when rtccr is "1", the existing data remains effective. rtccr can be rewritten at the same time as enabling the real time clock operation, but it can- not be rewritten at the same time as disabling the real time clock operation. 17.4 real time clock operation 17.4.1 enabling the real time clock operation set the interrupt generation interval to rtccr, and at the same time, set rtccr to "1". when rtccr is set to "1", the binary counter for the real time clock starts counting of the low-frequency clock. when the interrupt generation interval selected at rtccr is reached, a real time clock inter- rupt request (intrtc) is generated and the counter continues counting. 17.4.2 disabling the real time clock operation clear rtccr to "0". when rtccr is cleared to "0", the binary counter for the real time clock is cleared to "0" and stops counting of the low-frequency clock. tmp89fw20a page 277 2012/5/18 ra000
tmp89fw20a 17. real time clock (rtc) 17.4 real time clock operation page 278 2012/5/18 ra000
18. asynchronous serial interface (uart) the tmp89fw20a contains 3 channels of asynchronous serial interfaces (uart). this chapter describes asynchronous serial interface 0 (uart0). for uart1 and uart2, replace the sfr ad- dresses and pin names as shown in table 18-1 and table 18-2. table 18-1 sfr address assignment uartxcr1 (address) uartxcr2 (address) uartxdr (address) uartxsr (address) rdxbuf (address) tdxbuf (address) uart0 uart0cr1 (0x0001a) uart0cr2 (0x0001b) uart0dr (0x0001c) uart0sr (0x0001d) rd0buf (0x0001e) td0buf (0x0001e) uart1 uart1cr1 (0x00f54) uart1cr2 (0x00f55) uart1dr (0x00f56) uart1sr (0x00f57) rd1buf (0x00f58) td1buf (0x00f58) uart2 uart2cr1 (0x00f5a) uart2cr2 (0x00f5b) uart2dr (0x00f5c) uart2sr (0x00f5d) rd2buf (0x00f5e) td2buf (0x00f5e) table 18-2 pin names serial data input pin serial data output pin uart0 rxd0 pin txd0 pin uart1 rxd1 pin txd1 pin uart2 rxd2 pin txd2 pin tmp89fw20a page 279 2012/5/18 ra001
18.1 configuration figure 18-1 asynchronous serial interface (uart) tmp89fw20a 18. asynchronous serial interface (uart) 18.1 configuration page 280 2012/5/18 ra001 8-bit counter 8-bit counter y a b c s s a by fcgck or fs match detection en en match detection comparator comparator start bit detection transmission start stop bit parity bit fcgck/2 6 fcgck/2 7 fcgck/2 8 ppga0 output (tca0 output) baud rate generator transmit rt clock receive rt clock 2 4 2 2 2 noise rejection circuit shift register shift register irda control s a by counter counter transmit control circuit receive control circuit selector frequency divider uart0cr1 uart0 control register 1 inttxd0 interrupt request intrxd0 interrupt request uart0 transmit data buffer uart0 receive data buffer rxd0 txd0 uart0cr1 rd0buf uart0cr2 uart0sr uart0dr uart0 baud rate register uart0 status register uart0 control register 2
18.2 control uart0 is controlled by the low power consumption registers (poffcr1), uart0 control registers 1 and 2 (uart0cr1 and uart0cr2) and the uart0 baud rate register (uart0dr). the operating status can be moni- tored using the uart status register (uart0sr). low power consumption register 1 poffcr1 7 6 5 4 3 2 1 0 (0x00f75) bit symbol - - - sbi0en - uart2en uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 sbi0en i2c0 control 0 1 disable enable uart2en uart2 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable tmp89fw20a page 281 2012/5/18 ra001
uart0 control register 1 uart0cr1 7 6 5 4 3 2 1 0 (0x0001a) bit symbol txe rxe stopbt even pe irdasel brg - read/write r/w r/w r/w r/w r/w r/w r/w r after reset 0 0 0 0 0 0 0 0 txe transmit operation 0: 1: disable enable rxe receive operation 0: 1: disable enable stopbt transmit stop bit length 0: 1: 1 bit 2 bits even parity selection 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity added irdasel txd pin output selection 0: 1: uart output irda output brg transfer base clock selection when syscr2 is "0" when syscr2 is "1" 0: fcgck fs 1: tca0 output note 1: fcgck, gear clock; fs, low-frequency clock note 2: if the txe or rxe bit is set to "0" during the transmission or receiving of data, the operation is not disabled until the da- ta transfer is completed. at this time, the data stored in the transmit data buffer is discarded. note 3: even, pe and brg settings are common to transmission and receiving. note 4: set rxe and txe to "0" before changing brg. note 5: when brg is set to the tca0 output, the rt clock becomes asynchronous and the start bit of the transmitted/re- ceived data may get shorter by a maximum of (uart0dr+1)/(transfer base clock frequency)[s]. if the pin is not used for the tca0 output, control the tca0 output by using the port function control register. note 6: to prevent stopbt, even, pe, irdasel and brg from being changed accidentally during the uart communica- tion, the register cannot be rewritten during the uart operation. for details, refer to "18.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed ". note 7: when the stop, idle0 or sleep0 mode is activated, txe and rxe are cleared to "0" and the uart stops. other bits keep their values. tmp89fw20a 18. asynchronous serial interface (uart) 18.2 control page 282 2012/5/18 ra001
uart0 control register 2 uart0cr2 7 6 5 4 3 2 1 0 (0x0001b) bit symbol - - rtsel rxdnc stopbr read/write r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 rtsel selects the number of rt clocks odd-numbered bits of transfer frame even-numbered bits of transfer frame 000: 16 clocks 16 clocks 001: 16 clocks 17 clocks 010: 15 clocks 15 clocks 011: 15 clocks 16 clocks 100: 17 clocks 17 clocks 101: reserved 11*: reserved rxdnc selects the rxd input noise rejec- tion time (time of pulses to be removed as noise) 00: 01: 10: 11: no noise rejection 1 x (uart0dr+1)/(transfer base clock frequency) [s] 2 x (uart0dr+1)/(transfer base clock frequency) [s] 4 x (uart0dr+1)/(transfer base clock frequency) [s] stopbr receive stop bit length 0: 1: 1 bit 2 bits note 1: when a read instruction is executed on uart0cr2, bits 7 and 6 are read as "0". note 2: rtsel can be set to two kinds of rt clocks for the even- and odd-numbered bits of the transfer frame. for details, re- fer to "18.8.1 transfer baud rate calculation method". note 3: for details of the rxdnc noise rejection time, refer to "18.10 received data noise rejection". note 4: when the stop, idle0 or sleep0 mode is activated, the uart stops automatically but each bit value of uart0cr2 remains unchanged. note 5: when stopbr is set to 2 bits, the first bit of the stop bits (during data receiving) is not checked for a framing error. note 6: to prevent rtsel, rxdnc and stopbr from being changed accidentally during the uart communication, the reg- ister cannot be rewritten during the uart operation. for details, refer to "18.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed ". uart0 baud rate register uart0dr 7 6 5 4 3 2 1 0 (0x0001c) bit symbol uart0dr7 uart0dr6 uart0dr5 uart0dr4 uart0dr3 uart0dr2 uart0dr1 uart0dr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note 1: set uart0cr1 and uart0cr1 to "0" before changing uart0dr. for the set values, refer to "18.8 transfer baud rate". note 2: when uart0cr1 is set to the tca0 output, the value set to uart0dr has no meaning. note 3: when the stop, idle0 or sleep0 mode is activated, the uart stops automatically but each bit value of uart0dr remains unchanged. tmp89fw20a page 283 2012/5/18 ra001
uart0 status register uart0sr 7 6 5 4 3 2 1 0 (0x0001d) bit symbol perr ferr oerr - rbsy rbfl tbsy tbfl read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 perr parity error flag 0: 1: no parity error parity error ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrrun error overrun error rbsy receive busy flag 0: 1: before receiving or end of receiving on receiving rbfl receive buffer full flag 0: 1: receive buffer empty receive buffer full tbsy transmit busy flag 0: 1: before transmission or end of transmission on transmitting tbfl transmit buffer full flag 0: 1: transmit buffer empty transmit buffer full (transmit data writing is completed) note 1: tbfl is cleared to "0" automatically after an inttxd0 interrupt request is generated, and is set to "1" when data is set to td0buf. note 2: when a read instruction is executed on uart0sr, bit 4 is read as "0". note 3: when the stop, idle0 or sleep0 mode is activated, each bit of uart0sr is cleared to "0" and the uart stops. uart0 receive data buffer rd0buf 7 6 5 4 3 2 1 0 (0x0001e) bit symbol rd0dr7 rd0dr6 rd0dr5 rd0dr4 rd0dr3 rd0dr2 rd0dr1 rd0dr0 read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 note 1: when the stop, idle0 or sleep0 mode is activated, the rd0buf values become undefined. if received data is re- quired, read it before activating the mode. uart0 transmit data buffer td0buf 7 6 5 4 3 2 1 0 (0x0001e) bit symbol td0dr7 td0dr6 td0dr5 td0dr4 td0dr3 td0dr2 td0dr1 td0dr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 note 1: when the stop, idle0 or sleep0 mode is activated, the td0buf values become undefined. tmp89fw20a 18. asynchronous serial interface (uart) 18.2 control page 284 2012/5/18 ra001
18.3 low power consumption function uart0 has a low power consumption register (poffcr1) that saves power consumption when the uart func- tion is not used. setting poffcr1 to "0" disables the basic clock supply to uart0 to save power. note that this ren- ders the uart unusable. setting poffcr1 to "1" enables the basic clock supply to uart0 and ren- ders the uart usable. after reset, poffcr1 is initialized to "0", and this renders the uart unusable. when using the uart for the first time, be sure to set poffcr1 to "1" in the initial setting of the program (before the uart control register is operated). do not change poffcr1 to "0" during the uart operation, otherwise uart0 may operate unex- pectedly. tmp89fw20a page 285 2012/5/18 ra001
18.4 protection to prevent uart0cr1 and uart0cr2 registers from be- ing changed the tmp89fw20a has a function that protects the registers from being changed so that the uart communica- tion settings (for example, stop bit and parity) are not changed accidentally during the uart operation. specific bits of uart0cr1 and uart0cr2 can be changed only under the conditions shown in table 18-3. if a write instruction is executed on the register when it is protected from being changed, the bits remain un- changed and keep their previous values. table 18-3 changing of uart0cr1 and uart0cr2 bit to be changed function conditions that allow the bit to be changed uart0cr1 uart0sr uart0cr1 uart0sr uart0cr1 transmit stop bit length both of these bits are "0" - - uart0cr1 parity selection all of these bits are "0" uart0cr1 parity addition uart0cr1 txd pin output selection both of these bits are "0" - - uart0cr1 transfer base clock selec- tion all of these bits are "0" uart0cr2 selection of number of rt clocks uart0cr2 selection of rxd pin input noise rejection time - - both of these bits are "0" uart0cr2 receive stop bit length tmp89fw20a 18. asynchronous serial interface (uart) 18.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed page 286 2012/5/18 ra001
18.5 activation of stop, idle0 or sleep0 mode 18.5.1 transition of register status when the stop, idle0 or sleep0 mode is activated, the uart stops automatically and each register be- comes the status as shown in table 18-4. for the registers that do not hold their values, make settings again as needed after the operation mode is recovered. table 18-4 transition of register status 7 6 5 4 3 2 1 0 uart0cr1 txe rxe stopbt even pe irdasel brg - cleared to 0 cleared to 0 hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the val- ue - uart0cr2 - - rtsel rxdnc stopbr - - hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the value uart0sr perr ferr oerr - rbsy rbfl tbsy tbfl cleared to 0 cleared to 0 cleared to 0 - cleared to 0 cleared to 0 cleared to 0 cleared to 0 uart0dr uart0dr7 uart0dr6 uart0dr5 uart0dr4 uart0dr3 uart0dr2 uart0dr1 uart0dr0 hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the val- ue hold the value rd0buf rd0dr7 rd0dr6 rd0dr5 rd0dr4 rd0dr3 rd0dr2 rd0dr1 rd0dr0 indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate td0buf td0dr7 td0dr6 td0dr5 td0dr4 td0dr3 td0dr2 td0dr1 td0dr0 indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate 18.5.2 transition of txd pin status when the idle0, sleep0 or stop mode is activated, the txd pin reverts to the status shown in table 18-5, whether data is transmitted/received or the operation is stopped. table 18-5 txd pin status when the stop, idle0 or sleep0 mode is activated uart0cr1 idle0 or sleep0 mode stop mode syscr1="1" syscr1="0" "0" h level h level hi-z "1" l level l level tmp89fw20a page 287 2012/5/18 ra001
18.6 transfer data format the uart transfers data composed of the following four elements. the data from the start bit to the stop bit is collectively defined as a "transfer frame". the start bit consists of 1 bit (l level) and the data consists of 8 bits. par- ity bits are determined by uart0cr1 that selects the presence or absence of parity and uart0cr1 that selects even- or odd-numbered parity. the bit length of the stop bit can be selected at uart0cr1. figure 18-2 shows the transfer data format. ? start bit (1 bit) ? data (8 bits) ? parity bit (selectable from even-numbered, odd-numbered or no parity) ? stop bit (selectable from 1 bit or 2 bits) figure 18-2 transfer data format 18.7 infrared data format transfer mode the txd0 pin can output data in the infrared data format (irda) by the setting of the irda output control regis- ter. setting uart0cr1 to "1" allows the txd0 pin to output data in the infrared data format. figure 18-3 example of infrared data format (comparison between normal output and ir- da output) tmp89fw20a 18. asynchronous serial interface (uart) 18.6 transfer data format page 288 2012/5/18 ra001 start 123456789101112 bit 0 stop 1 start bit 0 stop 1 stop 2 stop 1 stop 1 stop 2 start bit 0 bit 0 start bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity parity bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 1 0 1 0 0 1 1 stbt pe transfer frame uart output irda output start bit stop bit d0 d1 d2 d7 3/16 bit width
18.8 transfer baud rate the transfer baud rate of uart is set by uart0cr1, uart0dr and uart0cr2. the set- tings of uart0dr and uart0cr2 for general baud rates and operating frequencies are shown below. for independent calculation of transfer baud rates, refer to "18.8.1 transfer baud rate calculation method". table 18-6 set values of uart0dr and uart0cr2 for transfer baud rates (fcgck=10 to 1 mhz, uart0cr2=0y00) basic baud rate [baud] register operating frequency 10mhz 8mhz 7.3728 mhz 6.144 mhz 6mhz 5mhz 4.9152 mhz 4.19mhz 4mhz 2mhz 1mhz 128000 uart0dr 0x04 0x03 - 0x02 0x02 - - 0x01 0x01 0x00 - rtsel 0y011 0y011 - 0y000 0y011 - - 0y001 0y011 0y011 - error (+0.81%) (+0.81%) - (0%) (+0.81%) - - (-0.80%) (+0.81%) (+0.81%) - 115200 uart0dr 0x04 0x03 0x03 - 0x02 - - - 0x01 0x00 - rtsel 0y100 0y100 0y000 - 0y100 - - - 0y100 0y100 - error (+2.12%) (+2.12%) (0%) - (+2.12%) - - - (+2.12%) (+2.12%) - 76800 uart0dr 0x07 0x06 0x05 0x04 0x04 0x03 0x03 - 0x02 - - rtsel 0y001 0y010 0y000 0y000 0y011 0y001 0y000 - 0y100 - - error (-1.36%) (-0.79%) (0%) (0%) (+0.81%) (-1.36%) (0%) - (+2.12%) - - 62500 uart0dr 0x09 0x07 0x06 0x05 0x05 0x04 0x04 0x03 0x03 0x01 0x00 rtsel 0y000 0y000 0y100 0y001 0y000 0y000 0y011 0y100 0y000 0y000 0y000 error (0%) (0%) (-0.87%) (-0.70%) (0%) (0%) (+1.48%) (-1.41%) (0%) (0%) (0%) 57600 uart0dr 0x0a 0x08 0x07 0x06 0x06 0x04 0x04 - 0x03 0x01 0x00 rtsel 0y000 0y011 0y000 0y010 0y010 0y100 0y100 - 0y100 0y100 0y100 error (-1.36%) (-0.44%) (0%) (+1.59%) (-0.79%) (+2.12%) (+0.39%) - (+2.12%) (+2.12%) (+2.12%) 38400 uart0dr 0x10 0x0c 0x0b 0x09 0x09 0x07 0x07 0x06 0x06 0x02 - rtsel 0y011 0y000 0y000 0y000 0y011 0y001 0y000 0y011 0y010 0y100 - error (-1.17%) (+0.16%) (0%) (0%) (+0.81%) (-1.36%) (0%) (+0.57%) (-0.79%) (+2.12%) - 19200 uart0dr 0x22 0x19 0x17 0x13 0x12 0x10 0x0f 0x0d 0x0c 0x06 0x02 rtsel 0y010 0y000 0y000 0y000 0y001 0y011 0y000 0y011 0y000 0y010 0y100 error (-0.79%) (+0.16%) (0%) (0%) (-0.32%) (-1.17%) (0%) (+0.57%) (+0.16%) (-0.79%) (+2.12%) 9600 uart0dr 0x40 0x30 0x2f 0x27 0x26 0x22 0x1f 0x1c 0x19 0x0c 0x06 rtsel 0y000 0y100 0y000 0y000 0y000 0y010 0y000 0y010 0y000 0y000 0y010 error (+0.16%) (+0.04%) (0%) (0%) (+0.16%) (-0.79%) (0%) (+0.34%) (+0.16%) (+0.16%) (-0.79%) 4800 uart0dr 0x8a 0x64 0x5f 0x4f 0x4d 0x40 0x3f 0x34 0x30 0x19 0x0c rtsel 0y010 0y001 0y000 0y000 0y000 0y000 0y000 0y001 0y100 0y000 0y000 error (-0.08%) (+0.01%) (0%) (0%) (+0.16%) (+0.16%) (0%) (-0.18%) (+0.04%) (+0.16%) (+0.16%) 2400 uart0dr 0xf4 0xc9 0xbf 0x9f 0x92 0x8a 0x7f 0x6c 0x64 0x30 0x19 rtsel 0y100 0y001 0y000 0y000 0y100 0y010 0y000 0y000 0y001 0y100 0y000 error (+0.04%) (+0.01%) (0%) (0%) (+0.04%) (-0.08%) (0%) (+0.11%) (+0.01%) (+0.04%) (+0.16%) 1200 uart0dr - - - - - 0xf4 0xff 0xe8 0xc9 0x64 0x30 rtsel - - - - - 0y100 0y000 0y010 0y001 0y001 0y100 error - - - - - (+0.04%) (+0%) (-0.10%) (+0.01%) (+0.01%) (+0.04%) tmp89fw20a page 289 2012/5/18 ra001
table 18-7 set values of uart0dr and uart0cr2 for transfer baud rates (fs=32.768 khz, uart0cr2=0y00) basic baud rate [baud] register operating frequency 32.768 khz 300 uart0dr 0x06 rtsel 0y011 error (+0.67%) 150 uart0dr 0x0d rtsel 0y011 error (+0.67%) 134 uart0dr 0x0e rtsel 0y001 error (-1.20%) 110 uart0dr 0x11 rtsel 0y001 error (+0.30%) 75 uart0dr 0x1c rtsel 0y010 error (+0.44%) note 1: the overall error from the basic baud rate must be within 3%. even if the overall error is within 3%, the communica- tion may fail due to factors such as frequency errors in external controllers (for example, a personal computer) and os- cillators and the load capacity of the communication pin. 18.8.1 transfer baud rate calculation method 18.8.1.1 bit width adjustment using uart0cr2 the bit width of transmitted/received data can be finely adjusted by changing uart0cr2. the number of rt clocks per bit can be changed in a range of 15 to 17 clocks by changing uart0cr2. the rt clock is the transfer base clock, which is the pulses obtained by counting the clock selected at uart0cr1 the number of times of (uart0dr set value) + 1. especially, when uart0cr2 is set to "0y001" or "0y011", two types of rt clocks alternate at each bit, so that the pseudo baud rates of rt 15.5 clocks and rt 16.5 clocks can be generated. the number of rt clocks per bit of transfer frame is shown in figure 18-4. for example, when fcgck is 4 [mhz], uart0cr2 is set to "0y000" and uart0dr is set to "0x19", the baud rate calculated using the formula in figure 18-4 is expressed as: fcgck / (16 (uart0dr + 1) = 9615 [baud] these settings generate a baud rate close to 9600 [baud] (+0.16%). tmp89fw20a 18. asynchronous serial interface (uart) 18.8 transfer baud rate page 290 2012/5/18 ra001
figure 18-4 fine adjustment of baud rate clock using uart0cr2 18.8.1.2 calculation of set values of uart0cr2 and uart0dr the set value of uart0dr for an operating frequency and baud rate can be calculated using the calcu- lation formula shown in figure 18-5. for example, to generate a basic baud rate of 38400 [baud] with fcgck=4 [mhz], calculate the set value of uart0dr for each setting of uart0cr2 and com- pensate the calculated value to a positive number to obtain the generated baud rate as shown in figure 18-6. basically, select the set value of uart0cr2 that has the smallest baud rate error from among the generated baud rates. in figure 18-6, the setting of uart0cr2="0y010" has the smallest error among the calculated baud rates, and thus the generated baud rate is 38095 [baud] (?0.79%) against the basic baud rate of 38400 [baud]. note:the error from the basic baud rate should be accurate to within 3%. even if the error is within 3%, the communication may fail due to factors such as frequency errors of external controllers (for example, a personal computer) and oscillators and the load capacity of the communication pin. figure 18-5 uart0dr calculation method (when brg is set to fcgck) tmp89fw20a page 291 2012/5/18 ra001 start 123456789101112 bit 0 stop 1 start bit 0 stop 1 stop 2 stop 1 stop 1 stop 2 start bit 0 bit 0 start bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity parity bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 1 0 1 0 0 1 1 stbt pe 000 001 010 011 100 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 fcgck [baud] 16 (uartdr+1) generated baud rate *when brg is set to fcgck 17 15 16 17 rtsel transfer frame fcgck [baud] 16.5 (uartdr+1) fcgck [baud] 15 (uartdr+1) fcgck [baud] 15.5 (uartdr+1) fcgck [baud] 17 (uartdr+1) number of rt clocks 000 fcgck [hz] 1 1 1 1 1 uartdr = 16 a [baud] uartdr set value rtsel 001 fcgck [hz] uartdr = 16.5 a [baud] 010 fcgck [hz] uartdr = 15 a [baud] 011 fcgck [hz] uartdr = 15.5 a [baud] 100 fcgck [hz] uartdr = 17 a [baud]
figure 18-6 example of uart0dr calculation tmp89fw20a 18. asynchronous serial interface (uart) 18.8 transfer baud rate page 292 2012/5/18 ra001 000 4000000 [hz] 4000000 [hz] 4000000 [hz] 4000000 [hz] 4000000 [hz] 1 6 35714 [baud] ( 6.99%) 40404 [baud] ( 5.22%) 38095 [baud] ( 0.79%) 36866 [baud] ( 3.99%) 39216 [baud] ( 2.12%) 1 6 1 6 1 5 1 5 uartdr = 16 38400 [baud] uartdr calculation generated baud rate rtsel 4000000 [hz] 16 (6 + 1) 4000000 [hz] 16.5 (5 + 1) 4000000 [hz] 15 (6 + 1) 4000000 [hz] 15.5 (6 + 1) 4000000 [hz] 17 (5 + 1) 001 uartdr = 16.5 38400 [baud] 010 uartdr = 15 38400 [baud] 011 uartdr = 15.5 38400 [baud] 100 uartdr = 17 38400 [baud]
18.9 data sampling method the uart receive control circuit starts rt clock counting when it detects a falling edge of the input pulses to the rxd0 pin. 15 to 17 rt clocks are counted per bit and each clock is expressed as rtn (n=16 to 0). in a bit that has 17 rt clocks, rt16 to rt0 are counted. in a bit that has 16 rt clocks, rt15 to rt0 are counted. in a bit that has 15 rt clocks, rt14 to rt0 are counted (decrement). during counting of rt8 to rt6, the uart re- ceive control circuit samples the input pulses to the rxd0 pin to make a majority decision. the same level detec- ted twice or more from among three samplings is processed as the data for the bit. the number of rt clocks can be changed in a range of 15 to 17 by setting uart0cr2. however, sam- pling is always executed in rt8 to rt6, even if the number of rt clocks is changed (figure 18-7). figure 18-7 data sampling in each case of uartcr2 tmp89fw20a page 293 2012/5/18 ra001 rt15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 bit 0 start bit bit 0 start bit (b) uartcr2 is ?001b? rt clock internal received data rt15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 bit 0 start bit bit 0 start bit (a) uartcr2 is ?000b? rt clock rxd0 pin rxd0 pin rxd0 pin rxd0 pin rxd0 pin internal received data rt16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bit 0 start bit bit 0 start bit (e) uartcr2 is ?100b? rt clock internal received data rt14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 bit 0 start bit bit 0 start bit (d) uartcr2 is ?011b? rt clock internal received data rt14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 bit 0 bit 1 bit 1 bit 1 bit 1 start bit bit 0 start bit (c) uartcr2 is ?010b? rt clock internal received data
if "1" is detected in sampling of the start bit, for example, due to the influence of noise, rt clock counting stops and the data receiving is suspended. subsequently, when a falling edge is detected in the input pulses to the rxd0 pin, rt clock counting restarts and the data receiving restarts with the start bit. figure 18-8 start bit sampling tmp89fw20a 18. asynchronous serial interface (uart) 18.9 data sampling method page 294 2012/5/18 ra001 rt15 14 13 12 11 10 9 8 7 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 bit 0 start bit start bit bit 0 rt clock rxd0 pin shift register noise bit 0 internal received data error because the start bit is 1 counting is suspended until the next falling edge is detected receiving continues because the start bit is 0 the received data is taken into the shift register a falling edge is detected a falling edge is detected
18.10 received data noise rejection when noise rejection is enabled at uart0cr2, the time of pulses to be regarded as signals is as shown in table 18-8. table 18-8 received data noise rejection time rxdnc noise rejection time [s] time of pulses to be regarded as signals 00 no noise rejection - 01 (uart0dr+1)/(transfer base clock frequency) 2 (uart0dr+1)/(transfer base clock frequency) 10 2 (uart0dr+1)/(transfer base clock frequency) 4 (uart0dr+1)/(transfer base clock frequency) 11 4 (uart0dr+1)/(transfer base clock frequency) 8 (uart0dr+1)/(transfer base clock frequency) note 1: the transfer base clock frequency is the clock frequency selected at uartcr1. figure 18-9 received data noise rejection tmp89fw20a page 295 2012/5/18 ra001 receiving continues because the start bit is 0 the received data is taken into the shift register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 bit 0 start bit start bit bit 0 rt clock internal received data shift register bit 0 rxd0 pin noise noise is removed a falling edge is detected when the noise rejection circuit is used
18.11 transmit/receive operation 18.11.1 data transmit operation set uart0cr1 to "1". check uart0sr = "0", and then write data into td0buf (trans- mit data buffer). writing data into td0buf sets uart0sr to "1", transfers the data to the transmit shift register, and outputs the data sequentially from the txd0 pin. the data output includes a start bit, stop bits whose number is specified in uart0cr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uart0cr1, uart0cr2 and uart0dr. when data trans- mission starts, the transmit buffer full flag uart0sr is cleared to "0" and an inttxd0 interrupt re- quest is generated. note 1: after data is written into td0buf, if new data is written into td0buf before the previous data is transfer- red to the shift register, the new data is written over the previous data and is transferred to the shift register. note 2: under the conditions shown in table 18-9, the txd0 pin output is fixed at the l or h level according to the setting of uart0cr1. table 18-9 txd0 pin output condition txd0 pin output irdasel="0" irdasel="1" when uart0cr1 is "0" h level l level from when "1" is written to uart0cr1 to when the trans- mitted data is written to td0buf when the stop, idle0 or sleep0 mode is active 18.11.2 data receive operation set uart0cr1 to "1". when data is received via the rxd0 pin, the received data is transferred to rd0buf (receive data buffer). at this time, the transmitted data includes a start bit, stop bit(s) and a pari- ty bit if parity addition is specified. when the stop bit(s) are received, data only is extracted and transferred to rd0buf (receive data buffer). then the receive buffer full flag uart0sr is set and an intrxd0 interrupt request is generated. set the data transfer baud rate using uart0cr1, uart0cr2 and uart0dr. if an overrun error occurs when data is received, the data is not transferred to rd0buf (receive data buf- fer) but discarded; data in the rd0buf is not affected. tmp89fw20a 18. asynchronous serial interface (uart) 18.11 transmit/receive operation page 296 2012/5/18 ra001
18.12 status flag 18.12.1 parity error when the parity determined using the receive data bits differs from the received parity bit, the parity error flag uart0sr is set to "1". at this time, an intrxd0 interrupt request is generated. if uart0sr is "1" when uart0sr is read, uart0sr will be cleared to "0" when rd0buf is read subsequently. (the rd0buf read value becomes undefined.) if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 18-10 occurrence of parity error tmp89fw20a page 297 2012/5/18 ra001 rxd0 pin input indeterminate data reading perr is cleared to ?0? when rd0buf is read after reading perr=?1?. intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop reading of uart0sr reading of rd0buf rd0buf rxd0 pin input indeterminate not cleared data reading perr is cleared to ?0? when rd0buf is read after reading perr=?1?. intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop reading of uart0sr reading of rd0buf rd0buf data reading
18.12.2 framing error if the internal and external baud rates differ or "0" is sampled as the stop bit of received data due to the in- fluence of noise on the rxd0 pin, the framing error flag uart0sr is set to "1". at this time, an intrxd0 interrupt request is generated. if uart0sr is "1" when uart0sr is read, uart0sr will be cleared to "0" when rd0buf is read subsequently. if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 18-11 occurrence of framing error tmp89fw20a 18. asynchronous serial interface (uart) 18.12 status flag page 298 2012/5/18 ra001 rxd0 pin input a falling edge is detected ferr is generated if ?0? is received in the sampling of the stop bit. ferr is cleared to ?0? when rd0buf is read after reading ferr=?1?. ferr is cleared to ?0? when rd0buf is read after reading ferr=?1?. sampling intrxd0 interrupt request uart0sr when the external baud rate is slower than the internally set baud rate when the external baud rate is faster than the internally set baud rate start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop reading of uart0sr reading of rd0buf rxd0 pin input a falling edge is detected a falling edge is detected ferr is generated if ?0? is received in the sampling of the stop bit. sampling intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 reading of uart0sr reading of rd0buf rd0buf indeterminate data reading rd0buf indeterminate data reading
18.12.3 overrun error if receiving of all data bits is completed before the previous received data is read from rd0buf, the over- run error flag uart0sr is set to "1" and an intrxd0 interrupt request is generated. the data re- ceived at the occurrence of the overrun error is discarded and the previous received data is maintained. subse- quently, if data is received while uart0sr is still "1", no intrxd0 interrupt request is gener- ated, and the received data is discarded. (figure 18-12) note that parity or framing errors in the discarded received data cannot be detected. (these error flags are not set.) that is to say, if these errors are detected together with an overrun error during the reading of uart0sr, they have occurred in the previous received data (the data stored in rd0buf). (figure 18-13) if uart0sr is "1" when uart0sr is read, uart0sr will be cleared to "0" when rd0buf is read subsequently. (figure 18-14) if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. (figure 18-14) figure 18-12 generation of intrxd0 interrupt request tmp89fw20a page 299 2012/5/18 ra001 rxd0 pin input data a data a an interrupt request is generated. the flag is set. an interrupt request is generated. no interrupt request is generated. data b intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop rd0buf start bit0 bit1 bit7 stop data c the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained.
figure 18-13 framing/parity error flags when an overrun error occurs tmp89fw20a 18. asynchronous serial interface (uart) 18.12 status flag page 300 2012/5/18 ra001 rxd0 pin input data a data a a parity error occurs. an interrupt request is generated. the error flag is not set together with an overrun error. an interrupt request is generated. the flag is set. no interrupt request is generated. data b intrxd0 interrupt request when a parity error occurs in the first received data and a framing error occurs in the second data when a parity error occurs in the second received data uart0sr uart0sr start bit0 parity stop start bit0 parity stop rd0buf uart0sr uart0sr start bit0 parity stop start bit0 parity stop data c data d the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained. the contents of data d are discarded and those of data a are maintained. the parity is ok. the parity is ok. the flag is not set even if a framing error occurs. rxd0 pin input data a data a an interrupt request is generated. an interrupt request is generated. no interrupt request is generated. data b intrxd0 interrupt request uart0sr uart0sr start bit0 parity stop start bit0 parity stop rd0buf uart0sr start bit0 parity stop start bit0 parity stop data c data d the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained. the contents of data d are discarded and those of data a are maintained. a parity error occurs.
figure 18-14 clearance of overrun error flag tmp89fw20a page 301 2012/5/18 ra001 rxd0 pin input data a data a reading of data a the contents of data b are discarded and those of data a are maintained. data b oerr is cleared to ?0? when rd0buf is read after reading oerr=?1?. rbfl is cleared to ?0? when rd0buf is read after reading rbfl=?1?. intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf rxd0 pin input data a data a reading of data a the contents of data b are discarded and those of data a are maintained. data b oerr is cleared to ?0? when rd0buf is read after reading oerr=?1?. rbfl is cleared to ?0? when rd0buf is read after reading rbfl=?1?. intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf reading of data a
18.12.4 receive data buffer full loading the received data in rd0buf sets uart0sr to "1". if uart0sr is "1" when uart0sr is read, uart0sr will be cleared to "0" when rd0buf is read subsequently. if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 18-15 occurrence of receive data buffer full tmp89fw20a 18. asynchronous serial interface (uart) 18.12 status flag page 302 2012/5/18 ra001 rxd0 pin input data a data a reading of data a data b reading of data b data b rbfl is cleared to ?0? when rd0buf is read after reading rbfl=?1?. intrxd0 interrupt request uart0sr start bit1 bit0 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf
18.12.5 transmit busy flag if transmission is completed with no waiting data in td0buf (when uart0sr="0"), uart0sr is cleared to "0". when transmission is restarted after data is written into td0buf, uart0sr is set to "1". at this time, an inttxd0 interrupt request is generated. figure 18-16 transmit busy flag and occurrence of transmit buffer full 18.12.6 transmit buffer full when td0buf has no data, or when data in td0buf is transferred to the transmit shift register and trans- mission is started, uart0sr is cleared to "0". at this time, an inttxd0 interrupt request is gener- ated. writing data into td0buf sets uart0sr to "1". figure 18-17 occurrence of transmit buffer full tmp89fw20a page 303 2012/5/18 ra001 txd0 pin input inttxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit6 bit7 stop writing of td0buf uart0sr uart0cr1 data a data b writing of data a writing of data b txd0 pin input inttxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit6 bit7 stop writing of td0buf uart0sr uart0cr1 data a data b writing of data a writing of data b
18.13 receiving process figure 18-18 shows an example of the receiving process. details of flag judgments in the processing are shown in table 18-10 and table 18-11. if any framing error or parity error is detected, the received data has erroneous value(s). execute the error han- dling, for example, by discarding the received data read from rd0buf and receiving the data again. if any overrun error is detected, the receiving of one or more pieces of data is unfinished. it is impossible to de- termine the number of pieces of data that could not be received. execute the error handling, for example, by receiv- ing data again from the beginning of the transfer. basically, an overrun error occurs when the internal software pro- cessing cannot follow the data transfer speed. it is recommended to slow the transfer baud rate or modify the soft- ware to execute flow control. figure 18-18 example of receiving process note 1: if multiple interrupts are used in the intrxd0 interrupt subroutine, the interrupt should be enabled after reading uart0sr and rd0buf. tmp89fw20a 18. asynchronous serial interface (uart) 18.13 receiving process page 304 2012/5/18 ra001 receiving process end when no receive interrupt is used when a receive interrupt is used read uart0sr read rd0buf error handling error handling error handling error handling data processing (received data is valid) uart0sr 1 1 1 0 0 0 1 0 uart0sr parity error framing error overrun error parity error framing error overrun error uart0sr uart0sr intrxd0 interrupt subroutine reti read uart0sr read rd0buf data processing (received data is valid) 1 1 0 0 1 0 uart0sr uart0sr uart0sr
table 18-10 flag judgments when no receive interrupt is used rbfl ferr/perr oerr state 0 - 0 data has not been received yet. 0 - 1 some pieces of data could not be received during the previ- ous data receiving process (receiving of next data is completed in the period from when uart0sr is read to when rd0buf is read in the pre- vious data receiving process.) 1 0 0 receiving has been completed properly. 1 0 1 receiving has been completed properly, but some pieces of data could not be received. 1 1 0 received data has erroneous value(s). 1 1 1 received data has erroneous value(s) and some pieces of data could not be received. table 18-11 flag judgments when a receive interrupt is used ferr/perr oerr state 0 0 receiving has been completed properly. 0 1 receiving has been completed properly, but some pieces of data could not be received. 1 0 received data has erroneous value(s). 1 1 received data has erroneous value(s) and some pieces of data could not be received. tmp89fw20a page 305 2012/5/18 ra001
18.14 ac properties 18.14.1 irda properties (v ss = 0 v, topr = ?40 to 85c) item condition min typ. max unit txd output pulse time (rt clock (3/16)) transfer baud rate = 2400 bps - 78.13 - s transfer baud rate = 9600 bps - 19.53 - transfer baud rate = 19200 bps - 9.77 - transfer baud rate = 38400 bps - 4.88 - transfer baud rate = 57600 bps - 3.26 - transfer baud rate = 115200 bps - 1.63 - tmp89fw20a 18. asynchronous serial interface (uart) 18.14 ac properties page 306 2012/5/18 ra001
19. synchronous serial interface (sio) the tmp89fw20a contains 2 channels of high-speed 8-bit serial interfaces of the clock synchronization type. this chapter describes serial interface 0. for serial interface 1, replace the sfr addresses and pin names as shown in table 19-1 and table 19-2. table 19-1 sfr address assignment sioxcr (address) sioxsr (address) sioxbuf (address) serial interface 0 sio0cr (0x0001f) sio0sr (0x00020) sio0buf (0x00021) serial interface 1 sio1cr (0x00f70) sio1sr (0x00f71) sio1buf (0x00f72) table 19-2 pin names serial clock input/output pin serial data input pin serial data output pin serial interface 0 sclk0 pin si0 pin so0 pin serial interface 1 sclk1 pin si1 pin so1 pin tmp89fw20a page 307 2012/5/18 ra001
19.1 configuration figure 19-1 serial interface note: the serial interface input/output pins are also used as the i/o ports. the i/o port register settings are re- quired to use these pins for a serial interface. for details, refer to the chapter of i/o ports. tmp89fw20a 19. synchronous serial interface (sio) 19.1 configuration page 308 2012/5/18 ra001 shift register on transmitter shift register on receiver control circuit shift clock internal clock port (note) port (note) msb/lsb selection port (note) internal bus internal bus sio0cr sio0sr sio0buf sio0buf intsio0 interrupt request so0 pin si0 pin sclk0 pin
19.2 control the synchronous serial interface sio0 is controlled by the low power consumption registers (poffcr2), the se- rial interface data buffer register (sio0buf), the serial interface control register (sio0cr) and the serial inter- face status register (sio0sr). low power consumption register 2 poffcr2 7 6 5 4 3 2 1 0 (0x00f76) bit symbol lcden - rtcen - - - sio1en sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 lcden lcd control 0 1 disable enable rtcen rtc control 0 1 disable enable sio1en sio1 control 0 1 disable enable sio0en sio0 control 0 1 disable enable serial interface buffer register sio0buf 7 6 5 4 3 2 1 0 (0x00021) bit symbol sio0buf read/write r after reset 0 0 0 0 0 0 0 0 serial interface buffer register sio0buf 7 6 5 4 3 2 1 0 (0x00021) bit symbol sio0buf read/write w after reset 1 1 1 1 1 1 1 1 note 1: sio0buf is the data buffer for both transmission and reception. the last received data is read each time sio0buf is read. if sio0buf has never received data, it is read as "0". when data is written into it, the data is treated as the trans- mit data. tmp89fw20a page 309 2012/5/18 ra001
serial interface control register sio0cr 7 6 5 4 3 2 1 0 (0x0001f) bit symbol sioedg siocks siodir sios siom read/write r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 sioedg transfer edge selection 0 1 0: receive data at a rising edge and transmit data at a falling edge 1: transmit data at a rising edge and receive data at a falling edge siocks serial clock selection [hz] normal1/2 or idle1/2 mode slow1/2 or sleep1 mode 000 fcgck/2 9 - 001 fcgck/2 6 - 010 fcgck/2 5 - 011 fcgck/2 4 - 100 fcgck/2 3 - 101 fcgck/2 2 - 110 fcgck/2 fs/2 3 111 external clock input siodir transfer format (msb/lsb) selec- tion 0 1 lsb first (transfer from bit 0) msb first (transfer from bit 7) sios transfer operation start/stop in- struction 0 1 0: operation stop (reserved stop) 1: operation start siom transfer mode selection and operation 00 operation stop (forced stop) 01 8-bit transmit mode 10 8-bit receive mode 11 8-bit transmit and receive mode note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: after the operation is started by writing "1" to sios, writing to sioedg, siocks and siodir is invalid until sio0sr becomes "0". (sioedg, siocks and siodir can be changed at the same time as changing sios from "0" to "1".) note 3: after the operation is started by writing "1" to sios, no values other than"00" can be written to siom until siof be- comes "0" (if a value from "01" to "11" is written to siom, it is ignored). the transfer mode cannot be changed during the operation. note 4: sios remains at "0", if "1" is written to sios when siom is "00" (operation stop). note 5: when sio is used in slow1/2 or sleep1 mode, be sure to set siocks to "110". if siocks is set to any other val- ue, sio will not operate. when sio is used in slow1/2 or sleep1 mode, execute communications with siocks="110" in advance or change siocks after sio is stopped. note 6: when stop, idle0 or sleep0 mode is activated, siom is automatically cleared to "00" and sio stops the opera- tion. at the same time, sios is cleared to "0". however, the values set for sioedg, siocks and siodir are main- tained. tmp89fw20a 19. synchronous serial interface (sio) 19.2 control page 310 2012/5/18 ra001
serial interface status register sio0sr 7 6 5 4 3 2 1 0 (0x00020) bit symbol siof sef oerr rend uerr tbfl - - read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 siof serial transfer operation status monitor 0 1 transfer not in progress transfer in progress sef shift operation status monitor 0 1 shift operation not in progress shift operation in progress oerr receive overrun error flag 0 1 no overrun error has occurred at least one overrun error has occurred rend receive completion flag 0 1 no data has been received since the last receive data was read out at least one data receive operation has been executed uerr transmit underrun error flag 0 1 no transmit underrun error has occurred at least one transmit underrun error has occurred tbfl transmit buffer full flag 0 1 the transmit buffer is empty the transmit buffer has the data that has not yet been transmitted note 1: the oerr and uerr flags are cleared by reading sio0sr. note 2: the rend flag is cleared by reading sio0buf. note 3: writing "00" to sio0cr clears all the bits of sio0sr to "0", whether the serial interface is operating or not. when stop, idle0 or sleep0 mode is activated, siom is automatically cleared to "00" and all the bits of sio0sr are cleared to "0". note 4: bit 1 to 0 of sio0sr are read "0". tmp89fw20a page 311 2012/5/18 ra001
19.3 low power consumption function serial interface 0 has the low power consumption registers (poffcr2) that save power when the serial inter- face is not being used. setting poffcr2 to "0" disables the basic clock supply to serial interface 0 to save power. note that this renders the serial interface unusable. setting poffcr2 to "1" enables the basic clock supply to serial interface 0 and allows the serial interface to operate. after reset, poffcr2 are initialized to "0", and this renders the serial interface unusable. when us- ing the serial interface for the first time, be sure to set poffcr2 to "1" in the initial setting of the pro- gram (before the serial interface control registers are operated). do not change poffcr2 to "0" during the serial interface operation. otherwise serial interface 0 may operate unexpectedly. tmp89fw20a 19. synchronous serial interface (sio) 19.3 low power consumption function page 312 2012/5/18 ra001
19.4 functions 19.4.1 transfer format the transfer format can be set to either msb or lsb first by using sio0cr. setting sio0cr to "0" selects lsb first as the transfer format. in this case, the serial data is transferred in sequence from the least significant bit. setting sio0cr to "1" selects msb first as the transfer format. in this case, the serial data is trans- ferred in sequence from the most significant bit. 19.4.2 serial clock the serial clock can be selected by using sio0cr. setting sio0cr to "000" to "110" selects the internal clock as the serial clock. in this case, the serial clock is output from the sclk0 pin. the serial data is transferred in synchronization with the edge of the sclk0 pin output. setting sio0cr to "111" selects an external clock as the serial clock. in this case, an external se- rial clock must be input to the sclk0 pin. the serial data is transferred in synchronization with the edge of the external clock. the serial data transfer edge can be selected for both the external and internal clocks. for details, refer to "19.4.3 transfer edge selection". table 19-3 transfer baud rate sio0cr serial clock [hz] fcgck=4mhz fcgck=8mhz fcgck=10mhz fs=32.768khz normal1/2 or idle1/2 mode slow1/2 or sleep1 mode 1-bit time (s) baud rate (bps) 1-bit time (s) baud rate (bps) 1-bit time (s) baud rate (bps) 1-bit time (s) baud rate (bps) 000 fcgck/2 9 - 128 7.813k 64 15.625k 51.2 19.531k - - 001 fcgck/2 6 - 16 62.5k 8 125k 6.4 156.25k - - 010 fcgck/2 5 - 8 125k 4 250k 3.2 312.5k - - 011 fcgck/2 4 - 4 250k 2 500k 1.6 625k - - 100 fcgck/2 3 - 2 500k 1 1m 0.8 1.25m - - 101 fcgck/2 2 - 1 1m 0.5 2m 0.4 2.5m - - 110 fcgck/2 fs/2 3 0.5 2m 0.25 4m 0.2 5m 244 4k 19.4.3 transfer edge selection the serial data transfer edge can be selected by using siocr. table 19-4 transfer edge selection sio0cr data transmission data reception 0 falling edge rising edge 1 rising edge falling edge when siocr is "0", the data is transmitted in synchronization with the falling edge of the clock and the data is received in synchronization with the rising edge of the clock. when siocr is "1", the data is transmitted in synchronization with the rising edge of the clock and the data is received in synchronization with the falling edge of the clock. tmp89fw20a page 313 2012/5/18 ra001
figure 19-2 transfer edge note: when an external clock input is used, 4/fcgck or longer is needed between the receive edge at the 8th bit and the transfer edge at the first bit of the next transfer. figure 19-3 interval time between bytes tmp89fw20a 19. synchronous serial interface (sio) 19.4 functions page 314 2012/5/18 ra001 r1 r0 r2 r3 r4 r5 r6 r7 t1 t0 t2 t3 t4 t5 t6 t7 slck0 pin so0 pin si0 pin when siocr=?0? r1 r0 r2 r3 r4 r5 r6 r7 t1 t0 t2 t3 t4 t5 t6 t7 sclk0 pin so0 pin si0 pin when siocr=?1? c7 c6 d0 d1 d2 a7 a6 b0 b1 b2 tbi leading edge at the 1st bit (transmit edge) trailing edge at the 8th bit (receive edge) sclk0 pin so0 pin si0 pin symbol name minimum time tbi interval time between bytes 4/fcgck
19.5 transfer modes 19.5.1 8-bit transmit mode the 8-bit transmit mode is selected by setting sio0cr to "01". 19.5.1.1 setting before starting the transmit operation, select the transfer edges at sio0cr, a transfer for- mat at sio0cr and a serial clock at sio0cr. to use the internal clock as the seri- al clock, select an appropriate serial clock at sio0cr. to use an external clock as the serial clock, set sio0cr to "111". the 8-bit transmit mode is selected by setting sio0cr to "01". the transmit operation is started by writing the first byte of transmit data to sio0buf and then setting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while the serial communication is stop- ped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to sio0cr is valid. 19.5.1.2 starting the transmit operation the transmit operation is started by writing data to sio0buf and then setting sio0cr to "1". the transmit data is transferred from sio0buf to the shift register, and then transmitted as the serial da- ta from the so0 pin according to the settings of sio0cr. the serial da- ta becomes undefined if the transmit operation is started without writing any transmit data to sio0buf. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. by setting sio0cr to "1", sio0sr are automatically set to "1" and an in- tsio0 interrupt request is generated. sio0sr is cleared to "0" when the 8th bit of the serial data is output. 19.5.1.3 transmit buffer and shift operation if data is written to sio0buf when the serial communication is in progress and the shift register is emp- ty, the written data is transferred to the shift register immediately. at this time, sio0sr remains at "0". if data is written to sio0buf when some data remains in the shift register, sio0sr is set to "1". if new data is written to sio0buf in this state, the contents of sio0buf are overwritten by the new value. make sure that sio0sr is "0" before writing data to sio0buf. 19.5.1.4 operation on completion of transmission the operation on completion of the data transmission varies depending on the operating clock and the state of sio0sr. tmp89fw20a page 315 2012/5/18 ra001
(1) when the internal clock is used and sio0sr is "0" when the data transmission is completed, the sclk0 pin becomes the initial state and the so0 pin becomes the "h" level. sio0sr remains at "0". when the internal clock is used, the seri- al clock and data output is stopped until the next transmit data is written into sio0buf (automatic wait). when the subsequent data is written into sio0buf, sio0sr is set to "1", the sclk0 pin out- puts the serial clock, and the transmit operation is restarted. an intsio0 interrupt request is gener- ated at the restart of the transmit operation. (2) when an external clock is used and sio0sr is "0" when the data transmission is completed, the so pin keeps last output value. when an external se- rial clock is input to the sclk0 pin after completion of the data transmission, an undefined value is transmitted and the transmit underrun error flag sio0sr is set to "1". if a transmit underrun error occurs, data must not be written to sio0buf during the transmission of an undefined value. (it is recommended to finish the transmit operation by setting sio0cr to "0" or force the transmit operation to stop by setting sio0cr to "00".) the transmit underrun error flag sio0sr is cleared by reading sio0sr. (3) when an internal or external clock is used and sio0sr is "1" when the data transmission is completed, sio0sr is cleared to "0". the data in sio0buf is transferred to the shift register and the transmission of subsequent data is started. at this time, sio0sr is set to "1" and an intsio0 interrupt request is generated. 19.5.1.5 stopping the transmit operation set sio0cr to "0" to stop the transmit operation. when sio0sr is "0", or when the shift operation is not in progress, the transmit operation is stopped immediately and an intsio0 interrupt request is generated. when sio0sr is "1", the transmit operation is stopped after all the data in the shift register is transmitted (reserved stop). at this time, an intsio0 interrupt request is generated again. when the transmit operation is completed, sio0sr are cleared to "0". other sio0sr registers keep their values. if the internal clock has been used, the so0 pin automatically returns to the "h" level. if an external clock has been used, the so0 pin keeps the last output value. to return the so0 pin to the "h" level, write "00" to sio0cr when the operation is stopped. the transmit operation can be forced to stop by setting sio0cr to "00" during the operation. by setting sio0cr to "00", sio0cr and sio0sr are cleared to "0" and the sio stops the operation, regardless of the sio0sr value. the so0 pin becomes the "h" level. if the internal clock is selected, the sclk0 pin returns to the initial level. tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 316 2012/5/18 ra001
figure 19-4 8-bit transmit mode (internal clock and reserved stop) figure 19-5 8-bit transmit mode (internal clock and forced stop) tmp89fw20a page 317 2012/5/18 ra001 so0 pin (output) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf ab c sio0cr sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c reserved stop start operation an interrupt is generated after transmission in case of reserved stop the level is held for the period of the internal clock(1/2) automatic wait 01 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 write to sio0buf sio0buf ab c d sio0cr sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c writing data d forced stop start operation 01 01 00 00 start operation bit0 bit1 bit2 bit3 bit4 bit5 data c forced stop forced stop has priority over reserved stop data is not held but becomes the h level clock output is stopped reserved stop
figure 19-6 8-bit transmit mode (external clock and reserved stop) figure 19-7 8-bit transmit mode (external clock and forced stop) tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 318 2012/5/18 ra001 so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf ab c sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c reserved stop start operation an interrupt is generated after transmission in case of reserved stop stopped while keeping the current level in the operation with an external clock returned to the h level by setting siocr1 to ?00? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 01 00 so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 write to sio0buf sio0buf abc d sio0cr sio0sr sio0sr sio0sr data a data c writing data a writing data b writing data c writing data d reserved stop start operation start operation bit0 bit1 bit2 bit3 bit4 bit5 data c forced stop forced stop has priority over reserved stop if two pieces of data are written, the latter data is effective when the operation is restarted after a forced stop, the last data written to the buffer is transmitted. data is not held but becomes the h level reserved stop sio0cr 01 01 00 00
figure 19-8 8-bit transmit mode (external clock and occurrence of transmit underrun error) tmp89fw20a page 319 2012/5/18 ra001 so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf abc read sio0sr sio0cr sio0sr sio0sr sio0sr sio0sr data a data a data b writing data a writing data b reading sio0sr writing data c reserved stop start operation stopped while keeping the current level in the operation with an external clock returned to the h level by setting siocr1 to ?00? transferred to the buffer immediately after writing bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data b data c transferred to the buffer immediately after writing sio0cr 01 00
19.5.2 8-bit receive mode the 8-bit receive mode is selected by setting sio0cr to "10". 19.5.2.1 setting as in the case of the transmit mode, before starting the receive operation, select the transfer edges at sio0cr, a transfer format at sio0cr and a serial clock at sio0cr. to use the internal clock as the serial clock, select an appropriate serial clock at sio0cr. to use an external clock as the serial clock, set sio0cr to "111". the 8-bit receive mode is selected by setting sio0cr to "10". reception is started by setting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while the serial communication is stop- ped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to sio0cr is valid. 19.5.2.2 starting the receive operation reception is started by setting sio0cr to "1". external serial data is taken into the shift regis- ter from the si0 pin according to the settings of sio0cr. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. by setting sio0cr to "1", sio0sr are automatically set to "1". 19.5.2.3 operation on completion of reception when the data reception is completed, the data is transferred from the shift register to sio0buf and an intsio0 interrupt request is generated. the receive completion flag sio0sr is set to "1". in the operation with the internal clock, the serial clock output is stopped until the receive data is read from sio0buf (automatic wait). at this time, sio0sr is set to "0". by reading the receive data from sio0buf, sio0sr is set to "1", the serial clock output is restarted and the receive operation continues. in the operation with an external clock, data can be continuously received without reading the received data from sio0buf. in this case, data must be read from sio0buf before the subsequent data has been fully received. if the subsequent data is received completely before reading data from sio0buf, the over- run error flag sio0sr is set to "1". when an overrun error has occurred, set sio0cr to "00" to abort the receive operation. the data received at the occurrence of an overrun error is discar- ded, and sio0buf holds the data value received before the occurrence of the overrun error. sio0sr is cleared to "0" by reading data from sio0buf. sio0sr is cleared by read- ing sio0sr. 19.5.2.4 stopping the receive operation set sio0cr to "0" to stop the receive operation. when sio0sr is "0", or when the shift operation is not in progress, the operation is stopped immediately. unlike the transmit mode, no in- tsio0 interrupt request is generated in this state. tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 320 2012/5/18 ra001
when sio0sr is "1", the operation is stopped after the 8-bit data has been completely received (reserved stop). at this time, an intsio0 interrupt request is generated. after the operation has stopped completely, sio0sr are cleared to "0". other sio0sr registers keep their values. the receive operation can be forced to stop by setting sio0cr to "00" during the operation. by setting sio0cr to "00", sio0cr and sio0sr are cleared to "0" and the sio stops the operation, regardless of the sio0sr value. if the internal clock is selected, the sclk0 pin re- turns to the initial level. figure 19-9 8-bit receive mode (internal clock and reserved stop) tmp89fw20a page 321 2012/5/18 ra001 si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf ac sio0cr sio0sr sio0sr sio0sr data a reading data a reading data c reserved stop automatic wait bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 10
figure 19-10 8-bit receive mode (internal clock and forced stop) figure 19-11 8-bit receive mode (external clock and reserved stop) tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 322 2012/5/18 ra001 si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf a sio0cr sio0cr sio0sr sio0sr sio0sr data a reading data a returned to the initial level reserved stop forced stop forced stop start operation start operation automatic wait 10 00 00 10 bit0 bit1 bit2 bit3 bit0 bit1 bit2 data b data c returned to the initial level si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf abc sio0cr sio0sr sio0sr sio0sr data a reading data a reading data b reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data b bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 10
figure 19-12 8-bit receive mode (external clock and forced stop) figure 19-13 8-bit receive mode (external clock and occurrence of overrun error) tmp89fw20a page 323 2012/5/18 ra001 si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf ac sio0cr sio0cr sio0sr sio0sr sio0sr data a reading data a reading data c forced stop start operation start operation 10 00 10 data b data b is discarded data c si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf a read sio0sr sio0cr sio0cr sio0sr sio0sr sio0sr sio0sr data a reading data a data b is discarded subsequent data is received completely before reading data a data c is discarded reading sui0sr forced stop start operation 10 00 data b data c
19.5.3 8-bit transmit/receive mode the 8-bit transmit/receive mode is selected by setting sio0cr to "11". 19.5.3.1 setting before starting the transmit/receive operation, select the transfer edges at sio0cr, a trans- fer format at sio0cr and a serial clock at sio0cr. to use the internal clock as the serial clock, select an appropriate serial clock at sio0cr. to use an external clock as the se- rial clock, set sio0cr to "111". the 8-bit transmit/receive mode is selected by setting sio0cr to "11". the transmit/receive operation is started by writing the first byte of transmit data to sio0buf and then setting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while the serial communication is stop- ped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to siocr is valid. 19.5.3.2 starting the transmit/receive operation the transmit/receive operation is started by writing data to sio0buf and then setting sio0cr to "1". the transmit data is transferred from sio0buf to the shift register, and the serial data is transmit- ted from the so0 pin according to the settings of sio0cr. at the same time, the serial data is received from the si0 pin according to the settings of sio0cr. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. the transmit data becomes undefined if the transmit/receive operation is started without writing any trans- mit data to sio0buf. by setting sio0cr to "1", sio0sr are automatically set to "1" and an in- tsio0 interrupt request is generated. sio0sr is cleared to "0" when the 8th bit of data is received. 19.5.3.3 transmit buffer and shift operation if any data is written to sio0buf when the serial communication is in progress and the shift register is empty, the written data is transferred to the shift register immediately. at this time, sio0sr re- mains at "0". if any data is written to sio0buf when some data remains in the shift register, sio0sr is set to "1". if new data is written to sio0buf in this state, the contents of sio0buf are overwritten by the new value. make sure that sio0sr is "0" before writing data to sio0buf. 19.5.3.4 operation on completion of transmission/reception when the data transmission/reception is completed, sio0sr is set to "1" and an intsio0 inter- rupt request is generated. the operation varies depending on the operating clock. tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 324 2012/5/18 ra001
(1) when the internal clock is used if sio0sr is "1", it is cleared to "0" and the transmit/receive operation continues. if sio0sr is already "1", sio0sr is set to "1". if sio0sr is "0", the transmit/receive operation is aborted. the sclk0 pin becomes the initial state and the so0 pin becomes the "h" level. sio0sr remains at "0". when the subse- quent data is written to sio0buf, sio0sr is set to "1", the sclk0 pin outputs the clock and the transmit/receive operation is restarted. to confirm the receive data, read it from sio0buf be- fore writing data to sio0buf. (2) when an external clock is used the transmit/receive operation continues. if the external serial clock is input without writing any da- ta to sio0buf, the last data value set to sio0buf is re-transmitted. at this time, the transmit under- run error flag sio0sr is set to "1". when the next 8-bit data is received completely before sio0buf is read, or in the state of sio0sr="1", sio0sr is set to "1". 19.5.3.5 stopping the transmit/receive operation set sio0cr to "0" to stop the transmit/receive operation. when sio0sr is "0", or when the shift operation is not in progress, the operation is stopped immediately. unlike the transmit mode, no intsio0 interrupt request is generated in this state. when sio0sr is "1", the operation is stopped after the 8-bit data is received completely. at this time, an intsio0 interrupt request is generated. after the operation has stopped completely, sio0sr are cleared to "0". other sio0sr registers keep their values. if the internal clock has been used, the so0 pin automatically returns to the "h" level. if an external clock has been used, the so0 pin keeps the last output value. to return the so0 pin to the "h" level, write "00" to sio0cr when the operation is stopped. the transmit/receive operation can be forced to stop by setting sio0cr to "00" during the op- eration. by setting sio0cr to "00", sio0cr and sio0sr are cleared to "0" and the sio stops the operation, regardless of the sio0sr value. the so0 pin becomes the "h" level. if the internal clock is selected, the sclk0 pin returns to the initial level. tmp89fw20a page 325 2012/5/18 ra001
figure 19-14 8-bit transmit/receive mode (internal clock and reserved stop) tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 326 2012/5/18 ra001 si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) de fg sio0buf (read buffer) ab c sio0cr sio0sr sio0sr sio0sr sio0sr data a data b writing data d read sio0buf reading data a reading data b reading data c writing data e writing data f writing data g reserved stop start operation wait bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data e bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data f
figure 19-15 8-bit transmit/receive mode (external clock and reserved stop) tmp89fw20a page 327 2012/5/18 ra001 si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) de fg sio0buf (read buffer) ab c sio0cr sio0cr sio0sr sio0sr sio0sr sio0sr data a 11 00 data b writing data d read sio0buf reading data a reading data b reading data c writing data e writing data f writing data g reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data e bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data f
figure 19-16 8-bit transmit/receive mode (external clock, occurrence of transmit under- run error and occurrence of overrun error) tmp89fw20a 19. synchronous serial interface (sio) 19.5 transfer modes page 328 2012/5/18 ra001 si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) dfg sio0buf (read buffer) ac read sio0sr sio0cr sio0sr sio0sr sio0sr sio0sr sio0sr sio0sr data a data b writing data d read sio0buf reading data a reading data c writing data f writing data g reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data d data f bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data g
19.6 ac characteristics figure 19-17 ac characteristics (v ss = 0 v, v dd = 4.5 v - 5.5 v, topr = -40 to 85c) parameter symbol condition min typ. max unit sclk cycle time t scy internal clock operation so pin and sclk pin load capacity=100 pf 2 / fcgck - - ns sclk "l" pulse width t scyl 1 / fcgck ? 25 - - sclk "h" pulse width t scyh 1 / fcgck ? 15 - - si input setup time t sis 60 - - si input hold time t sih 35 - - so output delay time t sod ?50 - 50 sclk cycle time t scy external clock operation so pin and sclk pin load capacity=100 pf 2 / fcgck - - sclk "l" pulse width t scyl 1 / fcgck - - sclk "h" pulse width t scyh 1 / fcgck - - si input setup time t sis 50 - - si input hold time t sih 50 - - so output delay time t sod 0 - 60 sclk low-level input voltage t sclkl 0 - v dd 0.30 v sclk high-level input voltage t sclkh v dd 0.70 - v dd figure 19-18 interval time between bytes tmp89fw20a page 329 2012/5/18 ra001 sclk pin t sis v sclkl v sclkh t scyl t scyh t scy t sod t sih si pin so pin c7 c6 d0 d1 d2 a7 a6 b0 b1 b2 tbi leading edge at the 1st bit (transmit edge) trailing edge at the 8th bit (receive edge) sclk0 pin so0 pin si0 pin symbol name minimum time tbi interval time between bytes 4/fcgck
tmp89fw20a 19. synchronous serial interface (sio) 19.6 ac characteristics page 330 2012/5/18 ra001
20. serial bus interface (sbi) the tmp89fw20a contains 1 channels of serial bus interface (sbi). the serial bus interface supports serial communication conforming to the i 2 c bus standards. it has clock synchro- nization and arbitration functions, and supports the multi-master in which multiple masters are connected on a bus. it also supports the unique free data format. tmp89fw20a page 331 2012/5/18 ra002
20.1 communication format 20.1.1 i 2 c bus the i 2 c bus is connected to devices via the sda0 and scl0 pins and can communicate with multiple devices. figure 20-1 device connections communications are implemented between a master and slave. the master transmits the start condition, the slave addresses, the direction bit and the stop condition to the slave(s) connected to the bus, and transmits and receives data. the slave detects these conditions transmitted from the master by the hardware, and transmits and receives data. the data format of the i 2 c bus that can communicate via the serial bus interface is shown in figure 20-2. the serial bus interface does not support the following functions among those specified by the i 2 c bus stand- ards: 1. start byte 2. 10-bit addressing 3. sda and scl pins falling edge slope control tmp89fw20a 20. serial bus interface (sbi) 20.1 communication format page 332 2012/5/18 ra002 vdd device 1 sda scl device 2 sda scl device n sda scl
figure 20-2 data format of i 2 c bus 20.1.2 free data format the free data format is for communication between a master and slave. in the free data format, the slave address and the direction bit are processed as data. figure 20-3 free data format tmp89fw20a page 333 2012/5/18 ra002 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p slave address data data 1 to 8 bits 1 r / w 8 bits 1 1 1 or more 1 or more 1 to 8 bits 1 1 1 s a c k a c k a c k p slave address data data slave address 1 to 8 bits 1 r / w 8 bits a c k r / w s (a) addressing format (b) addressing format (with restart) s r/w ack p : start condition : direction bit : acknowledge bit : stop condition 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p data data data 1 to 8 bits 1 (a) free data format s r/w ack p : start condition : direction bit : acknowledge bit : stop condition
20.2 configuration figure 20-4 serial bus interface 0 (sbi0) tmp89fw20a 20. serial bus interface (sbi) 20.2 configuration page 334 2012/5/18 ra002 sbi0cr1 i2c0ar sbi0dbr sbi0cr2 sbi0sr2 clock control circuit software reset circuit transfer control circuit shift register data control circuit l o r t n o c t u p t u o / t u p n i sda scl noise canceller noise canceller c b t s r w s n i p / b b / x r t / t s m k c a k c a o n k c s s l a b r l 0 s a / s a a / l a / x r t / t s m b b a s intsbi interrupt request
20.3 control the following registers are used to control the serial bus interface and monitor the operation status. ? serial bus interface control register 1 (sbi0cr1) ? serial bus interface control register 2 (sbi0cr2) ? serial bus interface status register 2 (sbi0sr2) ? serial bus interface data buffer register (sbi0dbr) ? i 2 c bus address register (i2c0ar) in addition, the serial bus interface has low power consumption registers that save power when the serial bus in- terface is not being used. low power consumption register 1 poffcr1 7 6 5 4 3 2 1 0 (0x00f75) bit symbol - - - sbi0en - uart2en uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 sbi0en i2c0 control 0 1 disable enable uart2en uart2 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable note 1: when sbi0en is cleared to "0", the clock supply to the serial bus interface is stopped. at this time, the data writ- ten to the serial bus interface control registers is invalid. when the serial bus interface is used, set sbi0en to "1" and then write the data to the serial bus interface control registers. tmp89fw20a page 335 2012/5/18 ra002
serial bus interface control register 1 sbi0cr1 (0x00022) 7 6 5 4 3 2 1 0 bit symbol bc ack noack sck read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note 1: fcgck: gear clock [hz], fs: low-frequency clock oscillation circuit clock note 2: don't change the contents of the registers when the start condition is generated, the stop condition is generated or the data transfer is in progress. write data to the registers before the start condition is generated or during the period from when an interrupt request is generated for stopping the data transfer until it is released. note 3: after a software reset is generated, all the bits of sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. note 5: when fcgck is 4mhz, sck should be not set to 0y000, 0y001 or 0y010 because it is not possible to satisfy the bus spec- ification of fast mode. serial bus interface control register 2 sbi0cr2 (0x00023) 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin sbim - swrst read/write w w w w w r w after reset 0 0 0 1 0 0 0 note 1: when sbi0cr2 is "0", no value can be written to sbi0cr2 except sbi0cr2. before writing values to sbi0cr2, write "1" to sbi0cr2 to activate the serial bus interface mode. note 2: don't change the contents of the registers, except sbi0cr2, when the start condition is generated, the stop condition is generated or the data transfer is in progress. write data to the registers before the start condition is gen- erated or during the period from when an interrupt request is generated for stopping the data transfer until it is released. note 3: make sure that the port is in a high state before switching the port mode to the serial bus interface mode. make sure that the bus is free before switching the serial bus interface mode to the port mode. note 4: sbi0cr2 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit op- eration. note 5: after a software reset is generated, all the bits of sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 6: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. serial bus interface status register 2 sbi0sr2 (0x00023) 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin al aas ad0 lrb read/write r r r r r r r r after reset 0 0 0 1 0 0 0 * note 1: * : unstable note 2: when sbi0cr2 becomes "0", sbi0sr is initialized. note 3: after a software reset is generated, all the bits of the sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. tmp89fw20a 20. serial bus interface (sbi) 20.3 control page 336 2012/5/18 ra002
i 2 c bus address register i2c0ar (0x00024) 7 6 5 4 3 2 1 0 bit symbol sa als read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note 1: don't set i2c0ar to "0x00". if it is set to "0x00", the slave address is deemed to be matched when the i 2 c bus standard start byte ("0x01") is received in the slave mode. note 2: don't change the contents of the registers when the start condition is generated, the stop condition is generated or the data transfer is in progress. write data to the registers before the start condition is generated or during the period from when an interrupt request is generated for stopping the data transfer until it is released. note 3: after a software reset is generated, all the bits of the sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. serial bus interface data buffer register sbi0dbr (0x00025) 7 6 5 4 3 2 1 0 bit symbol sbi0dbr read/write r/w after reset 0 0 0 0 0 0 0 0 note 1: write the transmit data beginning with the most significant bit (bit 7). note 2: sbi0dbr has individual writing and reading buffers, and written data cannot be read out. therefore, sbi0dbr must not be accessed by using a read-modify-write instruction, such as a bit operation. note 3: don't change the contents of the registers when the start condition is generated, the stop condition is generated or the data transfer is in progress. write data to the registers before the start condition is generated or during the period from when an interrupt request is generated for stopping the data transfer until it is released. note 4: to set sbi0cr2 to "1" by writing the dummy data to sbi0dbr, write 0x00. writing any data other than 0x00 cau- ses an improper value in the subsequently received data. note 5: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. tmp89fw20a page 337 2012/5/18 ra002
20.4 functions 20.4.1 low power consumption function the serial bus interface has a low power consumption register (poffcr1) that saves power when the seri- al bus interface is not being used. setting poffcr1 to "0" disables the basic clock supply to the serial bus interface to save pow- er. note that this makes the serial bus interface unusable. setting poffcr1 to "1" enables the ba- sic clock supply to the serial bus interface and makes external interrupts usable. after reset, poffcr1 is initialized to "0", and this makes the serial bus interface unusable. when using the serial bus interface for the first time, be sure to set poffcr1 to "1" in the initial setting of the program (before the serial bus interface control registers are operated). do not change poffcr1 to "0" during the serial bus interface operation, otherwise serial bus in- terface may operate unexpectedly. 20.4.2 selecting the slave address match detection and the general call detection sbi0cr1 enables and disables the slave address match detection and the general call de- tection in the slave mode. clearing sbi0cr1 to "0" enables the slave address match detection and the general call detection. setting sbi0cr1 to "1" disables the subsequent slave address match and general call de- tections. the slave addresses and "general call" sent from the master are ignored. no acknowledge- ment is returned and no interrupt request is generated. in the master mode, sbi0cr1 is ignored and has no influence on the operation. note:if sbi0cr1 is cleared to "0" during data transfer in the slave mode, it remains at "1" and re- turns an acknowledge signal of data transfer. 20.4.3 selecting the number of clocks for data transfer and selecting the acknowledge- ment or non-acknowledgment mode 1-word data transfer consists of data and an acknowledge signal. when the data transfer is finished, an inter- rupt request is generated. sbi0cr1 is used to select the number of bits of data to be transmitted/received subsequently. the acknowledgment mode is activated by setting sbi0cr1 to "1". the master device generates the clocks for an acknowledge signal and outputs an acknowledge signal in the receiver mode. the slave device counts the clocks for an acknowledge signal and outputs an acknowl- edge signal in the receiver mode. the non-acknowledgment mode is activated by setting sbi0cr1 to "0". the master device does not generate the clocks for an acknowledge signal. the slave device does not count the clocks for an acknowledge signal. 20.4.3.1 number of clocks for data transfer the number of clocks for data transfer is set by using sbi0cr1 and sbi0cr1. the acknowledgment mode is activated by setting sbi0cr1 to "1". tmp89fw20a 20. serial bus interface (sbi) 20.4 functions page 338 2012/5/18 ra002
in the acknowledgment mode, the master device generates the clocks that correspond to the number of da- ta bits, generates the clocks for an acknowledge signal, and generates an interrupt request. the slave device counts the clocks that correspond to the data bits, counts the clocks for an acknowl- edge signal, and generates an interrupt request. the non-acknowledgment mode is activated by setting sbi0cr1 to "0". in the non-acknowledgment mode, the master device generates the clocks that correspond to the num- ber of data bits, and generates an interrupt request. the slave device counts the clocks that correspond to the data bits, and generates an interrupt request. figure 20-5 number of clocks for data transfer and sbi0cr1 and sbi0cr1 the relationship between the number of clocks for data transfer and sbi0cr1 and sbi0cr1 is shown in table 20-1. table 20-1 relationship between the number of clocks for data transfer and sbi0cr1 and sbi0cr1 bc ack=0 (non-acknowledgment mode) ack=1 (acknowledgment mode) number of clocks for data transfer number of data bits number of clocks for data transfer number of data bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 bc is cleared to "000" by the start condition. therefore, the slave address and the direction bit are always transferred in 8-bit units. in other cases, bc keeps the set value. note:sbi0cr1 must be set before transmitting or receiving a slave address. when sbi0cr1 is cleared, the slave address match detection and the direction bit detection are not executed properly. 20.4.3.2 output of an acknowledge signal in the acknowledgment mode, the sda0 pin changes as follows during the period of the clocks for an ac- knowledge signal. ? in the master mode tmp89fw20a page 339 2012/5/18 ra002 22 33 44 56 11 sbi0cr1="110", sbi0cr1="0" intsbi0 interrupt request sbi0cr1="011", sbi0cr1="1"
in the transmitter mode, the sda0 pin is released to receive an acknowledge signal from the receiver during the period of the clocks for an acknowledge signal. in the receiver mode, the sda0 pin is pulled down to the low level and an acknowledge signal is generated during the period of the clocks for an acknowledge signal. ? in the slave mode when a match between the received slave address and the slave address set to i2c0ar is detected or when a general call is received, the sda0 pin is pulled down to the low level and an acknowledge signal is generated during the period of the clocks for an acknowledge signal. during the data transfer after the slave address match is detected or a "general call" is received in the transmitter mode, the sda0 pin is released to receive an acknowledge sig- nal from the receiver during the period of the clocks for an acknowledge signal. in the receiver mode, the sda0 pin is pulled down to the low level and an acknowledge sig- nal is generated. table 20-2 shows the states of the scl0 and sda0 pins in the acknowledg- ment mode. note:in the non-acknowledgment mode, the clocks for an acknowledge signal are not generated or coun- ted, and thus no acknowledge signal is output. table 20-2 states of the scl0 and sda0 pins in the acknowledgment mode mode pin condition transmitter receiver master scl0 - add the clocks for an acknowl- edge signal. add the clocks for an acknowl- edge signal sda0 - release the pin to receive an acknowledge signal output the low level as an ac- knowledge signal to the pin slave scl0 - count the clocks for an ac- knowledge signal count the clocks for an ac- knowledge signal sda0 when the slave address match is detected or a "general call" is re- ceived - output the low level as an ac- knowledge signal to the pin during transfer after the slave address match is detected or a "gener- al call" is received release the pin to receive an acknowledge signal output the low level as an ac- knowledge signal to the pin 20.4.4 serial clock 20.4.4.1 clock source sbi0cr1 is used to set the high and low periods of the serial clock to be output in the mas- ter mode. sck t high (m/fcgck) t low (n/fcgck) m n 000: 9 12 001: 11 14 010: 15 18 011: 23 26 100: 39 42 101: 71 74 110: 135 138 111: 263 266 tmp89fw20a 20. serial bus interface (sbi) 20.4 functions page 340 2012/5/18 ra002
figure 20-6 scl output note:there are cases where the high period differs from t high selected at sbi0cr1 when the ris- ing edge of the scl pin becomes blunt due to the load capacity of the bus. in the master mode, the hold time when the start condition is generated is t high [s] and the setup time when the stop condition is generated is t high [s]. when sbi0cr2 is set to "1" in the slave mode, the time that elapses before the release of the scl pin is t low [s]. in both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low lev- el period must be 5/fcgck[s] or longer for the externally input clock, regardless of the sbi0cr1 set- ting. figure 20-7 scl input 20.4.4.2 clock synchronization in the i 2 c bus, due to the structure of the pin, in order to drive a bus with a wired and, a master de- vice which pulls down a clock pulse to low will, in the first place, invalidate the clock pulse of another mas- ter device which generates a high-level clock pulse. therefore, the master outputting the high level must de- tect this to correspond to it. the serial bus interface circuit has a clock synchronization function. this function ensures normal trans- fer even if there are two or more masters on the same bus. the example explains clock synchronization procedures when two masters simultaneously exist on a bus. figure 20-8 example of clock synchronization tmp89fw20a page 341 2012/5/18 ra002 1/fscl t low t high scl output t high = m / fcgck t low = n / fcgck fscl = 1 / (t high + t low ) scl input t low t high t high 3 / fcgck t low 5 / fcgck count start abc scl pin (master 1) scl pin (master 2) scl (bus) count reset wait count reset
as master 1 pulls down the scl pin to the low level at point "a", the scl line of the bus becomes the low level. after detecting this situation, master 2 resets counting a clock pulse in the high level and sets the scl pin to the low level. master 1 finishes counting a clock pulse in the low level at point "b" and sets the scl pin to the high lev- el. since master 2 holds the scl line of the bus at the low level, master 1 waits for counting a clock pulse in the high level. after master 2 sets a clock pulse to the high level at point "c" and detects the scl line of the bus at the high level, master 1 starts counting a clock pulse in the high level. then, the mas- ter, which has finished the counting a clock pulse in the high level, pulls down the scl pin to the low lev- el. the clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. 20.4.5 master/slave selection to set a master device, sbi0cr2 should be set to "1". to set a slave device, sbi0cr2 should be cleared to "0". when a stop condition on the bus or an ar- bitration lost is detected, sbi0cr2 is cleared to "0" by the hardware. 20.4.6 transmitter/receiver selection to set the device as a transmitter, sbi0cr2 should be set to "1". to set the device as a receiver, sbi0cr2 should be cleared to "0". for the i 2 c bus data transfer in the slave mode, sbi0cr2 is set to "1" by the hardware if the direc- tion bit (r/ w) sent from the master device is "1", and is cleared to "0" if the bit is "0". in the master mode, after an acknowledge signal is returned from the slave device, sbi0cr2 is cleared to "0" by hardware if a transmitted direction bit is "1", and is set to "1" by hardware if it is "0". when an acknowledge signal is not returned, the current condition is maintained. when a stop condition on the bus or an arbitration lost is detected, sbi0cr2 is cleared to "0" by the hardware. table 20-3 shows sbi0cr2 changing conditions in each mode and sbi0cr2 val- ue after changing. note:when sbi0cr1 is "1", the slave address match detection and the general call detec- tion are disabled, and thus sbi0cr2 remains unchanged. table 20-3 sbi0cr1 operation in each mode mode direction bit changing condition trx after changing slave mode "0" a received slave address is the same as the value set to i2c0ar "0" "1" "1" master mode "0" ack signal is returned "1" "1" "0" when the serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. they are handled as data just after generating the start condition. sbi0cr2 is not changed by the hardware. tmp89fw20a 20. serial bus interface (sbi) 20.4 functions page 342 2012/5/18 ra002
20.4.7 start/stop condition generation when sbi0sr2 is "0", a slave address and a direction bit which are set to the sbi0dbr are output on a bus after generating a start condition by writing "1" to sbi0cr2 , sbi0cr2, sbi0cr2 and sbi0cr2. it is necessary to set sbi0cr1 to "1" before generating the start condition. figure 20-9 generating the start condition and a slave address when sbi0cr2 is "1", the sequence of generating the stop condition on the bus is started by writ- ing "1" to sbi0cr2, sbi0cr2 and sbi0cr2 and writing "0" to sbi0cr2. when a stop condition is generated. the scl line on a bus is pulled down to the low level by another de- vice, a stop condition is generated after releasing the scl line. figure 20-10 stop condition generation the bus condition can be indicated by reading the contents of sbi0sr2. sbi0sr2 is set to "1" when the start condition on the bus is detected (bus busy state) and is cleared to "0" when the stop condi- tion is detected (bus free state). 20.4.8 interrupt service request and release when a serial bus interface circuit is in the master mode and transferring a number of clocks set by sbi0cr1 and sbi0cr1 is complete, a serial bus interface interrupt request (intsbi0) is gener- ated. in the slave mode, a serial bus interface interrupt request (intsbi0) is generated when the above and follow- ing conditions are satisfied: ? at the end of the acknowledge signal when the received slave address matches to the value set by the i2c0ar with sbi0cr1 set at "0" ? at the end of the acknowledge signal when a "general call" is received with sbi0cr1 set at "0" ? at the end of transferring or receiving after matching of the slave address or receiving of "gener- al call" when a serial bus interface interrupt request occurs, sbi0cr2 is cleared to "0". during the time that sbi0cr2 is "0", the scl0 pin is pulled down to the low level. tmp89fw20a page 343 2012/5/18 ra002 slave address and direction bit start condition acknowledge signal 23456789 a3 a2 a1 a0 a4 a5 a6 r/w 1 scl0 pin sda0 pin intsbi0 interrupt request stop condition scl0 pin sda0 pin
figure 20-11 sbi0cr2 and scl0 pin writing data to sbi0dbr sets sbi0cr2 to "1". the time from sbi0cr2 being set to "1" un- til the sbi0 pin is released takes t low . although sbi0cr2 can be set to "1" by the software, sbi0cr2 can not be cleared to "0" by the software. 20.4.9 setting of serial bus interface mode sbi0cr2 is used to set serial bus interface mode. setting sbi0cr2 to "1" selects the serial bus interface mode. setting it to "0" selects the port mode. set sbi0cr2 to "1" in order to set serial bus interface mode. before setting of serial bus inter- face mode, confirm serial bus interface pins in a high level, and then, write "1" to sbi0cr2. and switch a port mode after confirming that a bus is free and set sbi0cr2 to "0". note:when sbi0cr2 is "0", no data can be written to sbi0cr2 except sbi0cr2. before setting values to sbi0cr2, write "1" to sbi0cr2 to activate the serial bus interface mode. 20.4.10 software reset the serial bus interface circuit has a software reset function that initializes the serial bus interface circuit. if the serial bus interface circuit locks up, for example, due to noise, it can be initialized by using this function. a software reset is generated by writing "10" and then "01" to sbi0cr2. after a software reset is generated, the serial bus interface circuit is initialized and all the bits of sbi0cr2 register, except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers, are initialized. 20.4.11 arbitration lost detection monitor since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple- mented in order to guarantee the contents of transferred data. data on the sda line is used for bus arbitration of the i 2 c bus. the following shows an example of a bus arbitration procedure when two master devices exist simultaneous- ly on a bus. master 1 and master 2 output the same data until point "a". after that, when master 1 outputs "1" and master 2 outputs "0", since the sda line of a bus is wired and, the sda line is pulled down to the low level by master 2. when the scl line of a bus is pulled-up at point "b", the slave device reads data on the sda line, that is data in master 2. data transmitted from master 1 becomes invalid. the state in master tmp89fw20a 20. serial bus interface (sbi) 20.4 functions page 344 2012/5/18 ra002 23 789 1 1 t low scl0 pin scl0 pin is pulled to low when sbi0cr2 is "0" set sbi0cr2 to "1" or write data to sbi0dbr sbi0cr2 intsbi0 interrupt request
1 is called "arbitration lost". a master device which loses arbitration releases the sda pin and the scl pin in order not to effect data transmitted from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuously after the second word. figure 20-12 arbitration lost the serial bus interface circuit compares levels of a sda line of a bus with its sda pin at the rising edge of the scl line. if the levels are unmatched, arbitration is lost and sbi0sr2 is set to "1". when sbi0sr2 is set to "1", sbi0cr2 and sbi0cr2 are cleared to "0" and the mode is switched to a slave receiver mode. thus, the serial bus interface circuit stops output of clock pulses dur- ing data transfer after the sbi0sr2 is set to "1". after the data transfer is completed, sbicr2 is cleared to "0" and the scl pin is pulled down to the low level. sbi0sr2 is cleared to "0" by writing data to the sbi0dbr, reading data from the sbi0dbr or writ- ing data to the sbi0cr2. figure 20-13 example when master b is a serial bus interface circuit tmp89fw20a page 345 2012/5/18 ra002 ab scl (bus) sda pin (master 1) sda pin (master 2) sda (bus) the sda pin becomes "1" after losing arbitration. scl pin sda pin scl pin sda pin sbi0sr2 sbi0cr2 sbi0cr2 sbi0cr2 intsbi0 interrupt request a ccess to sbi0dbr or sbi0cr2 d4a 123 123 456789 12 3456789 master a master b stop clock output releasing sda pin and scl pin to high level as losing arbitration. d5a d6a d7a d3a d2a d1a d0a d6a d7a d5a? d6a? d7a?
20.4.12 slave address match detection monitor in the slave mode, sbi0sr2 is set to "1" when the received data is "general call" or the re- ceived data matches the slave address setting by i2c0ar with sbi0cr1 set at "0" and the i 2 c bus mode is active (i2c0ar="0"). setting sbi0cr1 to "1" disables the subsequent slave address match and general call de- tections. sbi0sr2 remains at "0" even if a "general call" is received or the same slave ad- dress as the i2c0ar set value is received. when a serial bus interface circuit operates in the free data format (i2c0ar= "1"), sbi0sr2 is set to "1" after receiving the first 1-word of data. sbi0sr2 is cleared to "0" by writ- ing data to the sbi0dbr or reading data from the sbi0dbr. figure 20-14 changes in the slave address match detection monitor 20.4.13 general call detection monitor sbi0sr2 is set to "1" when sbi0cr1 is "0" and general call (all 8-bit received da- ta is "0" immediately after a start condition) in a slave mode. setting sbi0cr1 to "1" disables the subsequent slave address match and general call de- tections. sbi0sr2 remains at "0" even if a "general call" is received. sbi0sr2 is cleared to "0" when a start or stop condition is detected on a bus. figure 20-15 changes in the general call detection monitor tmp89fw20a 20. serial bus interface (sbi) 20.4 functions page 346 2012/5/18 ra002 start condition scl0 (bus) sda0 (bus) sda0 pin sbi0sr2 intsbi0 interrupt request output of an acknowledge signal writing or reading sbi0dbr slave address + direction bit 23456789 1 sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w start condition stop condition output of an acknowledge signal general call scl (bus) sda (bus) sda0 pin sbi0sr2 intsbi0 interrupt request 23456789 1
20.4.14 last received bit monitor the sda line value stored at the rising edge of the scl line is set to sbi0sr2. in the acknowledge mode, immediately after an interrupt request is generated, an acknowledge signal is read by reading the contents of sbi0sr2. figure 20-16 changes in the last received bit monitor 20.4.15 slave address and address recognition mode specification when the serial bus interface circuit is used in the i 2 c bus mode, clear i2c0ar to "0", and set i2c0ar to the slave address. when the serial bus interface circuit is used with a free data format not to recognize the slave address, set i2c0ar to "1". with a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after the start condition. tmp89fw20a page 347 2012/5/18 ra002 acknowledgment 23456789 1 d7 d6 d5 d4 d3 d2 d1 d0 d6 d7 d5 d4 d3 d2 d1 d acknowledgment scl sda sbi0sr2
20.5 data transfer of i 2 c bus 20.5.1 device initialization set poffcr1 to "1". after confirming that the serial bus interface pin is high level, set sbi0cr2 to "1" to select the se- rial bus interface mode. set sbi0cr1 to "1", sbi0cr1 to "0" and sbi0cr1 to "000" to count the num- ber of clocks for an acknowledge signal, to enable the slave address match detection and the general call detection, and set the data length to 8 bits. set t high and t low at sbi0cr1. set a slave address at i2c0ar and set i2c0ar to "0" to select the i 2 c bus mode. finally, set sbi0cr2, sbi0cr2 and sbi0cr2 to "0", sbi0cr2 to "1" and sbi0cr2 to "00" for specifying the default setting to a slave receiver mode. note:the initialization of a serial bus interface circuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. if not, the data can not be received correctly because the other device starts transferring before an end of the initialization of a serial bus interface circuit. example :initialize a device chk_port: ld a, (p2prd) ; checks whether the serial bus interface pin is at the high level and a, 0x18 cmp a, 0x18 jr nz, code_addr(chk_port) ld (sbi0cr2), 0x18 ; selects the serial bus interface mode ld (sbi0cr1), 0x16 ; selects the acknowledgment mode and sets sbi0cr1 to "110" ld (i2c0ar), 0xa0 ; sets the slave address to 1010000 and selects the i2c bus mode ld (sbi0cr2), 0x18 ; selects the slave receiver mode 20.5.2 start condition and slave address generation confirm a bus free status (sbi0sr2="0"). set sbi0cr1 to "1" and specify a slave address and a direction bit to be transmitted to the sbi0dbr. by writing "1" to sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2, the start condi- tion is generated on a bus and then, the slave address and the direction bit which are set to the sbi0dbr are output. the time from generating the start condition until the falling sbi0 pin takes t high . an interrupt request occurs at the 9th falling edge of a scl clock cycle, and sbi0cr2 is cleared to "0". the scl0 pin is pulled down to the low level while sbi0cr2 is "0". when an interrupt request oc- curs, sbi0cr2 changes by the hardware according to the direction bit only when an acknowledge sig- nal is returned from the slave device. note 1: do not write a slave address to the sbi0dbr while data is transferred. if data is written to the sbi0dbr, data to be output may be destroyed. note 2: the bus free state must be confirmed by software within 98.0 s (the shortest transmitting time accord- ing to the standard mode i 2 c bus standard) or 23.7s (the shortest transmitting time according to the fast mode i 2 c bus standard) after setting of the slave address to be output. only when the bus free state is confirmed, set "1" to sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 to generate the start conditions. if the writing of slave address and setting of sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 doesn't finish within 98.0s or 23.7s, the other mas- ters may start the transferring and the slave address data written in sbi0dbr may be broken. tmp89fw20a 20. serial bus interface (sbi) 20.5 data transfer of i 2 c bus page 348 2012/5/18 ra002
example :generate the start condition chk_bb: test (sbi0sr2).bb ; confirms that the bus is free jr f, code_addr(chk_bb) ld (sbi0dbr), 0xcb ; the transmission slave address 0x65 and the direction bit "1" ld (sbi0cr2), 0xf8 ; write "1" to sbi0cr2, , and to "1" figure 20-17 generating the start condition and the slave address 20.5.3 1-word data transfer check sbi0sr2 by the interrupt process after a 1-word data transfer is completed, and determine whether the mode is a master or slave. 20.5.3.1 when sbi0sr2 is "1" (master mode) check sbi0sr2 and determine whether the mode is a transmitter or receiver. (1) when sbi0sr2 is "1" (transmitter mode) check sbi0sr2. when sbi0sr2 is "1", a receiver does not request data. imple- ment the process to generate a stop condition (described later) and terminate data transfer. when sbi0sr2 is "0", the receiver requests subsequent data. when the data to be transmit- ted subsequently is other than 8 bits, set sbi0cr1 again, set sbi0cr1 to "1", and write the transmitted data to sbi0dbr. after writing the data, sbi0cr2 becomes "1", a serial clock pulse is generated for transfer- ring the subsequent 1-word data from the scl0 pin, and then the 1-word data is transmitted from the sda0 pin. after the data is transmitted, an interrupt request occurs. sbi0cr2 become "0" and the scl0 pin is set to the low level. if the data to be transferred is more than one word in length, re- peat the procedure from the sbi0sr2 checking above. tmp89fw20a page 349 2012/5/18 ra002 start condition scl0 pin sda0 pin sbi0cr1 sbi0cr2 interrupt request signal slave address + direction bit 23456789 1 acknowledgem ent signal from a slave sbi0cr2 is cleared to "0" when the direction bit is "1"and an acknowledge signal is returned.
figure 20-18 example when sbi0cr1="000" and sbi0cr1="1" (2) when sbi0sr2 is "0" (receiver mode) when the data to be transmitted subsequently is other than 8 bits, set sbi0cr1 again. set sbi0cr1< ack> to "1" and read the received data from the sbi0dbr (reading data is undefined im- mediately after a slave address is sent). after the data is read, sbi0cr2 becomes "1" by writing the dummy data (0x00) to the sbi0dbr. the serial bus interface circuit outputs a serial clock pulse to the scl0 pin to transfer the subsequent 1-word data and sets the sda0 pin to "0" at the acknowledge signal timing. an interrupt request occurs and sbi0cr2 becomes "0". then a serial bus interface circuit out- puts a clock pulse for 1-word data transfer and the acknowledge signal by writing data to the sbi0dbr or setting sbi0cr2 to "1" after reading the received data. figure 20-19 example when sbi0cr1="000" and sbi0cr1="1" to make the transmitter terminate transmission, execute following procedure before receiving a last data. 1. read the received data. 2. clear sbi0cr1 to "0" and set sbi0cr1 to "000". 3. to set sbi0cr2 to "1", write a dummy data (0x00) to sbi0dbr. transfer 1-word data in which no clock is generated for an acknowledge signal by setting sbi0cr2 to "1". next, execute following procedure. tmp89fw20a 20. serial bus interface (sbi) 20.5 data transfer of i 2 c bus page 350 2012/5/18 ra002 23456789 1 acknowledge signal from the receiver d7 d6 d5 d4 d3 d2 d1 d0 scl0 pin sda0 pin sbi0cr2 intsbi0 interrupt request write to sbi0dbr acknowledge signal to the transmitter 23456789 9 1 d7 read sbi0dbr scl0 pin sda0 pin sbi0cr2 intsbi0 interrupt request write to sbi0dbr new d7 d5 d6 d4 d3 d2 d1 d0
1. read the received data. 2. clear sbi0cr1 to "0" and set sbi0cr1 to "001". 3. to set sbi0cr2 to "1", write a dummy data (0x00) to sbi0dbr. transfer 1-bit data by setting sbi0cr1 to "1". in this case, since the master device is a receiver, the sda line on a bus keeps the high level. the transmitter receives the high-level signal as a negative acknowledge signal. the receiver indi- cates to the transmitter that data transfer is complete. after 1-bit data is received and an interrupt request has occurred, generate the stop condition to ter- minate data transfer. figure 20-20 termination of data transfer in the master receiver mode 20.5.3.2 when sbi0sr2 is "0" (slave mode) in the slave mode, a serial bus interface circuit operates either in the normal slave mode or in the slave mode after losing arbitration. in the slave mode, the conditions of generating the serial bus interface interrupt request (intsbi0) are fol- lows: ? at the end of the acknowledge signal when the received slave address matches the value set by the i2c0ar with sbi0cr1 set at "0" ? at the end of the acknowledge signal when a "general call" is received with sbi0cr1 set at "0" ? at the end of transferring or receiving after matching of slave address or receiving of "gener- al call" the serial bus interface circuit changes to the slave mode if arbitration is lost in the master mode. and an interrupt request occurs when the word data transfer terminates after losing arbitration. the generation of the interrupt request and the behavior of sbi0cr2 after losing arbitration are shown in table 20-4. tmp89fw20a page 351 2012/5/18 ra002 negative acknowledge signal to the transmitter after reading the received data, clear sbi0cr1 to "0" and writing the dummy data (0x00) scl0 pin sda0 pin sbi0cr intsbi0 interrupt request after reading the reveived data, set sbi0cr1 to "001" and write dummy data (0x00) 2345678 1 9 d7 d5 d6 d4 d3 d2 d1 d0
table 20-4 the behavior of an interrupt request and sbi0cr2 after losing arbitration when the arbitration lost occurs during transmis- sion of slave address as a master when the arbitration lost occurs during transmis- sion of data as master transmitter interrupt request an interrupt request is generated at the termination of word-data transfer. sbi0cr2 sbi0cr2 is cleared to "0". when an interrupt request occurs, sbi0cr2 is reset to "0", and the scl0 pin is set to the low lev- el. either writing data to the sbi0dbr or setting sbi0cr2 to "1" releases the scl0 pin after tak- ing t low . check sbi0sr2, sbi0sr2, sbi0sr2 and sbi0sr2 and implement process- es according to conditions listed in table 20-5. table 20-5 operation in the slave mode sbi0sr2< trx> sbi0sr2< al> sbi0sr2< aas> sbi0sr2< ad0> conditions process 1 1 1 0 the serial bus interface circuit loses ar- bitration when transmitting a slave ad- dress, and receives a slave address of which the value of the direction bit sent from another master is "1". set the number of bits in 1 word to sbi0cr1 and write the transmitted data to the sbi0dbr. 0 1 0 in the slave receiver mode, the serial bus interface circuit receives a slave ad- dress of which the value of the direc- tion bit sent from the master is "1". 0 0 in the slave transmitter mode, the serial bus interface circuit finishes the trans- mission of 1-word data check sbi0sr2. if it is set to "1", set sbi0cr2 to "1" since the receiv- er does not request subsequent data. then, clear sbi0cr2 to "0" to re- lease the bus. if sbi0sr2 is set to "0", set the number of bits in 1 word to sbi0cr1 and write the transmitted data to sbi0dbr since the receiver re- quests subsequent data. 0 1 1 1/0 the serial bus interface circuit loses ar- bitration when transmitting a slave ad- dress, and receives a slave address of which the value of the direction bit sent from another master is "0" or receives a "general call". write the dummy data (0x00) to the sbi0dbr to set sbi0cr2 to "1", or write "1" to sbi0cr2. 0 0 the serial bus interface circuit loses ar- bitration when transmitting a slave ad- dress or data, and terminates transfer- ring the word data. the serial bus interface circuit is changed to the slave mode. write the dummy data (0x00) to the sbi0dbr to clear sbi0sr2 to "0" and set sbi0cr2 to "1". 0 1 1/0 in the slave receiver mode, the serial bus interface circuit receives a slave ad- dress of which the value of the direc- tion bit sent from the master is "0" or re- ceives "general call". write the dummy data (0x00) to the sbi0dbr to set sbi0cr2 to "1", or write "1" to sbi0cr2. 0 1/0 in the slave receiver mode, the serial bus interface circuit terminates the re- ceipt of 1-word data. set the number of bits in 1-word to sbi0cr1, read the received data from the sbi0dbr and write the dummy data (0x00). note:in the slave mode, if the slave address set in i2c0ar is "0x00", a start byte "0x01" in i 2 c bus stand- ard is received, the device detects slave address match and sbi0cr2 is set to "1". do not set i2c0ar to "0x00". tmp89fw20a 20. serial bus interface (sbi) 20.5 data transfer of i 2 c bus page 352 2012/5/18 ra002
20.5.4 stop condition generation when sbi0cr2 is "1", a sequence of generating a stop condition is started by setting "1" to sbi0cr2, sbi0cr2 and sbi0cr2 and clearing sbi0cr2 to "0". do not modify the contents of sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 until a stop condi- tion is generated on a bus. when a scl line on a bus is pulled down by other devices, a serial bus interface circuit generates a stop con- dition after a scl line is released. the time from the releasing scl line until the generating the stop condition takes t high . example :generate the stop condition ld (sbi0cr2), 0xd8 ; sets sbi0cr2, and to "1" and sbi0cr2 to "0" chk_bb: test (sbi0sr2).bb ;waits until the bus is set free jr t, code_addr(chk_bb) figure 20-21 stop condition generation 20.5.5 restart restart is used to change the direction of data transfer between a master device and a slave device during transferring data. the following explains how to restart the serial bus interface circuit. clear sbi0cr2, sbi0cr2 and sbi0cr2 to "0" and set sbi0cr2 to "1". the sda0 pin retains the high level and the scl0 pin is released. since this is not a stop condition, the bus is assumed to be in a busy state from other devices. check sbi0sr2 until it becomes "0" to check that the scl0 pin of the serial bus interface circuit is re- leased. check sbi0sr2 until it becomes "1" to check that the scl line on the bus is not pulled down to the low level by other devices. tmp89fw20a page 353 2012/5/18 ra002 stop condition if the scl of the bus is pulled down by other devices, the stop condition is generated after it is released sbi0cr2="1" sbi0cr2="1" sbi0cr2="0" sbi0cr2="1" scl0 pin scl (bus) sda0 pin sbi0cr2 sbi0sr2
after confirming that the bus stays in a free state, generate a start condition in the procedure "20.5.2 start con- dition and slave address generation". in order to meet the setup time at a restart, take at least 4.7s of waiting time by the software in the stand- ard mode i 2 c bus standard or at least 0.6s of waiting time in the fast mode i 2 c bus standard from the time of restarting to confirm that a bus is free until the time to generate a start condition. note:when the master is in the receiver mode, it is necessary to stop the data transmission from the slave device before the stop condition is generated. to stop the transmission, the master device make the slave device receiving a negative acknowledge. therefore, sbi0sr2 is "1" before gen- erating the restart and it can not be confirmed that scl line is not pulled down by other devices. please confirm the scl line state by reading the port. example :generate a restart ld (sbi0cr2), 0x18 ; sets sbi0cr2, and to "0" and sbi0cr2 to "1" chk_bb: test (sbi0sr2).bb ; waits until sbi0sr2 becomes "0" jr t, code_addr(chk_bb) chk_lrb: test (sbi0sr2).lrb ; waits until sbi0sr2 becomes "1" jr f, code_addr(chk_lrb) . . ; wait time process by the software . ld (sbi0cr2), 0xf8 ; sets sbi0cr2, , and to "1" figure 20-22 timing diagram when restarting tmp89fw20a 20. serial bus interface (sbi) 20.5 data transfer of i 2 c bus page 354 2012/5/18 ra002 start condition sbi0cr2="0" sbi0cr2="0" sbi0cr2="0" sbi0cr2="1" scl (bus) scl0 pin sda0 pin sbi0sr2 sbi0sr2 sbi0cr2 sbi0cr2="1" sbi0cr2="1" sbi0cr2="1" sbi0cr2="1" 4.7 s min. in the normal mode or 0.6 s min. in the fast mode
20.6 ac specifications the ac specifications are as listed below. the operating mode (fast or standard) mode should be selected suitable for frequency of fcgck. for these operat- ing mode, refer to the following table. table 20-6 ac specifications (circuit output timing) parameter symbol standard mode fast mode unit min. max. min. max. scl clock frequency f scl 0 fcgck / (m+n) 0 fcgck / (m+n) khz hold time (re)start condition. this peri- od is followed by generation of the first clock pulse. t hd;sta m / fcgck - m / fcgck - s low-level period of scl clock (output) t low n / fcgck - n / fcgck - s high-level period of scl clock (output) t high m / fcgck - m / fcgck - s low-level period of scl clock (input) t low 5 / fcgck - 5 / fcgck - s high-level period of scl clock (input) t high 3 / fcgck - 3 / fcgck - s restart condition setup time t su;sta depends on the software - depends on the software - s data hold time t hd;dat 0 5 / fcgck 0 5 / fcgck s data setup time t su;dat 250 - 100 - ns rising time of sda and scl signals t r - 1000 - 300 ns falling time of sda and scl signals t f - 300 - 300 ns stop condition setup time t su;sto m / fcgck - m / fcgck - s bus free time between the stop condi- tion and the start condition t buf depends on the software - depends on the software - s time before rising of scl after sbicr2 is changed from "0" to "1" t su;scl n / fcgck - n / fcgck - s note:for m and n, refer to"20.4.4.1 clock source". figure 20-23 definition of timing (no. 1) tmp89fw20a page 355 2012/5/18 ra002 t low t f t f t su;sta t su;sto t buf t hd;sta t r t su;dat t hd;sta t high t hd;dat t f
figure 20-24 definition of timing (no. 2) tmp89fw20a 20. serial bus interface (sbi) 20.6 ac specifications page 356 2012/5/18 ra002 scl sbicr2 su;scl t
21. key-on wakeup (kwu) the key-on wakeup is a function for releasing the stop mode at the stop pin or at pins kwi2 through kwi0. 21.1 configuration figure 21-1 key-on wakeup circuit tmp89fw20a page 357 2012/5/18 ra000 syscr1 0 1 s y 76543210 kwucr0 (0x0fc4) kwi0 kwi1 kwi2 stop stop mode release signal (to be released if set to ?1?) selector rising edge detection port port port port
21.2 control key-on wakeup control registers (kwucr0) can be configured to designate the key-on wakeup pins (kwi2 through kwi0) as stop mode release pins and to specify the stop mode release levels of each of these designa- ted pins. key-on wakeup control register 0 kwucr0 7 6 5 4 3 2 1 0 (0x00fc4) bit symbol "0" "0" kw2le kw2en kw1le kw1en kw0le kw0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 kw2le stop mode release level of kwi2 pin 0: 1: low level high level kw2en input enable/disable control of kwi2 pin 0: 1: disable enable kw1le stop mode release level of kwi1 0: 1: low level high level kw1en input enable/disable control of kwi1 pin 0: 1: disable enable kw0le stop mode release level of kwi0 pin 0: 1: low level high level kw0en input enable/disable control of kwi0 pin 0: 1: disable enable note:make sure that you write "0" to bit7 and bit6 of kwucr0. key-on wakeup control register 1 kwucr1 7 6 5 4 3 2 1 0 (0x00fc5) bit symbol kw7le kw7en kw6le kw6en kw5le kw5en kw4le kw4en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 kw7le stop mode release level of kwi7 pin 0: 1: low level high level kw7en input enable/disable control of kwi7 pin 0: 1: disable enable kw6le stop mode release level of kwi6 pin 0: 1: low level high level kw6en input enable/disable control of kwi6 pin 0: 1: disable enable kw5le stop mode release level of kwi5 pin 0: 1: low level high level kw5en input enable/disable control of kwi5 pin 0: 1: disable enable kw4le stop mode release level of kwi4 pin 0: 1: low level high level kw4en input enable/disable control of kwi4 pin 0: 1: disable enable tmp89fw20a 21. key-on wakeup (kwu) 21.2 control page 358 2012/5/18 ra000
21.3 functions by using the key-on wakeup function, the stop mode can be released at a stop pin or at kwim pin (m: 0 through 2). after resetting, the stop pin is the only stop mode release pin. to designate the kwim pin as a stop mode release pin, therefore, it is necessary to configure the key-on wakeup control register (kwucrn) (n: 0 or 1). because the stop pin lacks a function for disabling inputs, it can be designated as a pin for receiving a stop mode release signal, irrespective of whether the key-on wakeup function is used or not. ? setting kwucrn and p4pu registers to designate a key-on wakeup pin (kwim) as a stop mode release pin, set kwucrn to "1". after kwim pin is set to "1" at kwucrn, a specific stop mode release level can be specified for this pin at kwucrn. if kwucrn is set to "0", stop mode is re- leased when an input is at a low level. if it is set to "1", stop mode is released when an input is at a high level. for example, if you want to release stop mode by inputting a high-level signal into a kwi0 pin, set kwucr0 to "1", " and kwucr0 to "1". each kwim pin can be connected to internal pull-up resistors. before connecting to internal pull-up re- sistors, the corresponding bits in the pull-up control register (p4pu) at port p4 must be set to "1". ? starting stop mode to start the stop mode, set syscr1 to "1" (level release mode), and syscr1 to "1". to use the key-on wakeup function, do not set syscr1 to "0" (edge release mode). if the key- on wakeup function is used in edge release mode, stop mode cannot be released, although a rising edge is input into the stop pin. this is because the kwim pin enabling inputs to be received is at a release lev- el after the stop mode starts. ? releasing stop mode to release stop mode, input a high-level signal into the stop pin or input a specific release level in- to the kwim pin for which receipt of inputs is enabled. if you want to release stop mode at the kwim pin, rather than the stop pin, continue inputting a low-level signal into the stop pin throughout the peri- od from when the stop mode is started to when it is released. if the stop pin or kwim pin is already at a release level when the stop mode starts, the following in- struction will be executed without starting the stop mode (with no warm-up performed). note 1: if an analog voltage is applied to kwim pin for which receipt of inputs is enabled by the key-on wakeup con- trol register (kwucrn) setting, a penetration current will flow. therefore, in this case, the analog voltage should be not applied to this pin. table 21-1 stop mode release level (edge) pin name release level (edge) syscr1="1" (level release mode) syscr1="0" (edge release mode) kwucrn="0" kwucrn="1" stop "h" level rising edge kwim "l" level "h" level don't use tmp89fw20a page 359 2012/5/18 ra000
example :a case in which stop mode is started with the release level of the stop pin set to a high level and the re- lease level of kwi0 set to a low level (connected to an internal pull-up resistor of the kwi0 pin) di ; imf0 set (p4pu).4 ; kwi0 (p44) connected to a pull-up resistor ld (kwucr0), 0y00000001 ; the kwi0 pin is set to enable inputs, and its release level is set ; to a low level. ld (syscr1), 0y10100000 ; starting in level release mode tmp89fw20a 21. key-on wakeup (kwu) 21.3 functions page 360 2012/5/18 ra000
22. 10-bit ad converter (adc) the tmp89fw20a has a 10-bit successive approximation type ad converter. 22.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 22-1. it consists of control registers adccr1 and adccr2, converted value registers adcdrl and adcdrh, a da converter, a sample-hold circuit, a comparator, a successive comparison circuit, etc. figure 22-1 10-bit ad converter note 1: before using the ad converter, set an appropriate value to the i/o port register which is also used as an analog input port. for details, see the section on "i/o ports". note 2: the da converter current (iref) is automatically cut off at times other than during ad conversion. tmp89fw20a page 361 2012/5/18 ra002 2 4 10 10 8 2 ainen s r d a r/2 r/2 r ack amd ad converted value registers 1 and 2 ad converter control registers 1 and 2 f b d a f c o e intadc sain n successive approximation circuit adccr2 adcdrl adcdrh adccr1 sample-hold circuit a s en shift clock da converter input selector y reference voltage analog comparator 3 control circuit avss varef avdd ain0 ain7
22.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects an analog channel in which to perform ad conversion, selects an ad conversion op- eration mode, and controls the start of the ad converter. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time, and monitors the operating status of the ad converter. 3. ad converted value registers (adcdrh and adcdrl) these registers store the digital values generated by the ad converter. tmp89fw20a 22. 10-bit ad converter (adc) 22.2 control page 362 2012/5/18 ra002
ad converter control register 1 adccr1 7 6 5 4 3 2 1 0 (0x00034) bit symbol adrs amd ainen sain read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 adrs ad conversion start 0: 1: - ad conversion start amd ad operating mode 00: 01: 10: 11: ad operation disable, forcibly stop ad operation single mode reserved repeat mode ainen analog input control 0: 1: analog input disable analog input enable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved note 1: do not perform the following operations on the adccr1 register while ad conversion is being executed (adccr2="1"). - changing sain - setting ainen to "0" - changing amd (except a forced stop by setting amd to "00") - setting adrs to "1" note 2: if you want to disable all analog input channels, set ainen to "0". note 3: although analog input pins are also used as input/output ports, it is recommended for the purpose of maintaining the ac- curacy of ad conversion that you do not execute input/output instructions during ad conversion. additionally, do not in- put widely varying signals into the ports adjacent to analog input pins. note 4: when stop, idle0 or slow mode is started, adrs, amd and ainen are initialized to "0". if you use the ad convert- er after returning to normal mode, you must reconfigure adrs, amd and ainen. note 5: after adrs is set to "1", it is automatically cleared to "0". the time between when adrs is set to "1" and when it is cleared to "0" is a maximum of 4/fcgck [s] when adccr2="00*", a maximum of 15/fcgck [s] when adccr2="01*", and a maximum of 52/fcgck [s] when adccr2="10*". tmp89fw20a page 363 2012/5/18 ra002
ad converter control register 2 adccr2 7 6 5 4 3 2 1 0 (0x00035) bit symbol eocf adbf - - "0" ack read/write r r r r w r/w after reset 0 0 0 0 0 0 0 0 eocf ad conversion end flag 0: 1: before conversion or during conversion conversion end adbf ad conversion busy flag 0: 1: ad conversion being halted ad conversion being executed ack ad conversion time select (exam- ples of ad conversion time are shown in the table below) 000: 001: 010: 011: 100: 101: 110: 111: 39/fcgck 78/fcgck 156/fcgck 312/fcgck 624/fcgck 1248/fcgck reserved reserved note 1: make sure that you make the ack setting when ad conversion is in a halt condition (adccr2="0"). note 2: make sure that you write "0" to bit 3 of adccr2. note 3: if stop, idle0 or slow mode is started, eocf and adbf are initialized to "0". note 4: if the ad converted value register (adcdrh) is read, eocf is cleared to "0". it is also cleared to "0" if ad conver- sion is started (adccr1="1") without reading adcdrh after completing ad conversion in single mode. note 5: if an instruction to read adccr2 is executed, 0 is read from bits 3 through 5. table 22-1 ack settings and conversion times relative to frequencies frequency (fcgck) ack setting conversion time 10mhz 8mhz 5mhz 4mhz 2.5mhz 2mhz 1mhz 0.5mhz 0.25 mhz 000 39/fcgck - - - - 15.6 s 19.5 s 39.0 s 78.0 s 156.0 s 001 78/fcgck - - 15.6 s 19.5 s 31.2 s 39.0 s 78.0 s 156.0 s - 010 156/fcgck 15.6 s 19.5 s 31.2 s 39.0 s 62.4 s 78.0 s 156.0 s - - 011 312/fcgck 31.2 s 39.0 s 62.4 s 78.0 s 124.8 s 156.0 s - - - 100 624/fcgck 62.4 s 78.0 s 124.8 s 156.0 s - - - - - 101 1248/fcgck 124.8 s 156.0 s - - - - - - - 11* reserved note 1: spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces. fcgck: high frequency oscillation clock [hz] note 2: above conversion times do not include the time shown below. - time from when adccr1 is set to 1 to when ad conversion is started - time from when ad conversion is finished to when a converted value is stored in adcdrl and adcdrh. if ack = 00*, the longest conversion time is 10/fcgck (s). if ack = 01*, it is 32/fcgck (s). if ack = 10*, it is 128/fcgck (s). note 3: the conversion time must be longer than the following time by analog reference voltage (varef). - varef = 4.5 to 5.5 v 15.6 s or longer - varef = 2.7 to 5.5 v 31.2 s or longer - varef = 2.2 to 5.5 v 124.8 s or longer tmp89fw20a 22. 10-bit ad converter (adc) 22.2 control page 364 2012/5/18 ra002
ad converted value register (lower side) adcdrl 7 6 5 4 3 2 1 0 (0x00036) bit symbol ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 ad converted value register (upper side) adcdrh 7 6 5 4 3 2 1 0 (0x00037) bit symbol - - - - - - ad09 ad08 read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 note 1: a read of adcdrl or adcdrh must be read after the intadc interrupt is generated or after adccr2 be- comes "1". note 2: in single mode, do not read adcdrl or adcdrh during ad conversion (adccr2="1"). (if ad conversion is finished in the interim between a read of adcdrl and a read of adcdrh, the intadc interrupt request is can- celed, and the conversion result is lost.) note 3: if stop, idle0 or slow mode is started, adcdrl and adcdrh are initialized to "0". note 4: if adccr1 is set to "00", adcdrl and adcdrh are initialized to "0". note 5: if an instruction to read adcdrh is executed, "0" is read from bits 7 through 2. note 6: if ad conversion is finished in repeat mode in the interim between a read of adcdrl and a read of adcdrh, the pre- vious converted value is retained without overwriting the ad converted value register. in this case, the intadc inter- rupt request is canceled, and the conversion result is lost. tmp89fw20a page 365 2012/5/18 ra002
22.3 functions the 10-bit ad converter operates in either single mode in which ad conversion is performed only once or re- peat mode in which ad conversion is performed repeatedly. 22.3.1 single mode in single mode, the voltage at a designated analog input pin is ad converted only once. setting adccr1 to "1" after setting adccr1 to "01" allows ad conversion to start. adccr1 is automatically cleared after the start of ad conversion. as ad conversion starts, adccr2 is set to "1". it is cleared to "0" if ad conversion is finished or if ad conversion is forced to stop. after ad conversion is finished, the conversion result is stored in the ad converted value registers (adcdrl and adcdrh), adccr2 is set to "1", and the ad conversion finished interrupt (in- tadc) is generated. the ad converted value registers (adcdrl and adcdrh) should be usually read ac- cording to the intadc interrupt processing routine. if the upper side (adcdrh) of the ad converted val- ue register is read, adccr2 is cleared to "0". note:do not perform the following operations on the adccr1 register when ad conversion is being execu- ted (adccr2="1"). if the following operations are performed, there is the possibility that ad conversion may not be executed properly. ? changing the adccr1 setting ? setting adccr1 to "0" ? changing the adccr1 setting (except a forced stop by setting amd to "00") ? setting adccr1 to "1" figure 22-2 single mode 22.3.2 repeat mode in repeat mode, the voltage at an analog input pin designated at adccr1 is ad converted repeat- edly. setting adccr1 to "1" after setting adccr1 to "11" allows ad conversion to start. af- ter the start of ad conversion, adccr1 is automatically cleared. after the first ad conversion is fin- ished, the conversion result is stored in the ad converted value registers (adcdrl and adcdrh), adccr2 is set to "1", and the ad conversion finished interrupt (intadc) is generated. after this interrupt is generated, the second (next) ad conversion starts immediately. tmp89fw20a 22. 10-bit ad converter (adc) 22.3 functions page 366 2012/5/18 ra002 status of adcdrl and adcdrh clearing eocf based on the conversion result read of conversion result read of conversion result read of conversion result read of conversion result adccr2 intadc interrupt request adccr2 adccr1 result of the first conversion result of the second conversion indeterminate ad conversion start ad conversion start read of adcdrh read of adcdrl
the ad converted value registers (adcdrl and addrh) should be read before the next ad conversion is finished. if the next ad conversion is finished in the interim between a read of adcdrl and a read of adcdrh, the previous converted value is retained without overwriting the ad converted value registers (adcdrl and adcdrh). in this case, the intadc interrupt request is not generated, and the conversion re- sult is lost. (see figure 22-3.) to stop ad conversion, write "00" (ad operation disable) to adccr1. as "00" is written to adccr1, ad conversion stops immediately. in this case, the converted value is not stored in the ad converted value register. as ad conversion starts, adccr2 is set to "1". it is cleared to "0" if "00" is written to amd. figure 22-3 repeat mode 22.3.3 ad operation disable and forced stop of ad operation if you want to force the ad converter to stop when ad conversion is ongoing in single mode or if you want to stop the ad converter when ad conversion is ongoing in repeat mode, set adccr1 to "00". if adccr1 is set to "00", registers adccr2, adccr2, adcdrl, and adcdrh are initialized to "0". tmp89fw20a page 367 2012/5/18 ra002 status of adcdrl and adcdrh a read of the conversion result will clear eocf. the intadc interrupt request is not generated in the interim between a read of adcdrl and a read of adcdrh. read of conversion result read of conversion result a dccr2 intadc interrupt conversion operation a dccr1 ad conversion start adccr1 ?11? ?00? ad conversion is suspended. the conversion result is not stored. read of adcdrh read of adcdrl read of conversion result read of conversion result read of conversion result read of conversion result indeterminate result of the 1st conversion result of the 2nd conversion result of the 3rd conversion result of the 4th conversion result of the 4th conversion result of the 3rd conversion
22.4 register setting 1. set the ad converter control register 1 (adccr1) as described below: ? from the ad input channel select (sain), select the channel in which ad conversion is to be per- formed. ? set the analog input control (ainen) to "analog input enable". ? at amd, specify the ad operating mode (single or repeat mode). 2. set the ad converter control register 2 (adccr2) as described below: ? at the ad conversion time (ack), specify the ad conversion time. for information on how to spec- ify the conversion time, refer to the ad converter control register 2 and table 22-1. 3. after the above two steps are completed, set "1" on the ad conversion start (adrs) of the ad convert- er control register 1 (adccr1), and ad conversion starts immediately if single mode is selected. 4. as ad conversion is finished, the ad conversion end flag (eocf) of the ad converter control register 2 (adccr2) is set to "1", the ad conversion result is stored in the ad converted value registers (adcdrh and adcdrl), and the intadc interrupt request is generated. 5. after the conversion result is read from the ad converted value register (adcdrh), eocf is cleared to "0". eocf will also be cleared to "0" if ad conversion is performed once again before reading the ad con- verted value register (adcdrh). in this case, the previous conversion result is retained until ad conver- sion is finished. example: after selecting the conversion time 15.6 s at 10 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, store the conversion result in the hl register. the operation mode is sin- gle mode. : (port setting) ;before setting ad converter registers, make an appropriate port ;register setting.(for further details, refer to the section that describes ;i/o ports.) ld (adccr1), 0y00110011 ;select ain3 and operation mode ld (adccr2), 0y00000010 ;select conversion time (156/fcgck) set (adccr1). 7 ;adrs = 1 (ad conversion start) sloop : test (adccr2). 7 ;eocf = 1 ? j t, code_addr(sloop) ld hl, (adcdrl) ;read result data 22.5 starting stop/idle0/slow modes if stop/idle0/slow mode is started, registers adccr1, adccr2, adcdrl and adcdrh are initialized to "0". if any of these modes is started during ad conversion, ad conversion is suspended, and the ad converter stops (registers are likewise initialized). when restored from stop/ idle0/slow mode, ad conversion is not automatically restarted. therefore, registers must be reconfig- ured as necessary. if stop/idle0/slow mode is started during ad conversion, analog reference voltage is automatically discon- nected and, therefore, there is no possibility of current flowing into the analog reference voltage. tmp89fw20a 22. 10-bit ad converter (adc) 22.4 register setting page 368 2012/5/18 ra002
22.6 analog input voltage and ad conversion result analog input voltages correspond to ad-converted, 10-bit digital values, as shown in figure 22-4. figure 22-4 relationships between analog input voltages and ad-converted values (typical values) tmp89fw20a page 369 2012/5/18 ra002 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad-converted value varef ? avss
22.7 precautions about the ad converter 22.7.1 analog input pin voltage range analog input pins (ain0 through ain7) should be used at voltages from varef to vss. if any voltage out- side this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain, and converted values on other pins will also be affected. 22.7.2 analog input pins used as input/output ports analog input pins (ain0 to ain7) are also used as input/output ports. in using one of analog input pins (ports) to execute ad conversion, input/output instructions at all other pins (ports) must not be executed. if they are executed, there is the possibility that the accuracy of ad conversion may deteriorate. this also ap- plies to pins other than analog input pins; if one pin receives inputs or generates outputs, noise may occur and its adjacent pins may be affected by that noise. 22.7.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 22-5. the higher the output impe- dance of the analog input source, the more susceptible it becomes to noise. therefore, make sure the output im- pedance of the signal source in your design is 5 k or less. it is recommended that a capacitor be attached ex- ternally. figure 22-5 analog input equivalent circuit and example of input pin processing tmp89fw20a 22. 10-bit ad converter (adc) 22.7 precautions about the ad converter page 370 2012/5/18 ra002 da converter analog comparator r nal resistance: r nal capacitance: #!undefined!# k (typ) da converter aini analog comparator internal resistance: permissible signal source impedance: internal capacitance: 5 k ? (typ) 5 k ? (max) note) i = 7 to 0 c = 22 pf (typ.)
23. lcd driver the tmp89fw20a has a driver and control circuit to directly drive a liquid crystal display (lcd) device. the pins to be connected to the lcd are as follows: 1. segment output pins : 32 pins (seg31 to seg0) 2. common output pins : 4 pins (com3 to com0) in addition, the vlc pin is provided as a drive power supply pin, and the lv1 and lv2 pins are provided as ex- ternal bleeder resistance connection pins. note 1: the external bleeder resistance connection pins lv1 and lv2 are shared with the segment output pins seg30,31. when external bleeder resistance is used, seg30,31 cannot be used for segment output. note 2: when the static, 1/3 or 1/2 duties are selected, unused common output pins should be opened. (it outputs bias voltage) the lcd driver can directly drive the following five types of lcd: 1. 1/4 duty (1/3 bias) lcd max. 128 pixels (8 segments 16 digits) 2. 1/3 duty (1/3 bias) lcd max. 96 pixels (8 segments 12 digits) 3. 1/3 duty (1/2 bias) lcd max. 96 pixels (8 segments 12 digits) 4. 1/2 duty (1/2 bias) lcd max. 64 pixels (8 segments 8 digits) 5. static lcd max. 32 pixels (8 segments 4 digits) tmp89fw20a page 371 2012/5/18 ra000
23.1 configuration figure 23-1 lcd driver tmp89fw20a 23. lcd driver 23.1 configuration page 372 2012/5/18 ra000 com3 seg0 com0 vlc duty control common driver lcd display data area display data select control timing control display data buffer register segment driver lcdcr1 to to edsp duty slf lcd driver control register 1 lcdcr2 syscr2 syscr2 lcd driver control register 2 7 6 5 4 3 2 1 0 vss lrse low resistance timing control high resistance low resistance brh brsel 7 6 5 4 3 2 1 0 vm2 vm1 1/2 bias vm1 vm2 300k 200k 20k v1 v2 fs fcgck syscr2 poffcr2 seg31
23.2 control the lcd driver is controlled by the low power consumption register (poffcr2), lcd control register 1 (lcdcr1), and lcd control register 2 (lcdcr2). low power consumption register 2 poffcr2 7 6 5 4 3 2 1 0 (0x00f76) bit symbol lcden - rtcen - - - sio1en sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 lcden lcd control 0 1 disable enable rtcen rtc control 0 1 disable enable sio1en sio1 control 0 1 disable enable sio0en sio0 control 0 1 disable enable tmp89fw20a page 373 2012/5/18 ra000
lcd driver control register 1 lcdcr1 7 6 5 4 3 2 1 0 (0x00e7c) bit symbol edsp duty slf read/write r/w r/w r/w after reset 0 0 0 0 0 0 0 0 edsp lcd display control 0 1 blank lcd display enable lcd display duty lcd drive method selection 000 1/4 duty (1/3 bias) 001 1/3 duty (1/3 bias) 010 1/3 duty (1/2 bias) 011 1/2 duty (1/2 bias) 100 static 101 reserved 110 reserved 111 reserved slf base frequency selection 0000 fcgck/2 18 0001 fcgck/2 17 0010 fcgck/2 16 0011 fcgck/2 15 0100 fcgck/2 14 0101 fcgck/2 13 0110 fcgck/2 12 0111 reserved 1000 fs/2 9 1001 fs/2 8 1010 reserved to 1111 reserved note 1: fcgck = gear clock [hz], fs = low-frequency clock [hz] note 2: in slow2 mode, do not set slf to 0y0000 to 0y0110 (i.e. frequencies based on fcgck). if slf is set to one of these frequencies, pulses of an unexpected frame frequency will be output from the common and segment output pins. tmp89fw20a 23. lcd driver 23.2 control page 374 2012/5/18 ra000
lcd driver control register 2 lcdcr2 7 6 5 4 3 2 1 0 (0x00e7d) bit symbol lrse brh brsel read/write r/w r/w r/w r r r after reset 0 0 0 0 0 0 0 0 lrse low internal bleeder resistance connection time selection lcdcr1 setting 0000 0001 0010 0011 0100 0101 0110 1000 1001 000 not connected 001 2 11/ fcgck 2 10/ fcgck 2 9/ fcgck 2 8/ fcgck 2 7/ fcgck 2 6/ fcgck 2 5/ fcgck 2 2/ fs 2/fs 010 2 12/ fcgck 2 11/ fcgck 2 10/ fcgck 2 9/ fcgck 2 8/ fcgck 2 7/ fcgck 2 6/ fcgck 2 3/ fs 2 2/ fs 011 2 13/ fcgck 2 12/ fcgck 2 11/ fcgck 2 10/ fcgck 2 9/ fcgck 2 8/ fcgck 2 7/ fcgck 2 4/ fs 2 3/ fs 100 2 14/ fcgck 2 13/ fcgck 2 12/ fcgck 2 11/ fcgck 2 10/ fcgck 2 9/ fcgck 2 8/ fcgck 2 5/ fs 2 4/ fs 101 2 15/ fcgck 2 14/ fcgck 2 13/ fcgck 2 12/ fcgck 2 11/ fcgck 2 10/ fcgck 2 9/ fcgck 2 6/ fs 2 5/ fs 110 always connected 111 reserved brh high internal bleeder resistance selection 0 200 k (typ.) 1 500 k (typ.) brsel internal/external bleeder resist- ance switching control 0 use external bleeder resistance (note 4) 1 use internal bleeder resistance note 1: fcgck = gear clock [hz], fs = low-frequency clock [hz] note 2: the lrse and brh settings are effective only when brsel is set to select internal bleeder resistance. note 3: when a read instruction is executed on lcdcr2, bits 2 to 0 are read as "0". note 4: the external bleeder resistance connection pins are shared with the segment output pins seg30,31. when external bleeder resistance is used, seg30,31 cannot be used for segment output. tmp89fw20a page 375 2012/5/18 ra000
23.3 low power consumption function the lcd driver has the low power consumption register (poffcr2) to reduce unnecessary power consump- tion when the display function is not used. setting poffcr2 to "0" disables the basic clock supply to the lcd driver to reduce unnecessary pow- er consumption. the lcd driver cannot be used in this state. setting poffcr2 to "1" enables the ba- sic clock supply to the lcd driver, allowing the lcd driver to be used. after a reset, poffcr2 is initialized to "0", disabling the lcd driver. therefore, to use the lcd driv- er, be sure to set poffcr2 to "1" in the initialization part of the program (before setting the lcd driv- er control registers). do not change poffcr2 to "0" while the lcd driver is operating. doing so may cause the lcd driv- er to behave in an unexpected manner. tmp89fw20a 23. lcd driver 23.3 low power consumption function page 376 2012/5/18 ra000
23.4 functions 23.4.1 lcd display control (lcdcr1) when lcdcr1 is set to "1", the power switch of the lcd driver is turned on and vlc voltage is applied to the lcd driver, enabling the display function. setting lcdcr1 to "0" turns off the pow- er switch of the lcd driver and shuts off vlc voltage, blanking the display. table 23-1 shows the pin states when the display is enabled and when the display is blank. table 23-1 pin states pxlcr lcdcr2 lcdcr1 common output pins multiplexed pins (input/output port ) (segment output) multiplexed pins (input/output port) (segment output) (external bleeder resist- ance connection) 0 0 0 l level input/output port external bleeder resist- ance connection 0 0 1 common output 0 1 0 l level input/output port 0 1 1 common output 1 0 0 l level l level external bleeder resist- ance connection 1 0 1 common output segment output 1 1 0 l level l level l level 1 1 1 common output segment output segment output note:"x" denotes an i/o port number. 23.4.1.1 operation at reset when a reset occurs, lcdcr1 is initialized to "0" and the power switch of the lcd driver is au- tomatically turned off, shutting off vlc voltage. at this time, the common output pins are fixed to the l lev- el. the multiplexed pins (input/output port or segment output) are configured as port input pins (high impe- dance). therefore, if external reset operation takes time, the lcd display may become blurred. the multi- plexed pins (input/output port, external bleeder resistance connection or segment output) are configured as external bleeder resistance connection pins. 23.4.1.2 operation in idle0, sleep0 and stop modes when idle0, sleep0 or stop mode is activated while lcdcr1 is set to "1", lcdcr1 is automatically initialized to "0", blanking the lcd display. after idle0, sleep0 or stop mode is exited, lcdcr1 must be set to "1" to re-enable the lcd display. 23.4.1.3 operation in slow mode when the lcd is used in both normal2 mode and slow1/2 mode, it is recommended that lcdcr1 be set to a frequency based on fs (0y1000 or 0y1001). (this will eliminate the need for changing the lcdcr1 setting each time the operating mode is switched between normal2 mode and slow1/2 mode. ) if a frequency based on fcgck is used in normal 2 mode, it is necessary to clear lcdcr1 to "0" before switching to slow2 mode. then, after entering slow2 mode, it is necessary to change lcdcr1 to a frequency based on fs and to set lcdcr1 to "1". likewise, in switching tmp89fw20a page 377 2012/5/18 ra000
from slow2 mode to normal2 mode, it is necessary to clear lcdcr1 to "0" before switch- ing to normal2 mode. then, after entering normal2 mode, it is necessary to change lcdcr1 to a frequency based on fcgck and to set lcdcr1 to "1". 23.4.1.4 display operation according to the base frequency setting (lcdcr1) (fail-safe) when lcdcr1 is set to 0y0000 to 0y0110, the high-frequency clock must be activated (syscr2="1" or syscr2="1") and allowed to achieve stable oscillation before lcdcr1 can be set to "1". if lcdcr1 is set to "1" while the high-frequency clock is stop- ped, the lcd display cannot be enabled. (although lcdcr1 changes to "1", the lcd display re- mains blank.) likewise, when lcdcr1 is set to 0y1000 to 0y1001, the low-frequency clock must be activa- ted (syscr2="1") and allowed to achieve stable oscillation before lcdcr1 can be set to "1". if lcdcr1 is set to "1" while the low-frequency clock is stopped, the lcd display can- not be enabled. (although lcdcr1 changes to "1", the lcd display remains blank.) 23.4.1.5 display operation according to the low power consumption register (fail-safe) when lcdcr1="1", setting poffcr2 to "0" blanks the lcd display. the display can be re-enabled by setting poffcr2 to "1". tmp89fw20a 23. lcd driver 23.4 functions page 378 2012/5/18 ra000
23.4.2 lcd drive methods (lcdcr1) the lcd drive method can be selected from the following five types by the setting of lcdcr1. note 1: f f = frame frequency note 2: f b = base frequency (lcdcr1) note 3: v lcd3 = lcd drive voltage ( = v lc ? v ss ) figure 23-2 lcd drive waveforms (potential difference between com and seg pins) tmp89fw20a page 379 2012/5/18 ra000 data "0" data "1" v lcd ? v lcd 1/f f v lcd ? v lcd 1/f b 1/f b 1/f b 1/f f 1/f f data "1" data "0" 0 ? v lcd 0 (b) 1/3 duty (1/3 bias) v lcd 0 (c) 1/3 duty (1/2 bias) (a) 1/4 duty (1/3 bias) (e) static (d) 1/2 duty (1/2 bias) 1/f b 1/f b 1/f f data "1" data "0" data "1" data "0" data "1" data "0" ? v lcd v lcd 0 ? v lcd v lcd 0 1/f f
23.4.3 frame frequency (lcdcr1) the frame frequency (f f ) is determined based on the drive method and base frequency, as shown in table 23-2. the base frequency is selected by lcdcr1. table 23-2 frame frequency settings slf base frequency [hz] frame frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 0000 fcgck / 2 18 fcgck / 2 18 ( 4 / 3 ) x fcgck / 2 18 ( 4 / 2 ) x fcgck / 2 18 fcgck / 2 18 (fcgck = 16 mhz) 61 81 122 61 0001 fcgck / 2 17 fcgck / 2 17 ( 4 / 3 ) x fcgck / 2 17 ( 4 / 2 ) x fcgck / 2 17 fcgck / 2 17 (fcgck = 16 mhz) 122 163 244 122 (fcgck = 8 mhz) 61 81 122 61 0010 fcgck / 2 16 fcgck / 2 16 ( 4 / 3 ) x fcgck / 2 16 ( 4 / 2 ) x fcgck / 2 16 fcgck / 2 16 (fcgck = 8 mhz) 122 163 244 122 (fcgck = 4 mhz) 61 81 122 61 0011 fcgck / 2 15 fcgck / 2 15 ( 4 / 3 ) x fcgck / 2 15 ( 4 / 2 ) x fcgck / 2 15 fcgck / 2 15 (fcgck = 4 mhz) 122 163 244 122 (fcgck = 2 mhz) 61 81 122 61 0100 fcgck / 2 14 fcgck / 2 14 ( 4 / 3 ) x fcgck / 2 14 ( 4 / 2 ) x fcgck / 2 14 fcgck / 2 14 (fcgck = 2 mhz) 122 163 244 122 (fcgck = 1 mhz) 61 81 122 61 0101 fcgck / 2 13 fcgck / 2 13 ( 4 / 3 ) x fcgck / 2 13 ( 4 / 2 ) x fcgck / 2 13 fcgck / 2 13 (fcgck = 1 mhz) 122 163 244 122 (fcgck = 0.5 mhz) 61 81 122 61 0110 fcgck / 2 12 fcgck / 2 12 ( 4 / 3 ) x fcgck / 2 12 ( 4 / 2 ) x fcgck / 2 12 fcgck / 2 12 (fcgck = 0.5 mhz) 122 163 244 122 (fcgck = 0.25 mhz) 61 81 122 61 1000 fs / 2 9 fs / 2 9 ( 4 / 3 ) x fs / 2 9 ( 4 / 2 ) x fs / 2 9 fs / 2 9 (fs = 32.768 khz) 64 85 128 64 1001 fs / 2 8 fs / 2 8 ( 4 / 3 ) x fs / 2 8 ( 4 / 2 ) x fs / 2 8 fs / 2 8 (fs = 32.768 khz) 128 171 256 128 note:fcgck = gear clock frequency [hz], fs = low-frequency clock frequency [hz] tmp89fw20a 23. lcd driver 23.4 functions page 380 2012/5/18 ra000
23.4.4 internal/external bleeder resistance switching control the lcd bias voltage is generated by bleeder resistance. either external or internal bleeder resistance can be used. to use internal bleeder resistance, set lcdcr2 to "1". in this case, the multiplexed pins (input/out- put port, external bleeder resistance connection or segment output) can be configured as input/output ports or segment output pins. to use external bleeder resistance, set lcdcr2 to "0" and connect external resistance to the ex- ternal bleeder resistance connection pins (v1, v2). in this case, the multiplexed pins (input/output port, exter- nal bleeder resistance connection, or segment output) can only be used as external bleeder resistance connec- tion pins. see figure 23-4 for how to connect bleeder resistance. 23.4.5 low internal bleeder resistance connection time selection (lcdcr2) internal bleeder resistance is comprised of two parts: high resistance and low resistance. the high and low resistance parts are connected in parallel for each bias voltage. the low bleeder resistance is provided with an analog switch, and the time to turn on the low bleeder resistance can be adjusted by lcdcr2. while the analog switch is turned on, the low resistance is connected in parallel to the high resistance. this re- duces the total amount of resistance, allowing the drive capability of the lcd driver to be increased. typically, the longer the period of connecting the low resistance, the higher the drive capability of the lcd panel, but the higher the power consumption. conversely, the shorter the period of connecting the low re- sistance, the lower the drive capability, but the lower the power consumption. insufficient drive capability will cause adverse effects on the lcd display, such as blurring. choose the optimum drive capability for the lcd panel to be used. table 23-3 shows the connection time (percentage) of the low bleeder resistance per frame and the estima- ted amount of current that flows through the entire bleeder resistance in each case. figure 23-3 shows the bleeder resistance control timing for the 1/4 duty and 1/3 bias lcd. see "23.4.6 high internal bleeder resistance selection (lcdcr2)"for the setting of lcdcr2. tmp89fw20a page 381 2012/5/18 ra000
table 23-3 low bleeder resistance connection time (%) and total bleeder current values (estimated) lcdcr2 1/4 duty (1/3 bias) 1/3 duty (1/3 bias) 1/3 duty (1/2 bias) 1/2 duty (1/2 bias) brh="1" brh="0" brh="1" brh="0" brh="1" brh="0" brh="1" brh="0" 000 low resistance connection time (%) 0% (always high resistance) bleeder current vlc=5v 3.33a 8.33a 3.33a 8.33a 5.00a 12.5a 5.00a 12.5a vlc=3v 2.00a 5.00a 2.00a 5.00a 3.00a 7.50a 3.00a 7.50a 001 low resistance connection time (%) 3.13% bleeder current vlc=5v 5.94a 10.94a 5.94a 10.94a 8.91a 16.41a 8.91a 16.41a vlc=3v 3.56a 6.56a 3.56a 6.56a 5.34a 9.84a 5.34a 9.84a 010 low resistance connection time (%) 6.25% bleeder current vlc=5v 8.54a 13.54a 8.54a 13.54a 12.81a 20.31a 12.81a 20.31a vlc=3v 5.13a 8.13a 5.13a 8.13a 7.69a 12.19a 7.69a 12.19a 011 low resistance connection time (%) 12.5% bleeder current vlc=5v 13.75a 18.75a 13.75a 18.75a 20.63a 28.13a 20.63a 28.13a vlc=3v 8.25a 11.25a 8.25a 11.25a 12.38a 16.88a 12.38a 16.88a 100 low resistance connection time (%) 25% bleeder current vlc=5v 24.17a 29.17a 24.17a 29.17a 36.25a 43.75a 36.25a 43.75a vlc=3v 14.50a 17.50a 14.50a 17.50a 21.75a 26.25a 21.75a 26.25a 101 low resistance connection time (%) 50% bleeder current vlc=5v 45.00a 50.00a 45.00a 50.00a 67.50a 75.00a 67.50a 75.00a vlc=3v 27.00a 30.00a 27.00a 30.00a 40.50a 45.00a 40.50a 45.00a 110 low resistance connection time (%) 100% (always connected) bleeder current vlc=5v 86.67a 91.67a 86.67a 91.67a 130.0a 137.5a 130.0a 137.5a vlc=3v 52.00a 55.00a 52.00a 55.00a 78.00a 82.50a 78.00a 82.50a note:the bleeder resistance current values shown above are estimated values. the actual current values may vary depending on the amount of lcd load and manufacturing variations in resistance values. tmp89fw20a 23. lcd driver 23.4 functions page 382 2012/5/18 ra000
figure 23-3 bleeder resistance selection by lcdcr2 (1/4 duty, 1/3 bias) tmp89fw20a page 383 2012/5/18 ra000 vlcd vm1 vm2 vss frame frequency r lt r lt : r ht : r lt r lt r lt r lt lcdcr = 0y101 r ht r ht r ht r ht r ht lcdcr = 0y000 r lt r ht r lt r ht r lt r ht r lt r ht r lt r ht lcdcr = 0y001, 0y010, 0y011 or 0y100 low bleeder resistance connection time period during which low resistance is connected (high resistance and low resistance are connected in parallel) period during which low resistance is not connected (only high resistance is connected)
23.4.6 high internal bleeder resistance selection (lcdcr2) the value of high internal bleeder resistance can be selected from two levels (500 k (typ.) or 200 k (typ.)) by the setting of lcdcr2. typically, the lower the resistance value, the higher the drive capa- bility of the lcd panel, but the higher the power consumption. conversely, the higher the resistance value, the lower the drive capability, but the lower the power consumption. the resistance value of the low resistance is fixed to 20 k (typ.). since the low resistance is connected in parallel to the high resistance via an analog switch, the total amount of resistance can be adjusted by the set- ting of lcdcr2 as shown in table 23-4. for example, setting lcdcr2 to "1" selects a synthesized resistance of 19.23 k (typ.) when the low resistance is connected, and a high resistance of 500 k (typ.) when the low resistance is not connected. table 23-4 bleeder resistance values lcdcr2 when low resistance is not connected when low resistance is connected 1 500 k (typ.) 19.23 k (typ.) 0 200 k (typ.) 18.18 k (typ.) tmp89fw20a 23. lcd driver 23.4 functions page 384 2012/5/18 ra000
23.5 lcd display operation the lcd drive voltage v lcd is given by the potential difference between the vlc and vss pins (v lc ? v ss ). the lcd lights up when the potential difference between segment and common outputs is vl cd. at other times, the lcd is turned off. power supply connections should be made to satisfy the condition vlc vdd. connection examples are shown in figure 23-4. figure 23-4 connection examples note 1: when the cpu operating voltage is the same as the lcd drive voltage, the vlc pin should be connected to the vdd pin. note 2: at reset, the common output pins become low. however, the multiplexed pins (input/output port or segment output) are configured as port input pins (high impedance). therefore, if the multiplexed pins (input/output port or segment out- put) are used as segment output pins and an external reset signal is input for a prolonged period of time, the lcd dis- play may be adversely affected, such as blurring. the multiplexed pins (input/output port, external bleeder resistance connection or segment output) are configured as external bleeder resistance connection pins. tmp89fw20a page 385 2012/5/18 ra000 vdd contrast adjustment (b) vdd = vlc (a) vdd > vlc when internal bleeder resistance is used (lcdcr2=?1?) vdd vlc lv2 lv1 vss vdd vlc v1 v2 vss seg com lcd panel mcu vdd seg com lcd panel mcu vdd vlc lv2 lv1 vss vdd *1 *2 *3 *1 *2 *3 contrast adjustment (b) vdd = vlc *1 : 1/3 bias *2 : 1/2 bias *3 : static (a) vdd > vlc when external bleeder resistance is used (lcdcr2=?0?) vdd vlc lv2 lv1 vss vdd vlc v1 v2 vss seg com lcd panel mcu vdd seg com lcd panel mcu vdd vlc lv2 lv1 vss can also be used as port pins or segment output can also be used as port pins or segment output
23.6 display data setting display data is stored in the display data area (16 bytes at addresses 0x00e40 to 0x00e4f). the display data stored in the display data area is automatically read out and sent to the lcd driver by hard- ware. the lcd driver generates the segment and common signals according to the display data and drive meth- od. therefore, display patterns can be changed by simply overwriting the contents of the display data area.table 23-6 shows the correspondence between the display data area and the seg and com pins. the lcd lights up when display data is "1" and is turned off when display data is "0". at reset, the data in the display data area (16 bytes at addresses 0x00e40 to 0x00e4f) are initialized to "0". since the number of pixels that can be driven varies with the lcd drive method, the number of bits used for stor- ing display data also varies accordingly. therefore, the bits not used for storing display data and the data memory locations corresponding to addresses not connected to the lcd can be used for storing general user data (see ta- ble 23-5). table 23-5 bits to be used for storing display data drive method bits 7/3 bits 6/2 bits 5/1 bits 4/0 1/4 duty com3 com2 com1 com0 1/3 duty - com2 com1 com0 1/2 duty - - com1 com0 static - - - com0 note:" - " denotes bits not used for storing display data. table 23-6 lcd display data area registar name (address) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/ write initial value lcdbuf00 (0x00e40) seg1 seg0 r/w (0000 0000) lcdbuf01 (0x00e41) seg3 seg2 r/w (0000 0000) lcdbuf02 (0x00e42) seg5 seg4 r/w (0000 0000) lcdbuf03 (0x00e43) seg7 seg6 r/w (0000 0000) lcdbuf04 (0x00e44) seg9 seg8 r/w (0000 0000) lcdbuf05 (0x00e45) seg11 seg10 r/w (0000 0000) lcdbuf06 (0x00e46) seg13 seg12 r/w (0000 0000) lcdbuf07 (0x00e47) seg15 seg14 r/w (0000 0000) lcdbuf08 (0x00e48) seg17 seg16 r/w (0000 0000) lcdbuf09 (0x00e49) seg19 seg18 r/w (0000 0000) lcdbuf10 (0x00e4a) seg21 seg20 r/w (0000 0000) lcdbuf11 (0x00e4b) seg23 seg22 r/w (0000 0000) lcdbuf12 (0x00e4c) seg25 seg24 r/w (0000 0000) lcdbuf13 (0x00e4d) seg27 seg26 r/w (0000 0000) lcdbuf14 (0x00e4e) seg29 seg28 r/w (0000 0000) lcdbuf15 (0x00e4f) seg31 seg30 r/w (0000 0000) com3 com2 com1 com0 com3 com2 com1 com0 tmp89fw20a 23. lcd driver 23.6 display data setting page 386 2012/5/18 ra000
23.7 examples of how to control the lcd driver 23.7.1 initialization figure 23-5 is a flowchart showing the initialization process of the lcd driver. example: when the lcd driver is to be operated with the following conditions: - drive method: 1/4 duty, 1/3 bias - lcd frame frequency: fcgck/2 18 [hz] - connection time of low bleeder resistance (internal): 2 15 /fcgck - high bleeder resistance (internal): 200 k ld (poffcr2),0x80 ; lcden = 1 ld (lcdcr1),0x00 ; set the lcd drive method and base frequency ld (lcdcr2),0x28 ; set the connection time of low bleeder resistance and the ; high bleeder resistance value ld (pxlcr),0xff ; set the pxlcr register (x: i/o port number) : : : : ; set initial display data set (lcdcr1).7 ; enable the lcd display figure 23-5 flowchart for the lcd driver initialization 23.7.2 display data setting display data is normally prepared as fixed data in the program memory (rom) and transferred to the dis- play data area by instructions. example: the following shows an example of how to set display data for displaying a number corre- sponding to bcd data stored at address 0x90 in the data memory by using the 1/4 duty and 1/3 bias lcd. figure 23-6 shows an example of how the com and seg pins are connected to the lcd, and table 23-7 shows how display data is set for this example. tmp89fw20a page 387 2012/5/18 ra000 set lcd drive method (duty) set base frequency (slf) set bleeder resistance on time (lrse) select high bleeder resistance (brh) internal / external bleeder resistance switching control (brsel) set pxlcr register (x; i/o port number) initialize display data area enable lcd display (edsp)
lcdctl section code abs = 0x1f000 slcdmain: ld c,(0x90) ld hl,stable ld a,(hl+c) ld (0x0e40),a ret lcddata section romdata abs = 0xf800 stable: db 0y11011111, 0y00000110, 0y11100011, 0y10100111, 0y00110110, 0y10110101, 0y11110101, 0y00010111, 0y11110111, 0y10110111 note:"db" denotes a byte data definition instruction. figure 23-6 example of com and seg pin connections (1/4 duty) table 23-7 example of display data (1/4 duty) no. display display data no. display display data 0 11011111 5 10110101 1 00000110 6 11110101 2 11100011 7 00000111 3 10100111 8 11110111 4 00110110 9 10110111 tmp89fw20a 23. lcd driver 23.7 examples of how to control the lcd driver page 388 2012/5/18 ra000 seg0 seg1 com0 com1 com2 com3
example: the following shows an example of how to set display data for displaying a number as ex- plained in example 1 by using the 1/2 duty lcd. figure 23-7 shows an example of how the seg and com pins are connected to the lcd, and table 23-8 shows how display data is set for this example. figure 23-7 example of com and seg pin connections table 23-8 example of display data (1/2 duty) number display data number display data high-order address low-order address high-order address low-order address 0 **01**11 **01**11 5 **11**10 **01**01 1 **00**10 **00**10 6 **11**11 **01**01 2 **10**01 **01**11 7 **01**10 **00**11 3 **10**10 **01**11 8 **11**11 **01**11 4 **11**10 **00**10 9 **11**10 **01**11 note:an asterisk (*) denotes "dont care". tmp89fw20a page 389 2012/5/18 ra000 seg0 seg2 seg1 seg3 com0 com1
23.7.3 drive output examples figure 23-8 1/4 duty (1/3 bias) drive tmp89fw20a 23. lcd driver 23.7 examples of how to control the lcd driver page 390 2012/5/18 ra000 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc -v lc 0 v lc -v lc 0 seg0 seg1 display data area a ddress edsp seg0 seg1 com0 com1 com2 com3 com0-seg0 (selected) com2-seg1 (non selected) 1011 0101 com0 com1 com2 com3 0x00e40
figure 23-9 1/3 duty (1/3 bias) drive tmp89fw20a page 391 2012/5/18 ra000 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc -v lc 0 v lc -v lc 0 seg2 address *: don't care seg1 seg0 com0 com1 com2 display data area *111 *010 **** *001 edsp seg0 seg1 seg2 com0 com1 com2 com0-seg1 (selected) com1-seg2 (non selected) 0x00e40 0x00e41
figure 23-10 1/3 duty (1/2 bias) drive tmp89fw20a 23. lcd driver 23.7 examples of how to control the lcd driver page 392 2012/5/18 ra000 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc -v lc 0 v lc -v lc 0 seg2 address *: don't care seg1 seg0 com0 com1 com2 display data area *111 *010 **** *001 edsp seg0 seg1 seg2 com0 com1 com2 com0-seg1 (selected) com1-seg2 (non selected) 0x00e40 0x00e41
figure 23-11 1/2 duty (1/2 bias) drive tmp89fw20a page 393 2012/5/18 ra000 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc -v lc 0 v lc -v lc 0 edsp seg0 seg1 seg2 seg3 com0 com1 com0-seg1 (selected) com0-seg2 (non selected) seg3 address *: don't care seg0 com0 display data area **01 **01 **11 **10 seg1 seg2 com1 0x00e40 0x00e41
figure 23-12 static drive tmp89fw20a 23. lcd driver 23.7 examples of how to control the lcd driver page 394 2012/5/18 ra000 v lc 0 v lc 0 v lc 0 v lc 0 v lc -v lc 0 v lc -v lc 0 edsp seg0 seg4 seg7 com0 com0-seg0 (selected) com0-seg4 (non selected) seg2 seg7 address seg5 seg4 seg3 seg0 seg1 seg6 com0 ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1 display data area *: don't care 0x00e40 0x00e41 0x00e42 0x00e43
24. flash memory the tmp89fw20a has flash memory of 126976 bytes. a write and erase operation to be performed on flash mem- ory can be controlled in the following three modes: - mcu mode in mcu mode, the flash memory is accessesd by the cpu control, and the flash memory can be execu- ted the erasing and writing without affecting the operation of a running application. therefore, this mode is used for software debugging and a firmware change after shipment of tmp89fw20a. - serial prom mode in serial prom mode, the flash memory is accesed by the cpu control. use of the serial interface (uart and sio) enables the flash memory to be controlled by the small number of pins. the tmp89fw20a used in serial prom mode supports on-board programming, which enables users to pro- gram flash memory after the microcontroller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by a third-party.high-speed access to the flash memory is available by control- ling address and data signals directly. to receive a support serivice for the program writer, please ask a toshiba sales representative. in mcu mode and serial prom modes, flash memory control registers (flscr1 and flscr2) are used to con- trol the flash memory. this chapter describes how to access the flash memory using the mcu mode and serial prom modes. tmp89fw20a page 395 2012/5/18 ra000
24.1 flash memory control the flash memory is controlled by the flash memory register 1 (flscr1) and the flash memory control regis- ter 2 (flscr2). flash memory control register 1 flscr1 7 6 5 4 3 2 1 0 (0x00fd0) bit symbol flsmd barea farea "0" "0" read/write r/w r/w r/w r/w r/w after reset 0 1 0 0 0 0 0 0 flsmd flash memory command sequence control 010: 101: others: disable command sequence execution enable command sequence execution reserved barea bootrom mapping control mcu mode serial prom mode 0: 1: hide bootrom show bootrom - show bootrom farea flash memory area select control 00: assign the data area 0x08000 through 0x0ffff to the data area 0x08000 through 0x0ffff(standard mapping) 01: assign the data area 0x01000 through 0x07fff to the data area 0x09000 through 0x0ffff. 10: assign the data area 0x18000 through 0x1ffff to the data area 0x08000 through 0x0ffff. 11: assign the data area 0x10000 through 0x17fff to the data area 0x08000 through 0x0ffff. note 1: reserved : it is prohibited to make a setting in "reserved". note 2: the flash memory control register 1 has a double-buffer structure comprised of the register flscr1 and a shift regis- ter. writing "0xd5" to the register flscr2 allows a register setting for the register flscr1 to be reflected and take ef- fect in the shift register. this means that a register setting value does not take effect until "0xd5" is written to the reg- ister flscr2. the value of the shift register can be checked by reading the register flscrm. note 3: flsmd must be set either 0y010 or 0y101. note 4: make sure that you write "0" to the bits 0 and 1 of the register flscr1. flash memory control register 2 flscr2 7 6 5 4 3 2 1 0 (0x00fd1) bit symbol cr1en read/write w after reset * * * * * * * * cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved note 1: if "0xd5" is set on flscr2 with flscr1 set to "101", the flash memory goes into an active state, and mcu consumes the same amount of current as it does during a read. tmp89fw20a 24. flash memory 24.1 flash memory control page 396 2012/5/18 ra000
flash memory status register flscrm 7 6 5 4 3 2 1 0 (0x00fd1) bit symbol busy - flsmdm baream faream - - read/write r r r r r r r after reset 0 0 0 0 0 0 0 0 busy flash memory ready / busy status 0 1 - during write or erase operation of flash memory during write or erase operation of security bit flsmdm monitoring of flscr1 status 0 1 flscr1="101" setting disabled flscr1="101" setting enabled baream monitoring of flscr1 status value of flscr1 currenly enabled faream monitoring of flscr1 status value of flscr1 currently enabled note 1: bits 5 through 2 of the flscrm is the register that checks the value of the shift regsiter of the flash memory control reg- ister 1. note 2: flsmdm turns into "1" only if flsmd="101" becomes effective. note 3: if an instruction to read flscrm is executed, "0" is read from the bit 6. note 4: in serial prom mode, "1" is always read from baream. note 5: bits 1 and 0 of flscrm are read from the value of bits 1 and 0 of flscr1 at the time 0xd5 was set to flscr2. tmp89fw20a page 397 2012/5/18 ra000
port input control register (works only in serial prom mode) spcr 7 6 5 4 3 2 1 0 (0x00fd3) bit symbol - - - - - - pin1 pin0 read/write r r r r r r r/w r/w after reset 1 1 1 1 1 0 0 0 pin1 port input control (sclk0 pin) in serial prom mode in serial prom mode in mcu mode 0 1 port input disabled port input enabled input enabled for all ports. nonfunctional whatever settings are made. "0" is read. pin0 port input control (except rxd0, txd0 and sclk0) in serial prom mode 0 1 port input disabled port input enabled note 1: a read or a write operation can be performed on the spcr register only in serial prom mode. if a write operation is performed on this register in mcu mode, the port input control does not function. if a read operation is performed on the spcr register in mcu mode, "0" is read from bits 7 through 0. note 2: all i/o ports are controlled by pin0, except the ports rxd0, txd0 and sclk0 which are used in serial prom mode. by using pin1, the sclk0 pin can be configured separately. tmp89fw20a 24. flash memory 24.1 flash memory control page 398 2012/5/18 ra000
24.2 functions 24.2.1 flash memory command sequence execution (flscr1) to prevent inadvertent writes to the flash memory due to program error or microcontroller malfunction, the execution of the flash memory command sequence can be disabled (the flash memory can be write protec- ted) by making an appropriate setting to the control register (write protection). to enable the execution of the command sequence, set flscr1 to "0y101", and then set flscr2 to "0xd5". to dis- able the execution of the command sequence, set flscr1 to "0y010", and then set flscr2 to "0xd5". if the command sequence is executed with the execution of the command se- quence set to "disable", the executed command sequence takes no effect. after a reset, flscr1 is initialized to "0y010" to disable the execution of the command se- quence. flscr1 should normally set to "0y010" except when a write or a erase is to be per- formed on the flash memory. note 1: if flscr1 is set to "disable", subsequent commands (write instruction) generated are rejected but a command sequence being executed is not initialized. if you want to set flscr1 to "disable", you must finish all command sequence and verify that the flash memory is ready to be read. tmp89fw20a page 399 2012/5/18 ra000
24.2.2 flash memory area switching (flscr1) to perform an erase or a write operation on the flash memory, a memory transfer instruction (command se- quence) must be executed. if a memory transfer instruction is used to read or write data, a read or write oper- ation can be performed only in the data area. to perform an erase or write operation on the code area, there- fore, a part of the code area must be temporarily switched to the data area. this switching between data and code areas is performed by making the appropriate setting to flscr1 . by setting "0xd5" on flscr after setting flscr1 to "01", 0x01000 through 0x07fff (area d0) in the data area is mapped to 0x09000 through 0x0ffff (area d1) in the data area. by setting "0xd5" on flscr2 after setting to "10", 0x18000 through 0x1ffff (area c1) in the code area is mapped to 0x08000 through 0x0ffff (area d1). by setting "0xd5" to flscr2 after setting flscr1 to "11", 0x10000 through 0x17fff (area c0) in the code area is mapped to 0x08000 through 0x0ffff (area d1). for example, to access 0x14000 in the code area, set "0xd5" on flscr after setting flscr1 to "11", and then execute the memory transfer instruction on 0xc000. to restore the flash memory to the initial state of mapping, set flscr1 to "00", and then set "0xd5" on flscr2. all flash memory areas can be accessed by performing the appropriate steps described above and then exe- cuting the memory transfer instruction on address 0x08000 through 0x0ffff (area d1) in the data area. additionally, make sure not to access the area where the memory is not allocated using an instruction, and not to specify the area using jump or call instruction. tmp89fw20a 24. flash memory 24.2 functions page 400 2012/5/18 ra000
figure 24-1 area switching using the flscr1 setting tmp89fw20a page 401 2012/5/18 ra000 0x0ffff ffffh 0x08000 0x07fff 0x18000 0x17fff data area if flscr=?00? code area 0x00000 0x10000 sfr ram 0x00fff 0x01000 flash flash flash 0x00000 sfr ram 0x00fff 0x00000 sfr ram 0x00fff 0x00000 sfr ram 0x00fff 0x18000 0x17fff 0x18000 0x17fff 0x18000 0x17fff 0x1ffff 0x10000 flash 61440 bytes 65536 bytes area c0 area c1 area d1 area d0 0x0ffff 0x08000 0x07fff data area if flscr=?01? code area 0x01000 65536 bytes area c0 area c1 area d0 if flscr=?10? flash 0x1ffff 0x10000 flash 0x0ffff 0x08000 0x07fff data area code area 0x01000 65536 bytes area c0 area c1 area c1 area d0 61440 bytes flash 0x1ffff 0x10000 flash 0x0ffff 0x08000 0x09000 0x07fff data area if flscr=?11? code area 0x01000 65536 bytes area c0 area d0 area c1 area d0 61440 bytes 61440 bytes area c0
24.2.3 ram area switching (syscr3) if "0xd4" is set on syscr4 after setting syscr3 to "1", ram is mapped to the code area. to restore the ram area to the initial state of mapping, set syscr3 to "0", and then set "0xd4" on syscr4. in serial prom mode, ram is mapped to the code area, irrespective of the syscr3 setting. note: do not allocate a program to switch syscr3 to the code area from 0x0040 through 0x0fff. if it is allocated to the area, the microcontroller may malfunction since the software does not function properly. 24.2.4 bootrom area switching (flscr1) if "0xd5" is set to flscr2 after setting flscr1 to "1" in mcu mode, the address- es from 0x1000 through 0x17ff in both data area and code area are masked by the flash memory, and 2k- byte (first half of 4kb) bootrom is mapped. if you do not want to map the bootrom, set "0" to flscr1, and then set "0xd5" on flscr2. bootrom stores program codes for programming the flash memory in serial prom mode, and a part of bootrom area contains a support program (api) in order to write/erase the flash memory easily. there- fore, erase/write/read the flash memory is easily performed by calling the subroutine after mapping the boot- rom. in serial prom mode, bootrom is mapped to the address from 0x1000 through 0x17ff in the data area and the address from 0x1000 through 0x1fff in the code area, irrespective of the flscr1 set- ting. barea is always "1", and the setting value of barea remains unchanged, even if you write data. "1" is always read from barea. note: do not allocate a program to switch flscr1 to the code area from 0x1000 through 0x1fff. if it is allocated to the area, the microcontroller may malfunction since the software does not function properly. tmp89fw20a 24. flash memory 24.2 functions page 402 2012/5/18 ra000
figure 24-2 show/hide switching for bootrom and ram tmp89fw20a page 403 2012/5/18 ra000 data area syssr4=?0? flscr1=?0? syssr4=?1? flscr1=?0? code area 0x00000 0x0003f 0x00040 0x0xxxx 0x01000 0x0ffff 0x10000 0x1ffff sfr data area syssr4=?0? flscr1=?1? note : 0xxxxx and 0x1xxxx is end address of ram. syssr4=?1? flscr1=?1? code area ram serial prom mode bootrom 0x00000 0x0003f 0x00040 0x0xxxx 0x01000 0x017ff 0x01800 0x0ffff sfr ram bootrom 0x10000 0x11000 0x117ff 0x11800 0x1ffff data area code area data area code area bootrom 0x00000 0x0003f 0x00040 0x0xxxx 0x01000 0x017ff 0x01800 0x0ffff sfr ram ram bootrom 0x10000 0x1003f 0x10040 0x1xxxx 0x11000 0x117ff 0x11800 0x1ffff data area code area bootrom 0x00000 0x0003f 0x00040 0x0xxxx 0x01000 0x017ff 0x01800 0x0ffff sfr ram ram bootrom 0x10000 0x1003f 0x10040 0x1xxxx 0x11000 0x117ff 0x11800 0x1ffff 0x00000 0x0003f 0x00040 0x0xxxx 0x01000 0x0ffff sfr ram ram 0x10000 0x1003f 0x10040 0x1xxxx 0x1xxxx+1 0x1ffff
24.2.5 monitoring a ready / busy state of the flash memory (flscrm) once command sequences (page program, chip erase, sector erase, security program and security erase) are executed, "1" is set to flscrm until the command sequences are completed. comple- tion of the execution can be checked using software. normally, a read operation of flscrm is exe- cuted following the execution of these command sequences, and then perform polling until "0" is read from the flash memory. 24.2.6 port input control register (spcr) in serial prom mode, the input levels of all ports, except the ports rxd0 and txd0 used in serial prom mode, are physically fixed after a reset is released. this is designed to prevent a penetration current from flowing through unused ports (port inputs and functional peripheral inputs, which are also used as ports, are disabled). therefore, to access the flash memory using the ram loader mode and a method other than the uart, port inputs must be set to "enable". to enable the sclk0 port input, set spcr to "1". to enable port inputs other than rxd0, txd0 and sclk0 port inputs, set spcr to "1". in mcu mode, the spcr register does not function. tmp89fw20a 24. flash memory 24.2 functions page 404 2012/5/18 ra000
24.3 command sequence in mcu mode and serial prom mode, the command sequence consists of seven commands, as shown in ta- ble 24-1. table 24-1 command sequence command sequence 1st bus write cy- cle 2nd bus write cy- cle 3rd bus write cy- cle 4th bus write cy- cle 5th bus write cy- cle 6th bus write cy- cle add data add data add data add data add data add data 1 page program 0x#555 0xaa 0x#aaa 0x55 0x#555 0xa0 pa (note 1) data0 (note 2) pa (note1) data1 (note 2) pa (note 1) data2 (note 2) 2 sector eraase (partial erase in sec- tor units ) 0x#555 0xaa 0x#aaa 0x55 0x#555 0x80 0x#555 0xaa 0x#aaa 0x55 sa (note 3) 0x30 3 chip erase (all erase) 0x#555 0xaa 0x#aaa 0x55 0x#555 0x80 0x#555 0xaa 0x#aaa 0x55 0x#555 0x10 4 product id entry 0x#555 0xaa 0x#aaa 0x55 0x#555 0x90 - - - - - - 5 product id exit 0x#xxx 0xf0 - - - - - - - - - - 6 security program 0x#555 0xaa 0x#aaa 0x55 0x#555 0x9a 0x#555 0xaa 0x#aaa 0x55 0x#555 0x9a 7 security erase 0x#555 0xaa 0x#aaa 0x55 0x#555 0x6a 0x#555 0xaa 0x#aaa 0x55 0x#555 0x6a command sequence 7th bus write cy- cle 8th bus write cy- cle 9th bus write cy- cle - - - 130th bus write cycle 131th bus write cycle add data add data add data - - - add data add data 1 page program pa (note 1) data3 (note 2) pa (note 1) data4 (note 2) pa (note 1) data5 (note 2) - - - pa (note 1) data 126 (note 2) pa (note 1) data 127 (note 2) 6 security program sb (note4) 0x9a - - - - - - - - - - - 7 security erase 0x#xxx 0x6a - - - - - - - - - - - note 1: pa : page address specify the beginning address of the pa to be written. refer to table 24-3 about the addressable address. as the page to be written is specified with the 4th address, addresses from 5th through 131st are not changed even if other page is specified. note 2: set the data in size of 128bytes (1 page). note 3: sa : sector address specify the sector address to be erased. refer to table 24-5 for further details about the addressable address. note 4: sb : security address specify the address of the security bits. refer to table 24-6 for further details about the addressable address. note 5: do not start the stop, idle0/1/2 or sleep1/0 mode while a command sequence is being executed or a task speci- fied in a command sequence is being executed (write, erase or id entry). note 6: # ; 0x1 through 0xf must be specified with the upper 4bits of the address. however, while flscrm is set to "1", 0x2 or more must be specified. usually, 0xf is recommended to be specified. note 7: command sequences must be executed at 4 or more instruction cycles. if you use an instruction less than 4 instruc- tion cycles, insert nop instruction right after the write instruction to provide a instruction interval of 4 or more instruc- tion cycle. a part of transfer instructions is shown in table 24-2. note 8: the command sequence must be executed when the power supply source is turned on (when sdwcr1="0" and sdwcr1="1"). even if the command sequence is executed when the pow- er supply of the flash memory is off, the command is not accepted. note 9: x ; dont care tmp89fw20a page 405 2012/5/18 ra000
table 24-2 instruction cycle of transfer instruction (example) instruction cy- cle instruction 6 ld (vw), n 5 ld (vw), r 4 ld (de), n ld (ix), n ld (iy), n 3 ld (hl), n ld (de), r ld (hl), r (note) ld (ix), r ld (iy), r note:ld (hl) and a are excepted (2 instruction cycle) tmp89fw20a 24. flash memory 24.3 command sequence page 406 2012/5/18 ra000
24.3.1 page program this command sequence writes the flash memory in units of one page. one command sequence can per- form a write to one page. one page consists of 128bytes, 992 page.the range of address that can be speci- fied to the page is shown in table 24-4. the address and the data to be written are specified in the bus write cycle from 4th through 131th. the bus write cycle from 4th through 131th (pa) must be specified as the beginning address of the page to be writ- ten. when you set addresses using the instruction, refer to the table 24-3 and set flscr1 too. for example, to write data into the page 1(0x01080 through 0x010ff) in the data area, set "0y01" to flscr1 , set "0xd5" to flscr2, and then specify 0x9080 as the address in 4th through 131th address. the time needed to write each page (the time between reception of the 131th com- mand and the moment when the flscrm becomes "0") is 1.25ms (typ.). other command sequen- ces or an operation to read from the flash memory must not be executed until the write operation is comple- ted. to check the completion of the write operation, perform a read operations on flscrm, and per- form polling until "0" is read from the flash memory. note 1: to rewrite data to address in the flash memory where data (including 0xff) is already written, make sure that you erase the existing page data by performing a sector erase or a chip erase before writing da- ta. note 2: do not perform a page program on the areas other than those shown in table 24-3. note 3: even if the pa is not the beginning address of the page, a write is performed to the page including the ad- dress. tmp89fw20a page 407 2012/5/18 ra000
table 24-3 address range specifiable (pa) write area flscr1 address from 4th through 131th (pa) sector page address area d0 (data area) 0 0x01000 through 0x0107f 01 0x9000 1 0x01080 through 0x010ff 0x9080 : : : 222 0x07f00 through 0x07f7f 0xff00 223 0x07f80 through 0x07fff 0xff80 area d1 (data area) 224 0x08000 through 0x0807f 00 0x8000 225 0x08080 thorugh 0x080ff 0x8080 : : : 478 0x0ff00 thorugh 0x0ff7f 0xff00 479 0x0ff80 through 0x0ffff 0xff80 area c0 (code area) 480 0x10000 through 0x1007f 11 0x8000 481 0x10080 through 0x100ff 0x8080 : : : 734 0x17f00 through 0x17f7f 0xff00 735 0x17f80 through 0x17fff 0xff80 area c1 (code area) 736 0x18000 through 0x1807f 10 0x8000 737 0x18080 through 0x180ff 0x8080 : : : 990 0x1ff00 through 0x1ff7f 0xff00 991 0x1ff80 through 0x1ffff 0xff80 tmp89fw20a 24. flash memory 24.3 command sequence page 408 2012/5/18 ra000
table 24-4 page configuration 0 1 2 3 4 5 6 7 8 9 a b c d e f 0x01000 f 0x01010 0x01020 0x01030 page 0 (128 bytes) 0x01040 0x01050 0x01060 0x01070 e 0x01080 f 0x01090 0x010a0 0x010b0 page 1 (128 bytes) 0x010c0 0x010d0 0x010e0 0x010f0 e 0x1ff80 f 0x1ff90 0x1ffa0 0x1ffb0 page 991 (128 bytes) 0x1ffc0 0x1ffd0 0x1ffe0 0x1fff0 e note:"f" indicates the beginning address of each page, and "e" indicates the end address of each page. tmp89fw20a page 409 2012/5/18 ra000
24.3.2 sector erase (partial erase in units of a sector) this command sequence erases the flash memory in units of a sector. one execution of the command se- quence can erase one sector, which consists of four sectors; area d0, d1, c0 and c1. 28kbytes of memo- ry is allocated to area d0, 32kbytes to area d1, c0 and c1.(figure 24-1) the sector to be erased is specified by the 6th bus write cycle address. the beginning address of the sec- tor to be erased is specified by the 6th address. set the addresses specified by the instruction must be set follow- ing the table 24-5, and also set flscr1 . for example, to erase 32kbytes from area c0, set "0y11" to flscr1, set "0xd5" to flscr2, and then specify 0x08000 as the 6th bus write cycle. the sector erase command is effective only in serial prom mode and mcu mode, and it can- not be used in parallel prom mode. the time needed to erase 32k (28k) bytes of the flash memory (the time between reception of the 6th com- mand and the moment when the value of flscrm becomes "0") is 100 ms (typ.). other command sequences or an operation to read from the flash memory must not be executed until the erasing operation is completed. to check the completion of the erase operation, perform a read operation on flscrm, and perform polling until "0" is read from the flash memory. data in the erased area is 0xff. note 1: do not perform a sector erase on areas other than those shown in table 24-5. note 2: even if sa is not the beginning address of the sector, a write is performed to the sector including the ad- dress. table 24-5 addresses range speciable (sa) erase area flscr1 6th address (sa) area d0 (data aea) 0x01000 through 0x07fff 01 0x9000 area d1 (data area) 0x08000 through 0x0ffff 00 0x8000 area c0 (code area) 0x10000 through 0x17fff 11 0x8000 area c1 (code area) 0x18000 through 0x1ffff 10 0x8000 24.3.3 chip erase (all erase) this command sequence erases the entire flash memory. the time needed to erase all areas (the time between the reception of the 6th command and the moment when the value of flscrm becomes "0") is 400 ms (typ.). other command sequences or an opera- tion to read from the flash memory must not be executed until the erasing operation is completed. to check the completion of the erase operation, perform a read operation to flscrm, and perform polling un- til "0" is read from the flash memory. data in the erased area is 0xff. tmp89fw20a 24. flash memory 24.3 command sequence page 410 2012/5/18 ra000
24.3.4 security program this command sequence sets the read protection and the write protection to the flash memory. the securi- ty program consists of 3-bit security bits (sb2 through sb0), and each command sequence can set 1-bit secur- ity bit. to set all three security bits, command sequence must be performed three times. once security bits (sb2 through sb0) is set, access limitation as shown below is set to each bit. ? mcu mode once sb2 is set, execution of a command sequence of the page program initiated by the cpu is canceled. limitations are not imposed on read operations initiated by the cpu. ? serial prom mode once sb2 is set, execution of a command sequence of the page program initiated by the cpu is canceled. limitations are not imposed on read operations initiated by the cpu. during the operation through a serial communication, if a security is set to one of the addresses from sb2 through sb0, execution of the following commands are limited: a write command to the flash memory initiated by an external device, flash memory read command and ram loader com- mand. ? parallel prom mode once the setting is applied to sb0 and sb1, a command sequence of the page program cannot be executed in all areas of the flash memory. if a read operation is performed, 0x9898 is always read from the data bus, irrespective of the flash memory settings. if the security program setting is ap- plied to one of sb0 or sb1, security program is valid, but the setting must be applied to both bits. the bits that the security porgram is to be applied are specified in the 7th bus write cycle. in this setting, the 7th address must be set according to the table 24-6. for example, to set a security to sb2, set 0x8100 as the 7th address. the processing time needed to execute one command sequence (the time between the reception of the 7th command and the time when the value of flscrm becomes "0") is 1.25ms (typ.). other command sequences or an operation to read from the flash memory must not be executed until the security setting is com- pleted. to check the completion of the security setting, perform a write operation to flscrm, and then perform polling until "0" is read from the flash memory. table 24-6 access control (sb) determined by security program security bit 7th address (sb) mcu mode serial prom mode parallel prom mode read protect write protect read protect write protect read protect write protect sb0 0x8000 - - - - sb1 0x8080 - - - - sb2 0x8100 - - - - note 1: ; access limitation can be applied by setting the corresponding security bit. note 2: - ; security bit has no effect. 24.3.5 security erase this command sequence disables write and read protection applied to the flash memory. the execution of the security erase erases the security bits from sb2 through sb0 at once. you cannot erase the security bit one by one. tmp89fw20a page 411 2012/5/18 ra000
to check whether the security program is enabled or disabled, read 0xff7f in product id mode. for fur- ther details, refer to the table 24-7. the time needed to erase it is 100ms (typ.). other command sequences or an operation to read from the flash memory must not be performed until the settings for the security erase is completed. to check the completion of the erase operation, perform a read operation to flscrm, and then perform polling until "0" is read from the flash memory. tmp89fw20a 24. flash memory 24.3 command sequence page 412 2012/5/18 ra000
24.3.6 product id entry this command activates the product id mode. if an instruction to read the flash memory is executed in prod- uct id, security status can be read from the flash memory. table 24-7 values to be read in product id mode address meaning read value 0x0ff7f security status bit 0 (sb0) 0 : sb0 enabled 1 : sb0 disabled bit 1 (sb1) 0 : sb1 enabled 1 : sb1 disabled bit 2 (sb2) 0 : sb2 enabled 1 : sb2 disabled bit 7 to 3 0y11111 note:x ; dont care 24.3.7 product id exit this command sequence is used to exit the product id mode. tmp89fw20a page 413 2012/5/18 ra000
24.4 access to the flash memory area a read or a program fetch cannot be performed on the whole of the flash memory area if the following opera- tions are performed: (a) data is being written to the flash memory. (b) data in the flash memory is being erased. (c) security settings are being made in the flash memory. when performing these operation on the flash memory area, the flash memory cannot be directly accessed by using a program in the flash memory; the flash memory must be accessed using a program in the bootrom area or the ram area. data can be written to and read from the flash memory area is in units of one page (128bytes). data in the flash memory can be erased in units of 32kbytes (partially 28kbytes) or the whole of the flash memory at one stroke. a read can be performed using one memory transfer instruction. a write or erase, however, must be per- formed with the execution of the memory transfer instructions several times to several hundreds of times because the command sequence method is used. for further information about the command sequence, refer to table 24-1. note 1: to allow a program to resume control on the flash memory area that is rewritten, it is recommended that you let the program jump (return) after verifying the program has been written properly. note 2: do not reset the mcu (including a reset generated due to the internal factors) when data is being written to the flash memory, data is being erased from the flash memory or the security command is being executed. if a reset occurs, there is the possibility that data in the flash memory may be rewritten to an unexpected value. note 3: the flash memory must be accessed when the power supply of the flash memory is provided (when sdwcr1 ="0" and sdwcr1="1"). 24.4.1 flash memory control in serial prom mode the serial prom mode is used to access the flash memory by using a control program provided in the boot- rom area. since almost all operations relating to access to the flash memory can be controlled simply using data supplied through the serial interface (uart or sio), it is not necessary for the user to operate the con- trol register. for details of the serial prom mode, see "serial prom mode". to access the flash memory in serial prom mode by using a user-specific program or peripheral func- tions other than uart and sio, it is necessary to execute a control program in the ram area by using the ram loader command of the serial prom mode. how to execute this control program is described in "24.4.1.1 how to transfer and write a control program to the ram area in ram loader mode of the serial prom mode". 24.4.1.1 how to transfer and write a control program to the ram area in ram loader mode of the se- rial prom mode how to execute a control program in the ram area in serial prom mode is described below. a con- trol program to be executed in the ram area must be generated in the intel-hex format and be transfer- red using the ram loader of the serial prom mode. step 1 and 2 shown below are controlled by a program in the bootrom, and other steps are control- led by a program transferred to the ram area. the following procedure is linked with a program exam- ple to be explained later. 1. transfer the write control program to the ram are in ram loader mode. 2. jump to the ram area. 3. set a nonmaskable interrupt vector in the ram area. 4. set "0y101" on flscr1, and specify the area to be erased by making the appropri- ate flscr1 setting. then set "0xd5" on flscr2. 5. execute the erase command sequence. 6. perform a read operation repeatedly until the value of flscrm becomes "0". tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 414 2012/5/18 ra000
7. specify the area (area erased in the step5 above) to which data is written by making the appro- priate flscr1 setting. then set "0xd5" on flscr2. 8. execute the write command sequence. 9. perform a read operation repeatedly until the value of flscrm becomes "0". 10. set flscr1 to 0y010, and then set "0xd5" on flscr2 (to disable the execution of the command sequence) note 1: if the ram loader is used in serial prom mode, the bootrom disables (di) a maskable interrupt, and the interrupt vector area is assigned as a ram area (syscr3 = "1").considering that a nonmaskable interrupt may be generated unexpectedly, it is recommended that vector address cor- responding these interrupts (intundef, intswi : 0x001f8 to 0x001f9, wdt : 0x001fc to 0x001fd) be established and that an interrupt service routine be defined inside the ram area. note 2: if a certain interrupt is used in the ram loader program, a vector address corresponding to that inter- rupt and the interrupt service must be established inside the ram area. in this case, it is recommen- ded that a nonmaskable interrupt be handled as explained in note 1. note 3: do not set syscr3 to "0" by using the ram loader program. if an interrupt occurs with syscr3 set to "0", the bootrom area is referenced as a vector address and, therefore, the program will not function properly. (example) a case in which a program is transferred to ram using the ram loader program, 128- byte data is stored in the ram (address 0x00200 to 0x0027f) via the serial interface, the sec- tor erase is performed on address 0x08000 through 0x0ffff in the data area, and then write the stored ram data to address 0x08500 through 0x0857f. if nonmaskable interrupts (in- tswi, intundef and intwdt) occur during a write or erase operation, then the system clock reset will be generated. main section code abs = 0x0100 ; #### set a nonmaskable interrupt vector inside the ram area. #### (step 3) ld hl,0x01fc ; set intundef, intswi interrupt vector ldw (hl),sintswi ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),sintwdt ; #### prepare data to be written #### store 128-byte of data in the ram (0x0200 - 0x027f) through a data channel, such as the serial interface ; #### disable mapping of shadow ram in the data area #### ld (sdwcr1),0x60 ; dadis=1 ; #### sector erase and write process #### ld iy,0xf555 ; variable for command sequence ld de,0xfaaa ; variable for command sequence ; sector erase process (step 5) ld c,0x00 ; set upper address ld ix,0x8000 ; set middle and lower addresses call ssectorerase ; sector erase process (0x08000) ; write process (step 8) ld c,0x00 ; set upper address ld ix,0x8500 ; set middle and lower address ld hl, 0x0200 ; set the beginning address of ram to be copied call spageprogram ; write process (0x08500) ; #### enable mapping of shadow ram in the data area #### ld (sdwcr1),0x40 ; dadis=0 ; #### execute the next main program #### tmp89fw20a page 415 2012/5/18 ra000
: : ; execute the main program j xxxxx ; #### proram to be executed in ram #### ssectorerase: call saddconv ; address conversion process ; sector erase process ld (iy),0xaa ; 1st bus write cycle (note1) ld (de),0x55 ; 2nd bus write cycle (note1) ld (iy),0x80 ; 3rd bus write cycle (note1) ld (iy),0xaa ; 4th bus write cycle (note1) ld (de),0x55 ; 5th bus write cycle (note1) ld (ix),0x30 ; 6th bus write cycle (note1) j sramopend ; write process spageprogram: call saddconv ; convert address ld (iy), 0xaa ; 1st bus write cycle (note1) ld (de), 0x55 ; 2nd bus write cycle (note1) ld (iy), 0xa0 ; 3rd bus write cycle (note1) spageloop: ld b, (hl) ld (ix),b ; 4th through 131th bus write cycle (note1) inc hl cmp l, 0x80 j nz, spageloop ; loop until the data of 1page is set ; end process sramopend nop ; (note2) nop ; (note2) nop ; (note2) sloop1: test (flscrm).7 ; (step 6,9) j f,sloop1 ; loop until flscrm becomes "0". ld (flscr1),0x40 ; disable the execution of command sequence (step 10) ld (flscr2),0xd5 ; reflect the flscr1 setting ret ; convert address (step 4 and 7) saddconv: ld wa,ix swap c and c,0x10 swap w and w,0x08 or c,w xor c,0x08 shrc c or c,0xa0 ld (flscr1),c ; enable the execution of command sequence. make the farea setting ld (flscr2),0xd5 ; reflect the flscr1 setting ld wa,ix test c.3 j z,saddconvend or w,0x80 ld ix,wa saddconvend: ret ; interrupt sesrvice routine sintwdt: tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 416 2012/5/18 ra000
sintswi: test (flscrm).7 j f,sintwdt ; loop until the value of the flscrm becomes "0". ld (syscr2),0x10 ; generatesystem clock reset retn note 1: in using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than four machine cycles or arrange write instruction in such a way that they are generated at in- tervals of four machine cycles or more machine cycles. if a 16-bit transfer instruction is used or if write instructions are executed at intervals of three machine cycles, the flash memory command se- quence will not be transmitted properly, and a malfunction may occur. note 2: if a read of the flscrm is to be performed after a write instruction is executed in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of three or more machine cycle;machine cycles are counted when the last xth bus write cycle is gener- ated to when each instruction is generated. three nop instructions are normally used. tmp89fw20a page 417 2012/5/18 ra000
24.4.2 flash memory control in mcu mode in mcu mode, a write operation can be performed on the flash memory by executing a control program in the ram or the shadow ram, or using a support program (api) provided in the bootrom. 24.4.2.1 how to write to the flash memory by transferring a control program to the ram area this section describes an example of how to execute a control program in ram in mcu mode. a con- trol program to be executed in the ram must be acquired and stored in the flash memory or it must be im- ported from an outside source through a communication pin, etc. (the procedures described below are an example assumed that a program copy is provided in the flash memory.) steps 1 through 5 and 11 shown below concern the control by a program in the flash memory, and oth- er steps concern the control by a program transferred to ram. the following procedure is linked with a pro- gram example to be described later. 1. set the interrupt master enable flag to "disable (di)"(imf "0"). 2. transfer the write control program to the ram. 3. establish the nonmaskable interrupt vector in the ram area. 4. after setting both syscr3 and syscr3 to "1", set "0xd4" on syscr4. then allocate the ram to the code area, and switch the vector area to the ram area. 5. disable mapping of shadow ram in the data area. 6. invoke the erase processing program in the ram area by executing a call instruction. 7. set flscr1 to "0y101", and specify the area to be erased by making the appropri- ate flscr1 setting. then set "0xd5" on flscr2. 8. execute the erase command sequence. 9. perform a read repeatedly until the value of flscrm becomes "0". 10. after setting flscr1 to "0y010" and flscr1 to "0y00", set "0xd5" on flscr2. (this disables the execution of the command sequence and returns farea to the initial state of mapping.) 11. execute the ret instruction to return to the flash memory. 12. invoke the write program in the ram area by executing a call instruction. 13. set flscr1 to "0y101", and make the appropriate flscr1 setting to specify the area (area erased by performing step 7 above) on which a write is to be performed. then set "0xd5" on flscr2. 14. execute the write command sequence. 15. perform a read on the same address in the flash memory repeatedly until the read value of flscrm becomes "0". 16. after setting flscr1 to "0y010" and flscr1 to "0y00", set "dx05" on flscr2 (this disables the execution of the command sequence and returns farea to the initial state of mapping.) tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 418 2012/5/18 ra000
17. execute the ret instruction to return to the flash memory. 18. after setting both syscr3 and syscr3 to "0", set "0xd4" on syscr4. then release ram allocation for the code area, and switch the vector area to the flash area. 19. enable mapping of shadow ram in the data area. note 1: before writing data to the flash memory from the ram area in mcu mode, the vector area must be switched to the ram area by using syscr3, data must be written to the vector address- es (intundef, intswi : 0x001f8 to 0x001f9, intwdt : 0x001fc to 0x001fd) that correspond to nonmaskable interrupts, and the interrupt subroutine (ram area) must be defined. this allows you to trap the errors that may occur due to an unexpected nonmaskable interrupt during a write opera- tion. if syscr3 is set in the flash memory area and if an unexpected interrupt occurs dur- ing a write operation, a malfunction may occur because the vector are in the flash memory cannot be read properly. note 2: before using a certain interrupt in mcu mode, the vector address corresponding to the interrupt and the interrupt service routine must be established in the ram area. in this case, the nonmaskable inter- rupt setting must be made, as established in note1. note 3: before jumping from the flash memory to the ram area, ram must bealocated to the code area by making the appropriate syscr3 setting (setting made in step 4 in the procedure descri- bed on the previous page). note 4: the setting described in step 4 cannot be allocated to the code area from 0x0040 to the end of ram address in the flash memory. if the setting is executed in the code area in the flash memory, the fetch area is switched from the flash memory area to the ram area, and the program will not func- tion properly. (example) case in which a program is transferred to ram (starting address 0x00200), a sector erase is performed on the address 0x08000 through 0x0ffff in the data area, and then ram data (0x00100 through 0x0017f) is written to the address 0x08500 through 0x0857f. if nonmaska- ble interrupts (intswi, intundef or intwdt) occur during a write or erase operation is be- ing executed, system clock reset is generated. cramstartadd equ 0x0200 ; ram start address main section code abs = 0x1f000 di ; disable interrupts (step 1) ; #### transfer the program to ram #### (step2) ld hl,cramstartadd ld ix,sramprogstart sramloop: ld a,(ix) ; transfer to cramstartadd the program (from ld (hl),a ; sramprogstart to sramprogend). inc hl inc ix cmp ix,sramprogend j nz,code_addr(sramloop) ; #### set a nonmaskable interrupt vector in the ram area #### (step 3) ld hl,0x01fc ; set intundef and intswi interrupt vector ldw (hl),sintswi - sramprogstart + cramstartadd ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),sintwdt - sramprogstart + cramstartadd ; #### allocate ram to the code area. switch the vector area to ram #### (step 4) ld (syscr3),0x06 ; set rarea = 1 and rvctr = 1. ld (syscr4),0xd4 ; enable code ; #### disable mapping of shadow ram in the data area #### ld (sdwcr1),0x60 ; dadis=1 ; #### sector erase and write process #### ld iy,0xf555 ; variable for command sequence tmp89fw20a page 419 2012/5/18 ra000
ld de,0xfaaa ; variable for command sequence ; sector erase process (step 5) ld c,0x00 ; set upper addresses ld ix,0x8000 ; set middle and lower addresses call ssectorerase - sramprogstart + cramstartadd ; sector erase process (0x1e000) ; write process (step 11) ld c,0x00 ; set upper addresses ld ix,0x8500 ; set middle and lower addresses ld hl, 0x0100 ; set the beginning address of ram to be copied. call spageprogram - sramprogstart + cramstartadd ; write process (0x1e500) ; ####allocate ram to the code area. switch the vector area to ram.#### (step 17) ld (syscr3),0x00 ; set rarea = 0 and rvctr = 0 ld (syscr4),0xd4 ; enable code ; #### enable mapping of shadow ram in the data area #### ld (sdwcr1),0x40 ; dadis=0 ; #### execute the next main program #### : : ; execute the main program j xxxxx ramexe section code abs = 0x2000 ; #### program to be executed in ram #### sramprogstart: nop ; fail-safe process nop nop nop nop ld (syscr2),0x10 ; generate system clock reset ssectorerase: call saddconv - sramprogstart + cramstartadd ; address conversion process ; sector eraseprocess (step 7) ld (iy),0xaa ; 1st bus write cycle (note1) ld (de),0x55 ; 2nd bus write cycle (note1) ld (iy),0x80 ; 3rd bus write cycle (note1) ld (iy),0xaa ; 4th bus write cycle (note1) ld (de),0x55 ; 5th bus write cycle (note1) ld (ix),0x30 ; 6th bus write cycle (note1) j sramopend ; write process (step 13) spageprogram: call saddconv - sramprogstart + cramstartadd ; address conversion process ld (iy), 0xaa ; 1st bus write cycle (note1) ld (de), 0x55 ; 2nd bus write cycle (note1) ld (iy), 0xa0 ; 3rd bus write cycle (note1) spageloop: ld b, (hl) ld (ix),b ; 4th through 131th bus write cycle (note1) inc hl cmp l, 0x80 j nz, spageloop ; loop until data of one page is set ; end process tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 420 2012/5/18 ra000
sramopend: nop ; (note2) nop ; (note2) nop ; (note2) sloop1: test (flscrm).7 ; (step 8 and 14) j f,sloop1 ; loop until flscrmbecomes "0". ld (flscr1),0x40 ; disable the execution of command sequence ; (step9 and 15) ld (flscr2),0xd5 ; reflect the flscr1 setting ret ; return to flash memory ; address conversion process (step 6 and 12) saddconv: ld wa,ix swap c and c,0x10 swap w and w,0x08 or c,w xor c,0x08 shrc c or c,0xa0 ld (flscr1),c ; enable the execution of command sequence.make the farea setting ld (flscr2),0xd5 ; reflect the flscr1 setting ld wa,ix test c.3 j z,saddconvend or w,0x80 ld ix,wa saddconvend: ret ; interrupt service routine sintwdt: sintswi: test (flscrm).7 j f,sintwdt ; loop until flscrm becomes "0". ld (syscr2),0x10 ; generate system clock reset retn sramprogend: nop note 1: in using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than four machine cycles or arrange write instructions in such a way that they are generated at intervals of four or more machine cycles. if a 16-bit transfer instruction is used or if write instruc- tions are executed at intervals of two machine cycles, the flash memory command sequence will not be transmitted properly, and a malfunction may occur. note 2: if a read of the flscrm is to be performed after a write instruction is generated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of four or more machine cycles. three nop instructions are normally used. tmp89fw20a page 421 2012/5/18 ra000
24.4.2.2 how to write to the flash memory by using a support program (api) of bootrom this section describes how to perform an erase and a write on the flash memory by using a support pro- gram (api) of bootrom in mcu mode. for details, refer to"24.5 api (application programming inter- face)". steps 1 through 14 shown below concern the control by a program in the flash memory. 1. establish the nonmaskable interrupt vector in the .btreset (0x1000). 2. after setting both syscr3 and syscr3 to "1", set "0xd4" on syscr4. then allocate ram to the code area, and switch the vector area to the ram area. 3. set "0xd5" on flscr2 after setting "1" on flscr1. 4. disable mapping of shadow ram in the data area. 5. set the address range to be erased to the a register according to table 24-9. 6. set "0xd5" to the c register as enable code. 7. call .bterasesec(0x1012).(sector erase is performed. it is not necessary from the step 4 to the step 6, if programming area is already erased.) 8. set the beginning address a[16] of page for programming to the c register. (upper 7 bits of the c register should be set to "0".) 9. set the beginning address a[15:0] of page for programming to the wa register. 10. set the beginning address of ram to be copied to the de register. 11. set "0xd5" to (sp-) as an enable code. 12. call .btwrite(0x1010). (page program is performed.) 13. if programming is continued for other page, return to step 7. 14. set "0xd5" to flscr2 after setting "0" to flscr1. 15. set "0xd4" to syscr4 adter setting "0" to both syscr3 and syscr3. 16. enable mapping of shadow ram in the data area. (example) case in which a sector erase is performed to the address from 0x08000 to 0x0ffff in the da- ta area, and then data stored in the address 0x00100 to 0x0017f in ram is written to the ad- dress 0x08000 to 0x0807f in the data area. if nonmaskable interrupts (intswi, intundef or intwdt) occur during a write or erase operation is going on, system clock reset is generated. .btreset equ 0x1000 ; generate system clock reset .btwrite equ 0x1010 ; write data to the flash memory .bterasesec equ 0x1012 ; sector erase .bterasechip equ 0x1014 ; chip erase .btgetsp equ 0x1016 ; check the status of security program .btsetsp equ 0x1018 ; configure the security program .btread equ 0x101a ; read data from the flash memory tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 422 2012/5/18 ra000
.btconvadr equ 0x101c ; address conversion process .btcalcuart equ 0x101e ; calculate the setting value of uart from the timercapture value .bterssp equ 0x1020 ; disable security program .btupdsd equ 0x1022 ; shadow ram update main section code abs = 0x1f000 ; #### set a nonmaskable interrupt vector to .btreset #### ld hl,0x01fc ; set intundef and intswi interrupt vectors ldw (hl),.btreset ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),.btreset ; #### allocate ram in the code area. switch the vector area to ram #### ld (syscr3),0x06 ; set rarea = 1 and rvctr = 1 ld (syscr4),0xd4 ; enable code ; #### allocate bootrom to the data/code area #### ld (flscr1),0x50 ; set barea to "1" ld (flscr2),0xd5 ; reflect the flscr1 setting ; #### disable mapping of shadow ram in the data area #### ld (sdwcr1),0x60 ; dadis=1 ; #### sector erase process (api) #### ld a,0x20 ; specify the area to be erased (0x08000 through 0x0ffff) ld c,0xd5 ; enable code call (.bterasesec) ; execute sector erase ; #### write process #### ld c,0x00 ; beginning address of page (bit16) ld wa,0x8000 ; beginning address of page (bit 15 to 0) ld de,0x0100 ; beginning address of ram to be copied ld (sp-),0xd5 ; enable code call (.btwrite) ; write data to the flash memory (128bytes) ; ####end process #### ld (flscr1),0x40 ; set barea to "0" ld (flscr2),0xd5 ; enable code ld (syscr3),0x00 ; set rarea = 0 and rvctr = 0 ld (syscr4),0xd4 ; enable code ; #### enable mapping of shadow ram in the data area #### ld (sdwcr1),0x40 ; dadis=0 : : j xxxx note 1: do not allocate the above program to the address from 0x0000 through 0x17ff in the code area of the flash memory. if the area is set as barea="1", it changes from the flash memory area to the bootrom area, so that the program will not function properly and the microcontroller may malfunction. note 2: it is not necessary to add di instruction to disable interrupt maskable enable flag (imf) for above sample pro- gram, because the support program has it. however, the support program does not include ei instruction. en- able imf after finishing all above process, if you use interrupt process. tmp89fw20a page 423 2012/5/18 ra000
24.4.2.3 how to set the security program by using a support program (api) of bootrom 1. transfer the subroutine program of nonmaskable interrupt (intswi and intwdt) to ram. 2. establish the nonmaskable interrupt vector in the ram area. 3. after setting "1" to both syscr3 and syscr3, set "0xd4" on syscr4. then allocate ram to the code area, and switch the vector area to the ram area. 4. set "1" on flscr1. 5. set "0xd5" on the a register as enable code. 6. disable mapping of shadow ram in the data area. 7. call .btgetsp(0x1016). (after processing, security program state returns to the a register) 8. read the a register, and then jump to the sskip because the security program is already set. 9. set "0xd5" to the a register as enable code. 10. call .btsetsp(0x1018). (security program is performed.) 11. set "0" on flscr1, and set "0xd5" on flscr2. 12. after setting "0" to both syscr3 and syscr3, set "0xd4" on syscr4. 13. enable mapping of shadow ram in the data area. (example) check the setting of security program(sb2). if it is not set yet, set security program(sb2). .btreset equ 0x1000 ; generate system clock reset. .btwrite equ 0x1010 ; write data to the flash memory .bterasesec equ 0x1012 ; sector erase .bterasechip equ 0x1014 ; chip erase .btgetsp equ 0x1016 ; check the state of security program .btsetsp equ 0x1018 ; set security program .btread equ 0x101a ; read data from the flash memory .btconvadr equ 0x101c ; address conversion .btcalcuart equ 0x101e ; calculate the setting value of uart from the timercapture value .bterssp equ 0x1020 ; disable security program .btupdsd equ 0x1022 ; shadow ram update main section code abs = 0x1f000 ; #### set a nonmaskable interrupt vector to .btreset #### ld hl,0x01fc ; set intundef and intswi interrupt vector ldw (hl),.btreset ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),.btreset ; #### allocate ram to the code area. switch the vector area to ram #### ld (syscr3),0x06 ; set rarea = 1 and rvctr = 1 ld (syscr4),0xd4 ; enable code ; #### allocate bootrom to data/code area #### ld (flscr1),0x50 ; set "1" to barea tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 424 2012/5/18 ra000
ld (flscr2),0xd5 ; reflict the flscr1 setting ; #### disable mapping of shadow ram in the data area #### ld (sdwcr1),0x60 ; dadis=1 ; #### check the status of security program #### call (.btgetsp) ; check the status of security program test a.2 j t,code_addr(sskip) ; go to sskip if sb2 is "0". ; #### security program enable process (api) #### ld wa,0x8000 ld de,0x0080 ld (sp-),0xd5 ; enable code ld c,0xfb ; set sb2=0 call (.btsetsp) ; set security program sskip: ld (flscr1),0x40 ; set "0" to barea ld (flscr2),0xd5 ; enable code ld (syscr3),0x00 ;set rarea = 0 and rvctr = 0 ld (syscr4),0xd4 ; enable code ; #### enable mapping of shadow ram in the data area #### ld (sdwcr1),0x40 ; dadis=0 : : j xxxx note 1: do not allocate the above program to the address from 0x0000 through 0x17ff in the code area of the flash memory. if the area is set as barea="1", it changes from the flash memory area to the bootrom area, so that the program will not function properly and the microcontroller may malfunction. note 2: it is not necessary to add di instruction to disable interrupt maskable enable flag (imf) for above sample pro- gram, because the support program has it. however, the support program does not include ei instruction. en- able imf after finishing all above process, if you use interrupt process. tmp89fw20a page 425 2012/5/18 ra000
24.4.2.4 how to rewrite the program itself by using the shadow ram and the support program (api) of the bootrom the following shows an example of how to execute a control program stored in the shadow ram in mcu mode. step 1 through 14 shown below are the processes performed by the program stored in the shadow ram. 1. set the nonmaskable interrupt vector to .btreset(0x1000). 2. set "0xd4" to syscr4 after setting "1" to both syscr3 and syscr3. then, allocate ram to the code area and switch the vector area to ram. 3. set "1" to flscr1, and set "0xd5" to flscr2. 4. set the range of address to be erased into the a register according to table 24-9. 5. set "0xd5" to the c register as enable code. 6. disable mapping of shadow ram in the data area. 7. call .bterasesec (0x1012). (sector erase is performed. it is not necessary from the step 4 to the step6, if programming area is already erased.) 8. store a new program in ram through a data channel, such as the serial interface. 9. set the beginning address a[16] of page for programming to the c register. (upper 7 bits of the c register should be set to "0".) 10. set the beginning address a[15:0] of page for programming to the wa register. 11. set the beginning address of ram to be copied to the de register. 12. set "0xd5" to (sp-) as an enable code. 13. call .btwrite(0x1010). (page program is performed.) 14. add "0x80" to the contents of the wa register and store the data in ram. 15. if programming is continued for other page, return to step 7. 16. set the address to return after updating the shadow ram into the wa register. 17. call .btupdsd(0x1022). (shadow ram is updated.) (example) case in which a sector erase is performed to the address from 0x18000 through 0x1ffff in the shadow ram area, and then write the new program obtained via the serial interface to the address 0x18000 through 0x1ffff in the flash memory. then, update the shadow ram, and run the new program from the address 0x1f900. if nonmaskable interrupts (intswi, in- tundef or intwdt) occur during a write or erase operation is going on, system clock re- set is generated. .btreset equ 0x1000 ; generate system clock reset .btwrite equ 0x1010 ; write data to the flash memory .bterasesec equ 0x1012 ; sector erase .bterasechip equ 0x1014 ; chip erase tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 426 2012/5/18 ra000
.btgetsp equ 0x1016 ; check the status of security program .btsetsp equ 0x1018 ; configure the security program .btread equ 0x101a ; read data from the flash memory .btconvadr equ 0x101c ; address conversion proces .btcalcuart equ 0x101e ; calculate the setting value of uart from the timercapture .bterssp equ 0x1020 ; disable security program .btupdsd equ 0x1022 ; shadow ram update ram section data abs = 0x00200 .gprgadd dsb 2 ; variable for write address main section code abs = 0x1fc00 ; #### set a nonmaskable interrupt vector to.btreset #### ld hl,0x01fc ; set intundef and intswi interrupt vector ldw (hl),.btreset ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),.btreset ; #### allocate ram in the code area. switch the vector area to ram #### ld (syscr3),0x06 ; set rarea = 1 and rvctr = 1 ld (syscr4),0xd4 ; enable code ; #### allocate bootrom to the data/code area #### ld (flscr1),0x50 ; set barea to "1" ld (flscr2),0xd5 ; reflect the flscr1 setting ; #### disable mapping of shadow ram in the data area #### ld (sdwcr1),0x60 ; dadis=1 ; #### sector erase process (api) #### ld a,0x20 ; set the address range to be erased (0x08000 to 0x0ffff) ld c,0xd5 ; enable code call (.bterasesec) ; perform sector erase ; ####load programming data #### ld hl, gprgadd ; set variable for write address ld (hl), 0x8000 ; set the start address sgetprgdat: store a new program in ram (0x00100 through 0x0017f) 128bytes at a time through a data channel, such as the serial interface ; #### write operation (api)#### ld c, 0x01 ; beginning address of page (bit 16) ld wa, (gprgadd) ; beginning address of page (bit 15 through bit0) ld de,0x0100 ; beginning address of ram to be copied ld (sp-),0xd5 ; enable code call (.btwrite) ; write data to the flash memory (128bytes) ld hl, gprgadd ; set variable for write address add wa, 0x80 ; set the start address ld (hl), wa cmp wa, 0x0000 ; repeat the operation to the last page j nz, sgetprgdat ; #### shadow ram update #### ld wa, 0xf900 ; set 0x1f900 as return address call (.btupdsd) ; jump to 0x1f900 after shadow ram update tmp89fw20a page 427 2012/5/18 ra000
24.4.2.5 how to read data from flash memory to read data from the flash memory, execute transfer instruction (read) for the memory. it is possible to read arbitrary data including the code area by setting the flscr1 and flscr2. (example) case in which data is read from 0x1f000 in the code area and stored at (0x98) in ram ld (flscr1),0xa8 ; select area c1 ld (flscr2),0xd5 ; reflect the flscr1 setting ld a,(0xf000) ; read data from 0xf000 ld (0x98),a ; store data at 0x98 ld (flscr1),0x40 ; select area d0 ld (flscr2),0xd5 ; reflect the flscr1 setting tmp89fw20a 24. flash memory 24.4 access to the flash memory area page 428 2012/5/18 ra000
24.5 api (application programming interface) the bootrom has a support program (api) which contains a special subroutine for erasing or writing on the flash memory. after mapping of the bootrom, it allows easy erasing or writing on the flash memory by call- ing the subroutine in bootrom. the table 24-8 shows the list of api. note:api must be called only when, except (.btcalcuart), the flash memory is turned on (when sdwcr1 ="0" and sdwcr1="1"). if the flash memory is turned off, an adequate re- sponse cannot be obtained even if api is called. table 24-8 list of api address contents using stack (note2) work register (note1) argument return value register setting value register contents 0x1000 (.btreset) perform polling until flscrm be- comes "0", and then gen- erate system clock reset - - - - - - - 0x1010 (.btwrite) write 128 consecutive bytes (one page) stored in ram to the flash mem- ory 19 bytes wa bc de ix wa beginning address of page (m, l) a 0xff normal end c beginning address of page (h) 0x00 overwrite error de ram beginning address to be copied 0x01 no busy error (sp-) 0xd5 (enable code) 0x02 write protection er- ror 0x03 verify error 0x1012 (.bterasesec) erasing the specified one sector. 6bytes wa bc de ix a erase sector a 0xff normal end c 0xd5 (enable code) 0x01 no busy error 0x1014 (.bterasechip) executing the chip erase 8bytes wa bc de ix a 0xd5 (enable code) a 0xff normal end 0x01 no busy error 0x1016 (.btgetsp) getting the status of se- curity program 8bytes wa bc de ix a the contents of id (0x0ff7f) 0x1018 (.btsetsp) setting the security pro- gram 13 bytes wa bc de ix wa 0x8000 a 0xff normal end c security setting value 0x01 no busy error de 0x0080 - 0x02 address overflow er- ror (sp-) 0xd5 (enable code) - - - 0x101c (.btconvadr) converting the flash memory address 4bytes wa bc de wa beginning address of page (m, l) wa converted address c beginning address of page (h) - - 0x101e (.btcalcuart) calculating the uart register setting (baud rate) using the value of the pulse width captured by timer counter 4bytes wa bc de ix iy wa captured value by timer counter w setting value for rtsel c the number of bit for cal- culation a setting value for uartdr tmp89fw20a page 429 2012/5/18 ra000
table 24-8 list of api address contents using stack (note2) work register (note1) argument return value register setting value register contents 0x101a (.btread) write 128 consecutive bytes (one page) stored in the flash memory to ram 9bytes wa bc de ix wa beginning address of page to be copied (m, l) a 0xff normal end c beginning address of page to be copied (h) 0x00 enable code error de beginning address of copy destination in ram - - - (sp-) 0xd5 (enable code) 0x1020 (.bterssp) disabling the security program 6bytes wa bc de ix a 0xd5 (enable code) a 0xff normal error 0x01 no busy error 0x1022 (.btupdsd) updating the contents of shadow ram 2bytes wa wa return address (note3) - - - note 1: since working registers are rewritten in the support program, if necessary, save the contents of the work registers be- fore calling the support program. note 2: while the support program is being executed, a maximum 19 bytes are used as stack (not including stack used by in- terrupts). therefore, be sure to reserve a stack area beforehand. note 3: if 0xffff is set, it returns to the 2-byte address stack in sp, regardless of the value of wa. 24.5.1 .btwrite this api writes 128-byte data after ram address specified by the de register into the page in the flash mem- ory specified by the c register and the wa register. enable code (0xd5) must be set preliminarily in (sp-). be- fore performing a write operation, the lower seven bits of the a register are masked to be "0". after the write operation, verification of page data and ram are performed. if a difference is found, api returns the a register with the contents of "0x03" (verify error) as return value. this api reads the page (128bytes) specified before performing a write operation. if a data other than "0xff" is included even for a byte, a write operation is not performed, and the api returns the a register with the contents of "0x00"(overwrite error) as return value. if security program (sb2) is enabled, a write operation is not performed, and the api returns the a regis- ter with the contents of "0x02" (write protection error) as return value. after performing a write operation, if the status of the flash memory does not become busy (in the case that "0xd5" is not set to (sp-), etc.), the api returns the a register with the contents of "0x01" (no busy er- ror) as return value. if the process is completed successfully, a return value is "0xff". 24.5.2 .btread this api reads 128-byte data after the beginning address of page in the flash memory specified by the c reg- ister and the wa register, and write the data into the 128 bytes after ram address specified by the de regis- ter. enable code (0xd5) must be set preliminarily in (sp-). before read operation, the lower seven bits of the a register are masked to be "0". this api can access the data (one page) of arbitrary address in the flash memory via ram by using with .btwrite. if the process is completed successfully, a return value is "0xff". if the data set to (sp-) is not "0xd5", "0x00" is returned as a return value which indicates an enable code error. if this value is returned, an opera- tion to read the flash memory and a operation to write data to ram are not performed. after the completion of the api, flscr1 is initialized to "0y00" regardless of the operation result; normal end or error. tmp89fw20a 24. flash memory 24.5 api (application programming interface) page 430 2012/5/18 ra000
24.5.3 .bterasesec this api erases the sector specified on the a register. enable code (0xd5) must be preliminarily set in the c register. table 24-9 shows the sectors to be erased. after erasing a sector, if the flash memory does not become busy state (in the case "0xd5" is not set to the c register, etc), the api returns the a register with the contents of "0x01" (no busy error) as return val- ue. if the process is completed successfully, a return value is "0xff". table 24-9 sector to be erased a register erasing sector erasing area 0x04 - 0x1f erase area d0 0x01000 through 0x07fff 0x20 - 0x3f erase area d1 0x08000 through 0x0ffff 0x40 - 0x5f erase area c0 0x10000 through 0x17fff 0x60 - 0x7f erase area c1 0x18000 through 0x1ffff 24.5.4 .bterasechip all flash memory area is erased. enable code (0xd5) must be preliminarily set in the a register. after per- forming the erase operation, if the flash memory does not become busy state (in the case "0xd5" is not set to the a register, etc.), the api returns the a register with the contents of "0x01" (no busy error) as return value. if the process is completed successfully, a return value is "0xff". 24.5.5 .btgetsp the security status of the flash memory can be obtained. the api returns the a register with the contents of (0xff7f) in the product id as return value. 24.5.6 .btsetsp this api set the security program of the flash memory. 0x8000 must be set on the wa register and 0x0080 must be set on the de register preliminarily. if the value set to the c register is "0xff", the expected operation is not performed, and "0xff" is returned to the a register. after disabling the security program, if the flash memory does not become busy (in the case "0xd5" is not set to (sp-), etc.), "0x01" (no busy error) is returned to the register a. also, the setting address exceeds 0xffff due to the setting of the start address and the increment address, "0x02" (address overflow error) is returned to the a register. setting values of c register 7 6 5 4 3 2 1 0 "1" "1" "1" "1" "1" sb2 sb1 sb0 sb2 the write protection setting in mcu mode and serial prom mode. 0: 1: enable a write protection ? sb1, sb0 the read/write protection setting in par- allel prom mode 00: 11: enable a read/write protection ? note 1: make sure to set "1" to the bit 7, 6, 5, 4 and 3 of the c register. tmp89fw20a page 431 2012/5/18 ra000
note 2: security program is not be disabled even if "1" is set to the bit that a value is already "0". note 3: set "1" to the bits that the security program is not enabled. note 4: make sure not to set "0" to the bits that a value is already "0". for example, if sb1 and sb0 are already "0", and you would like to clear the sb2 from "1" to "0", set "1" to the bit 1 and bit 0, and clear "0" to the bit 2. 24.5.7 .bterssp this api disables security program for the flash memory. enable code (0xd5) must be preliminarily set to the a register. after disabling the security program, if the flash memory does not become busy state (in the case "0xd5" is not set to the a register, etc.), "0x01" (no busy error) is returned to the a register. if the process is completed successfully, a return value is "0xff". 24.5.8 .btconvadr this api converts the address from 0x01000 through 0x1ffff specified in the c register and the wa reg- ister to the address 0x08000 through 0x0ffff, writes the data in the wa register, and then set flscr1. tmp89fw20a 24. flash memory 24.5 api (application programming interface) page 432 2012/5/18 ra000
24.5.9 .btcalcuart this api calculates the proper setting for baud rate of uart from the value of the c register and the wa register. a count value captured by the 16-bit timer counter in the pulse width measurement mode is set as the wa register. be sure to select 2/fcgck as the source clock for 16-bit timer and capture the 8-bit pulse. set 0x08 to the c register. rxd pin can be used as tca pin. to capture the value, set the rxd pin as tca pin using ser- sel temporarily. after capturing, be sure to resume the pin to rxd pin. the possible value range for the wa register is from 0x0020 through 0x3bff. if the contents of the wa reg- ister is out of the range, the api returns the wa register with the contents of 0xffff as return value. if the con- version is made properly, the value of uartcr2 is returned to the bits 5, 4 and 3 of the w regis- ter, and uartdr to the a register as return values. the api sets the bits other than 5, 4 and 3 to "0". there- fore, set the proper value for uartcr2. note 1: if the captured value of the wa register is so small (in the range of baud rates cannot be generated by uart), an error of return values becomes large and the appropriate baud rate may not be generated. note 2: when the internal high-frequency oscillation (fosc) is used, the maximum baud rate calculated by the api is as shown in table 24-10. table 24-10 maximum baud rate with internal oscillation (fosc) clock gear [hz] maximum baud rate [bps] fcgck = fosc / 1 76800 fcgck = fosc / 2 38400 fcgck = fosc / 4 19200 the following procedure shows an example of how to calculate the transfer clock of uart in mcu mode by using the support program of bootrom (api). 1. enable the timer counter input to be also used as rxd input by using the serial interface selection con- trol register sersel. 2. set 16-bit timer counter to pulse pulse width measurement mode. and set falling-edge/l level as an external trigger and select fcgck/2 as the source clock. 3. receive fixed data (0x80) from a master device via rxd pin. it is not necessary to enable uart. 4. write the captured value into the wa register. since the registers (de, bc and ix) are rewritten in the support program, the contents of these registers should be saved before calling the support pro- gram. 5. set the interrupt master enable flag to "disable" (di) (imf "0"). 6. set "0xd5" on flscr2 after setting flscr1 to "1". 7. set "0x08"(8-bit length) to the c register. 8. call .btcalcuart(0x101e). 9. set bits 5, 4 and 3 of the w regiser to uartcr2 and store the a register to uartdr. if the value of the wa register is 0xffff which indicates an error of calculation, retry the execu- tion from receiving the data (0x80). 10. set "0xd5" to flscr2 after setting flscr1 to "0". tmp89fw20a page 433 2012/5/18 ra000
note 1: if registers (wa,bc,de and ix register) is used in non-maskable interrupt subroutine, occurring of non- maskable interrupt may cause unexpected result. note 2: with success of calculation, this api returns "0" into the w register, 7, 6, 2, 1 and 0, as return values. there- fore, set proper value for these bits to select noise cancel time and receive stop bit length. (example) capture the low width of 8 bit value via rxd0 pin using the 16-bit timer counter (tca0) which is set to the pulse width measurement mode. and calculate baud rate for uart from the captured value. .btcalcuart equ 0x101e ; calculate baud rate for uart calcuart secion code abs = 0x1f000 ; #### set timer counter input to be also used as uart receive input #### ld (sersel),0x40 ; switch to tca0 input ; #### receive data (0x80) from a master device #### ld (ta0mod), 0x5e ; set the pulse width measurement mode and select falling edge/l level for ; external trigger ; select fcgck/2 as source clock stimerstart: ld (ta0cr), 0x01 ; timer start : : receives fixed data (0x80) via tca0 pin. : : ld wa,(ta0drl) ; write the captured data into the wa register ld (ta0cr), 0x00 ; timer stop di ; #### allocate bootrom to the data/code area #### ld (flscr1),0x50 ; set barea to "1" ld (flscr2),0xd5 ; reflect the flscr1 setting ; #### calculation for uart setting (api) #### ld c,0x08 ; the number of bit length (8 bit) call (.btcalcuart) ; calculate the uart setting data cmp w, 0xff j z, stimerstart ; if the value of the w register is "0xff", retry the execution of ; receiving ; data. ; #### set the calculated result to uart control register #### ld (uartcr2),w ; set rtsel ld (uartdr), a ; set baud rate register ; #### end process #### ld (flscr1),0x40 ; set barea to "0" ld (flscr2),0xd5 ; reflect the flscr1 setting 24.5.10 .btupdsd update the contents of the shadow ram. the address to return to must be preliminarily set in the wa reg- ister. after updating the shadow ram, it returns to the address specified in the wa register. however, if 0xffff is set to the wa register, it returns to the 2-byte address (next address of call instruction) stack in sp. if you would like to call this api with call instruction and start the next instruction after updating the shadow ram, set 0xffff to the wa register. tmp89fw20a 24. flash memory 24.5 api (application programming interface) page 434 2012/5/18 ra000
(example) update the shadow ram, and run a program from 0x1f900 .btupdsd equ 1022 updsd secion code abs = 0x1f800 : : ld wa,0xf900 call (.btupdsd) tmp89fw20a page 435 2012/5/18 ra000
tmp89fw20a 24. flash memory 24.5 api (application programming interface) page 436 2012/5/18 ra000
25. shadow ram 25.1 configuration shadow ram is mapped to addresses 0x0fc00 to 0x0ffff (1024 bytes) in the data area and 0x1f800 to 0x1ffff (2048 bytes) in the code area in the memory map. upon reset, the contents of the flash memory at these locations are automatically copied into the shadow ram. after reset release, when a read or fetch instruc- tion is executed on these locations, data is read from the shadow ram. when shadow ram is not mapped, the above locations can be mapped as data ram (3072 bytes at 0x01000 to 0x01bff) separately from the internal ram (3072bytes at 0x00040 to 0x00c3f ) by setting the appropriate reg- ister. it is also possible to map neither shadow ram nor data ram. figure 25-1 shows the configuration of the shadow ram control circuits. figure 25-1 configuration of the shadow ram control circuits tmp89fw20a page 437 2012/5/18 ra000 cpu 0 1 shadow ram control circuit address bus 0 1 flash memory shadow ram watchdog timer 0 1 address bus copying in progress copying in progress or reading shadow ram area address bus data bus each interrupt watchdog timer interrupt data bus data bus interrupt control circuit
25.2 control the shadow ram control circuits are controlled by the shadow ram control registers 1 and 2 (sdwcr1 and sdwcr2). shadow ram control register 1 sdwcr1 (0x00f7c) 7 6 5 4 3 2 1 0 bit symbol flsoff flswue dadis dawren expram sdwdis sdwbsy sdwcpy read/write r/w r r/w r/w r/w r/w r w after reset 0 1 0 0 0 0 0 0 flsoff flash memory power control 0 : 1 : connect the flash memory power supply disconnect the flash memory power supply flswue flash memory power warm-up end flag 0 : 1 : warming up or the power supply disconnected warm-up complete or the power supply connected dadis shadow ram mapping control in the data area sdwdis="0" sdwdis="1" 0 : enable mapping of shadow ram in the data area ? 1 : disable mapping of shadow ram in the data area ? dawren shadow ram write control in the data area wsdwdis="0" sdwdis="1" dadis="0" dadis="1" 0 : disable writing to shadow ram in the data area ? 1 : enable writing to shad- ow ram in the data area ? expram data ram mapping control sdwdis="0" sdwdis="1" 0 : ? disable mapping of data ram at 0x01000 to 0x01bff 1 : ? enable mapping of da- ta ram at 0x01000 to 0x01bff sdwdis shadow ram mapping control 0 : 1 : enable mapping of shadow ram disable mapping of shadow ram sdwbsy copy flag 0 : 1 : copying complete copying in progress sdwcpy start copying the contents of flash memory into shadow ram 0 : 1 : ? start copying note 1: bit 0 of sdwcr1 is read as "0". note 2: sdwcr1 and are double-buffered. the values written to these bits are reflected in the shift reg- ister by writing 0x3b to the sdwcr2 register. in other words, the settings of sdwcr1 and do not take effect until 0x3b is written to the sdwcr2 register. tmp89fw20a 25. shadow ram 25.2 control page 438 2012/5/18 ra000
shadow ram control register 2 sdwcr2 (0x00f7d) 7 6 5 4 3 2 1 0 bit symbol sdwcmd read/write write only after reset 0 0 0 0 0 0 0 0 sdwcmd sdwcr1< sdwdis> setting enable 0x3b : other enable the values written to sdwcr1 and reserved note 1: sdwcr2 is read as 0x00. note 2: a value newly written to sdwcr1 takes effect only when an instruction to write 0x3b to sdwcr2 is execu- ted in one of the following areas. if an instruction to write 0x3b to sdwcr2 is executed in any other area, a value new- ly written to sdwcr1 cannot be enabled and the setting of sdwcr1 remains unchanged. - bootrom - ram area (0x00040 to 0x00c3f) when rarea = "1" - shadow ram area note 3: a value newly written to sdwcr1 takes effect only when an instruction to write 0x3b to sdwcr2 is exe- cuted in one of the following areas. if an instruction to write 0x3b to sdwcr2 is executed in any other area, a value newly written to sdwcr1 cannot be enabled and the setting of sdwcr1 remains unchanged. - bootrom - ram area (0x00040 to 0x00c3f) when rarea = "1" - flash memory area tmp89fw20a page 439 2012/5/18 ra000
25.3 memory map the following shows how 3072 kbytes of ram are mapped depending on the settings of sdwcr1, and < expram>. 0x00000 sfr1 (64 bytes) 0x10000 0x00000 sfr1 (64 bytes) 0x10000 0x0003f 0x0003f 0x00040 ram (3072bytes) 0x00040 ram (3072 bytes) 0x00c3f 0x00c3f read as 0xff read as 0xff 0x00e40 sfr3 (192 bytes) flash (63488 bytes) 0x00e40 sfr3 (192 bytes) flash (63488 bytes) 0x00eff 0x00eff 0x00f00 sfr2 (256 bytes) 0x00f00 sfr2 (256 bytes) 0x00fff 0x00fff flash (60416 bytes) flash (61440 bytes) 0x1f7ff 0x1f7ff 0x1f800 shadow ram (2048 bytes) 0x1f800 shadow ram (2048 bytes) 0x0fc00 shadow ram (1024 bytes) 0x0ffff 0x1ffff 0x0ffff 0x1ffff data area code area data area code area sdwcr1 = "0" sdwcr1 = "0" sdwcr1 = "0" sdwcr1 = "1" 0x00000 sfr1 (64 bytes) 0x10000 0x00000 sfr1 (64 bytes) 0x10000 0x0003f 0x0003f 0x00040 ram (3072 bytes) 0x00040 ram (3072bytes) 0x00c3f 0x00c3f read as 0xff read as 0xff 0x00e40 sfr3 (192 bytes) flash (65536 bytes) 0x00e40 sfr3 (192 bytes) flash (65536 bytes) 0x00eff 0x00eff 0x00f00 sfr2 (256 bytes) 0x00f00 sfr2 (256 bytes) 0x00fff 0x00fff 0x01000 flash (61440 bytes) 0x01000 ram (3072 bytes) 0x01bff flash (58368 bytes) 0x0ffff 0x1ffff 0x0ffff 0x1ffff data area code area data area code area sdwcr1 = "1" sdwcr1 = "0" sdwcr1 = "1" sdwcr1 = "1" figure 25-2 memory map tmp89fw20a 25. shadow ram 25.3 memory map page 440 2012/5/18 ra000
25.4 functions 25.4.1 copying the flash memory upon reset, the contents of addresses 0x0fc00 to 0x0ffff (1024 bytes) in the data area and 0x1f800 to 0x1ffff (2048 bytes) in the code area of the flash memory are automatically copied into the shadow ram (figure 25-3). after reset release, if the contents of the shadow ram are rewritten or need to be refreshed, the contents of the flash memory can be copied into the shadow ram by setting sdwcr1 to "1". if an interrupt occurs while the contents of the flash memory are being copied into the shadow ram, the op- eration varies depending on the interrupt source as shown in table 25-1. table 25-1 interrupt operation during copying interrupt source operation when an interrupt occurs while the flash contents are being copied software interrupt (intswi) undefined instruction interrupt (intundef) an interrupt is accepted during copying. however, because the vector area in the shadow ram cannot be read during copying, the vector area must be mapped in the internal ram in advance through the setting of syscr3. watchdog timer interrupt (intwdt) an interrupt is ignored. because an interrupt request is not latched, no intwdt in- terrupt occurs upon completion of copying. when the up counter of the watchdog tim- er overflows, it is initialized to "0" and continues counting. (since the timeout period of the watchdog timer is much longer than the copying time, clearing the watchdog timer immediately before the start of copying normally prevents any intwdt interrupt during copying. ) other maskable interrupts an interrupt is not accepted even when imf (interrupt master enable flag) is set to "1". however, when imf is set to "1", an interrupt request is latched and it is serv- iced upon completion of copying. note 1: while the contents of the flash memory are being copied (sdwcr1 = "1"), no access is al- lowed to the flash memory and shadow ram. during that period, use api subroutines of the boot- rom or place the program in the ram area (0x00040 to 0x00c3f) and wait there until copying is comple- ted. note 2: while the contents of the flash memory are being copied (sdwcr1 = "1"), a read or fetch from the flash memory or shadow ram returns 0xff. note 3: while the contents of the flash memory are being copied (sdwcr1 = "1"), do not activate idle1, idle 2 or sleep1 mode. because no maskable interrupt can be accepted during copying, there is no means of exiting idle1, idle2 or sleep1 mode to return to normal or slow mode. note 4: before copying the contents of the flash memory, make sure that the flash memory is properly pow- ered (sdwcr1="0" and sdwcr1="1"). if copying is started before the power sup- ply has warmed up or the flash memory is powered off during copying, the contents of the flash memo- ry cannot be copied properly. figure 25-3 copy operation timing at reset tmp89fw20a page 441 2012/5/18 ra000 internal reset p10 / reset (external reset) shadow ram reset sdwcr1 address counter 0x000 0x000 0x2ff copying the contents of flash memory into shadow ram warming up period
the time required for copying the contents of the flash memory into the shadow ram is expressed by the following equation: tcpy = 3072 / (fcgck 4 ) [s] after sdwcr1 is set to "1", whether or not copying is completed can be checked by monitor- ing sdwcr1. tmp89fw20a 25. shadow ram 25.4 functions page 442 2012/5/18 ra000
(example) transfer the shadow ram copy program to the internal ram (0x00200-) to update the shadow ram. if a nonmaskable interrupt (intswi or intundef) occurs while the shadow ram is being up- dated, generate a system clock reset. cramstartadd equ 0x0200 ; ram start address shram section code abs = 0x1f000 ; #### set nonmaskable interrupt vector in ram area #### ld hl,0x01fc ;set interrupt vector for intundef and intswi ldw (hl),sintswi - sramprogstart + cramstartadd ; ####transfer code to ram #### ld hl,cramstartadd ld ix,sramprogstart sramloop: ld a,(ix) ; transfer code from sramprogstart through sramprogend ld (hl),a ; to cramstartadd inc hl inc ix cmp ix,sramprogend j nz,code_addr(sramloop) ; #### allocate ram to code area and switch vector area to ram #### ld (syscr3),0x06 ; set rarea = "1" and rvctr = "1" ld (syscr4),0xd4 ; enable code ; #### update shadow ram #### call cramstartadd ;call the code in ram ; ####next main program execution #### : : ; main program execution j code_addr(xxxxx) ramexe section code abs = 0x2000 ; #### code to be executed in ram #### sramprogstart: ld (sdwcr1), 0x01 ; start copying the contents of flash into shadow ram scploop1: test (sdwcr1).1 ; wait until copying is completed j f, scploop1 ; ret ; return to the main routine ; interrupt service routine sintswi: error processing execution scploop2: test (sdwcr1).1 ; wait until copying is completed j f, scploop2 ; ld (syscr2),0x10 ; generate a system clock reset retn sramprogend: nop tmp89fw20a page 443 2012/5/18 ra000
25.4.2 powering off the flash memory (sdwcr1) the power supply of the flash memory can be turned off by setting sdwcr1 to "1" and writ- ing 0x3b to sdwcr2. the power supply of the flash memory can be turned on by setting sdwcr1 to "0" and writing 0x3b to sdwcr2. after turning on the power supply of the flash memory, it is necessary to wait until the flash memory has warmed up. sdwcr1 should be monitored to determine whether or not the warm-up is comple- ted. the warm-up period is 2 to 4 ms regardless of the operating frequency. note 1: the power supply of the flash memory can be turned off only when the program is executing in the boot rom, ram (0x00040 to 0x00c3f) or shadow ram area. if sdwcr1 and sdwcr2 are set in any other area, those settings are ignored. when an instruction to write 0x3b to sdwcr2 is executed, the area in which the program resides is checked. if the program is executing from an area other than the bootrom, ram or shadow ram, sdwcr1 is cleared to "0". note 2: after the power supply of the flash memory is turned off, a read from the flash memory area returns 0xff. a fetch from the flash memory area causes a software interrupt. (example) turn off the power supply of the flash memory from the shadow ram and switch the operating mode from normal2 to slow1 mode. then, after detecting h level on port p70, turn on the pow- er supply of the flash memory, switch the operating mode from slow1 to normal2 mode, and re- turn to the main routine. shram section code abs = 0x1f800 slow_task: ld (sdwcr1), 0x80 ; turn off the power supply of the flash memory ld (sdwcr2), 0x3b set (syscr1).4 ; syscr2 = 1 (switch to slow2 mode) ; (switch the system clock to low-frequency reference clock) nop ; wait for 2 machine cycles nop clr (syscr2).6 ; syscr2 = 0 (switch to slow1 mode) sloop1: program execution test (p7prd).0 ; poll for rising edge of port p70 j t, code_addr(sloop1) ld (sdwcr1), 0x00 ; turn on the power supply of the flash memory ld (sdwcr2), 0x3b sloop2: test (sdwcr1).6 ; wait until the flash memory has warmed up j t, code_addr(sloop2) ld (wuccr), 0x09 ld (wucdr), 0x9d ; set the warm-up period set (syscr2) .6 ; syscr2 = 1 (switch to slow2 mode) sloop3: test (ill).4 ; wait until the high-frequency clock has warmed up j t, code_addr(sloop3) ld (ill), 0xef ; clear il4 clr (syscr1).4 ; syscr2 = 0 (switch to normal2 mode) ret ; return to the main routine tmp89fw20a 25. shadow ram 25.4 functions page 444 2012/5/18 ra000
25.4.3 shadow ram mapping control in the data area (sdwcr1) when sdwcr1 = "0", setting sdwcr1 to "1" disables the mapping of shadow ram to addresses 0x0fc00 to 0x0ffff in the data area and maps flash memory at these locations. clear- ing sdwcr1 to "0" enables the mapping of shadow ram in the data area. in executing erase and write operations on the flash memory (including api operations of the boot- rom), command sequences or verify operations cannot be performed on addresses 0x0fc00 to 0x0ffff when sdwcr1 is cleared to "0". therefore, to erase or program the flash memory, sdwcr1 must be set to "1" to disable the mapping of shadow ram in the data area. 25.4.4 shadow ram mapping control (sdwcr1) when sdwcr1 is set to "1" and 0x3b is written to sdwcr2, the mapping of shadow ram (0x0fc00 to 0x0ffff in the data area and 0x1f800 to 0x1ffff in the code area) is disabled and flash mem- ory is mapped to these locations. when sdwcr1 is cleared to "0" and 0x3b is written to sdwcr2, shadow ram is mapped to these locations, instead of flash memory. 25.4.5 shadow ram write control in the data area (sdwcr1) when sdwcr1 = "0" and sdwcr1 ="0", setting sdwcr1 to "1" al- lows the cpu to write to the shadow ram mapped in the data area. clearing sdwcr1 to "0" dis- ables writes to the shadow ram in the data area. note that clearing sdwcr1 to "0" does not automatically replace the contents of the shad- ow ram with the contents of the flash memory. if the contents of the shadow ram have been rewritten, dis- crepancies arise between the contents of the shadow ram and those of the flash memory. if the contents of the shadow ram need to match those of the flash memory, the contents of the flash memory must be explic- itly copied into the shadow ram (see "25.4.1 copying the flash memory"). 25.4.6 data ram mapping control (sdwcr1) after the mapping of shadow ram is disabled, setting sdwcr1 to "1" makes 3072 bytes at addresses 0x01000 to 0x01bff to be mapped as data ram, instead of flash memory, separately from the in- ternal ram (3072bytes at 0x00040 to 0x00c3f). when used as data ram, these locations are not affected by syscr3 (cannot be mapped in the code area). in this case, the flash memory cannot be accessed at these locations in the data area. tmp89fw20a page 445 2012/5/18 ra000
tmp89fw20a 25. shadow ram 25.4 functions page 446 2012/5/18 ra000
26. serial prom mode 26.1 outline the tmp89fw20a has a 4-kbyte bootrom (mask rom) for programming flash memory. the boot- rom is available in serial prom mode. the serial prom mode is controlled by the rxd0 / si0, txd0 / so0, mode and reset pins. in serial prom mode, communication is performed via the uart or sio. table 26-1 operating range in serial prom mode parameter min max unit power supply voltage 2.7 5.5 v high frequency 1 16 mhz note 1: high frequency in the above table means that external oscillator is used. note 2: serial prom mode can be used even if external oscillator is not connected to external pin, because system clock is star- ted by internal high frequency after reset. when the clock change command is used, system clock can be changed to external clock. 26.2 security in serial prom mode, two security functions are provided to prevent illegal memory access attempts by a third party: password protection and security program. for more security-related information, refer to "26.12 security". tmp89fw20a page 447 2012/5/18 ra000
26.3 serial prom mode setting 26.3.1 serial prom mode control pins to execute on-board programming, start the device in serial prom mode. table 26-2 shows the pin set- tings for starting the device in serial prom mode. table 26-2 serial prom mode setting pin setting rxd0 / si0 / p21 pin h level txd0 / so0 / p20 pin h level mode and reset pins note:the rxd0/si0/p21 and txd0/so0/p20 pins must be pulled up to the h level until the device starts in serial prom mode. table 26-3 pin functions in serial prom mode pin name (in serial prom mode) input/out- put function pin name (in mcu mode) txd0 / so0 output serial prom mode control/serial data output (note 1) txd0 / so0 / p20 / seg29 rxd0 / si0 input serial prom mode control/serial data input rxd0 / si0 / p21 / seg28 reset input serial prom mode control reset mode input serial prom mode control mode sclk0 input serial clock input (if sio is used) this pin is in the high-impedance state in serial prom mode. if the uart is used, the port input is physically fixed to a specified input level in order to prevent a penetration current. to enable the port in- put, the spcr must be set to "1" by the ram loader control program. sclk0 vdd power supply 2.7 v to 5.5 v avdd power supply connect to vdd. vss power supply 0 v avss power supply connect to vss. varef power supply leave open or apply reference voltage. ports other than rxd0 and txd0 input/ output these ports are in the high-impedance state in serial prom mode. the port input is physically fixed to a specified input level in order to prevent a penetration current (the port input is disa- bled). to enable the port input, the spcr must be set to "1" by the ram loader ocntrol pro- gram. com0 to com3 output the output is at the l level in serial prom mode. vlc power supply connect to vdd or apply an lcd drive voltage. xin input connect a resonator to make these pins self-oscillate. xout output note 1: if other parts are mounted on a user board, they may interfere with data being communicated through these communi- cation pins during on-board programming. it is recommended that these parts be somewhat isolated to prevent the pins from being affected. tmp89fw20a 26. serial prom mode 26.3 serial prom mode setting page 448 2012/5/18 ra000
figure 26-1 serial prom mode pin setting note 1: when using the uart, there is no need to control the sclk0 pin. note 2: for information on other pin settings, refer to "table 26-3 pin functions in serial prom mode". tmp89fw20a page 449 2012/5/18 ra000 vdd sclk0 rxd0 (p21) txd0 (p20) reset mode external contro pull-up resistors xin xout vss gnd tmp89fw20a vdd (2.7 v ~ 5.5 v)
26.4 examples of connections for on-board programming figure 26-2 shows examples of connections for on-board programming. figure 26-2 examples of connections for on-board programming note 1: if other parts on a target board interfere with the uart communication in serial prom mode, disconnect these pins by using a jumper or switch. note 2: if the reset control circuit on a target board interferes with the startup of serial prom mode, disconnect the circuit by us- ing a jumper, etc. note 3: for information on other pin settings, refer to "table 26-3 pin functions in serial prom mode". tmp89fw20a 26. serial prom mode 26.4 examples of connections for on-board programming page 450 2012/5/18 ra000 if uart is used serial prom mode mcu mode vdd mode rxd0 (p21) txd0 (p20) reset pc control pull-up resistors level converter xin xout vss gnd external control board target board rc power-on reset circuit reset control other parts (note 1) (note 2) if sio is used serial prom mode mcu mode vdd mode si0 (p21) so0 (p20) reset pull-up resistors microcomputer etc. xin xout vss gnd external control board target board rc power-on reset circuit reset control other parts (note 1) (note 2) sclk0 (p22) tmp89fw20a tmp89fw20a vdd (2.7 v ~ 5.5 v) vdd (2.7 v ~ 5.5 v)
26.5 starting in serial prom mode to start the device in serial prom mode, follow the steps below. for information on the detailed timing, refer to "26.14.1 reset timing". 1. supply power to the vdd pin. 2. set the reset and mode pins to low. 3. set the rxd0/si0/p21 and txd0/so0/p20 pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset and mode pins from low to high. 6. input the matching data 0x86 or 0x30 to the rxd0/si0/p21 pin after the setup period has elapsed. tmp89fw20a page 451 2012/5/18 ra000
26.6 interface specifications the serial prom mode supports two communication methods: uart and sio. the communication method is selected based on the first serial data value received after a reset. to execute on-board programming, the communication format of the external controller (personal computer, mi- crocontroller, etc.) must be set as described below. 26.6.1 sio communication - transfer rate: 250 kbps (max) - data length: 8 bits - slave (external clock) - hardware flow control (sc0 pin) if the tmp89fw20a receives serial data "0x30" after a reset, it starts the sio communication. in the sio communication, the tmp89fw20a functions as a slave device. therefore, the external control- ler must supply the tmp89fw20a with serial clock pulses (via the sclk0 pin) for synchronization. if the tmp89fw20a is not outputting serial data, it controls the hardware flow by using the so0 pin. if in- ternal data processing is not completed yet, though data has been received, the so0 pin outputs the l level. if internal data processing has progressed to a near-completion state or if it has been completed, the sc0 pin out- puts the h level. the external controller must check the status of the sc0 pin before it starts to supply serial clock pulses. 26.6.2 uart communication - baud rate: 9600 to 115200 bps (automatic detection) - data length: 8 bits (lsb first) - parity bit: none - stop bit: 1 bit if the tmp89fw20a receives serial data "0x86" after a reset, it starts the uart communication. it also measures the pulse width of the received data (0x86), and automatically establishes the reference baud rate. in all subsequent data communication transactions, this reference baud rate is used. for information on the com- munication timings of each operation command, refer to "26.14 ac characteristics (uart)". usable baud rates differ depending on the operating frequency and are shown in table 26-4. however, there is the possibility of data communication not working properly, even if a baud rate shown in table 26-4 is used, because data communication is affected by frequency errors of both a resonator and external control- ler (personal computer, etc.), the load capacity of a communication pin, and various other factors. tmp89fw20a 26. serial prom mode 26.6 interface specifications page 452 2012/5/18 ra000
table 26-4 usable baud rates as a general guideline 9600 bps 19200 bps 38400 bps 57600 bps 115200 bps 16 mhz 10 mhz 8 mhz 7.3728 mhz 6.144 mhz ? ? 6 mhz 5 mhz ? ? 4.9152 mhz ? 4.19 mhz ? ? 4 mhz 2 mhz ? 1 mhz ? ? ? note 1: : can be used, ? : cannot be used. note 2: high frequency in the above table means that external oscillator is used. when the internal high frequen- cy is used, baud rate should be set to 76800bps or less. tmp89fw20a page 453 2012/5/18 ra000
26.7 memory mapping figure 26-3 shows memory maps in serial prom mode and mcu mode. in serial prom mode, the bootrom (mask rom) is mapped to 0x1000 through 0x17ff in the data area and 0x1000 through 0x1fff in the code area respectively. to program or erase flash memory with a user-created program by using the ram loader (0x60) command, you need to switch between memory areas through the flash memory control registers (flscr1 and flscr2). for information on how to specify addresses, refer to the chapter on "flash memory". when the flash memory write (0x30) command or the flash memory erase (0xf0) command is executed, the bootrom automatically converts addresses. therefore, the flash memory is addressed at 0x01000 through 0x1ffff as in mcu mode (when flscr1="0"). figure 26-3 memory mapping tmp89fw20a 26. serial prom mode 26.7 memory mapping page 454 2012/5/18 ra000 0x0ffff data area if flscr1=?0? (mcu mode) code area 0x0003f 0x00000 0x10000 0x00040 01000h 0x1ffff 0x0ffff data area if flscr1=?1? (mcu mode) code area 0x0003f 0x00000 0x00040 0x01800 0x017ff 0x01000 1ffffh 0x10000 0x11800 0x10fff 0x117ff 0x11000 0x0ffff 0x0003f 0x00000 0x00040 0x01800 0x017ff 0x01000 0x1ffff 0x10000 0x12000 0x10fff 0x11fff 0x11000 bootrom (2048 bytes) bootrom (2048 bytes) bootrom (2048 bytes) bootrom (4096 bytes) flash sfr ram ram sfr sfr flash flash flash flash flash flash flash ram if serial prom mode data area code area
26.8 operation commands in serial prom mode, the commands shown in table 26-5 are used. after a reset is released, the tmp89fw20a goes into a standby state and awaits arrival of matching data 1 (0x86 or 0x30). table 26-5 operation commands in serial prom mode command data operation command description 0x86 or 0x30 setup (matching data 1, 2) after a reset is released, the serial prom mode always starts operation with this command. if matching data 1 is 0x86, communication starts in the uart format. if match- ing dta 1 is 0x03, communication starts in the sio format. 0xf0 flash memory erase data in the flash memory area (addresses 0x01000 through 0x1ffff) can be erased. 0x30 flash memory write data can be written to the flash memory area (addresses 0x01000 through 0x1ffff). 0x40 flash memory read data can be read from the flash memory area (addresses 0x01000 through 0x1ffff). 0x60 ram loader data can be written to a specified ram area (addresses 0x0060 through 0x0c3f). 0x90 flash memory sum output the 2-byte checksum of the entire flash memory (addresses 0x01000 through 0x1ffff) is output from the upper byte followed by the lower byte. 0xc0 product id code output product id codes are output. 0xc3 flash memory status output the security program status and other status codes are output. 0xfa flash memory security setting this command enables security program. 0xa0 clock change this command is used to change the system clock and baud rate. each command is outlined below. for detailed information on how each command works, refer to 26.8.1 and sub- sequent sections. 1. flash memory erase command either chip erase (erasing the entire flash memory) or sector erase (erasing in 32- kbyte or 28-kbyte units) can be used to erase the flash memory. data in the erase area is 0xff. when security program is en- abled or the option code epfc_op is set to 0xff, sector erase cannot be executed. to disable security pro- gram, execute chip erase. the tmp89fw20a performs password authentication before erasing the flash memory except when the product is blank or epfc_op is 0xff. the flash memory erase command can on- ly be executed after successful password authentication. 2. flash memory write command data can be written in 128-kbyte units to specified addresses in the flash memory. the external control- ler should transmit the data to be written as binary data in intel hex format. if no error occurs until the end record is reached, the tmp89fw20a calculates the checksum of the entire flash memory (0x01000 through 0x1ffff), and returns the result. when security program is enabled, the flash memory write com- mand cannot be executed. in this case, execute chip erase beforehand by using the flash memory erase com- mand. the tmp89fw20a performs password authentication before executing the flash memory write com- mand except when the product is blank. the flash memory write command can only be executed after suc- cessful password authentication. 3. flash memory read command data can be read from a specified address in the flash memory in single-byte units. the external control- ler should transmit the start address from where data is to be read and the number of bytes to be read. the tmp89fw20a outputs the specified number of bytes, then calculates the checksum and returns the re- sult. when security program is enabled, the flash memory read command cannot be executed. in this case, execute chip erase beforehand by using the flash memory erase command. the tmp89fw20a per- tmp89fw20a page 455 2012/5/18 ra000
forms password authentication before executing the flash memory read command except when the prod- uct is blank. the flash memory read command can only be executed after successful password authentica- tion. 4. ram loader command the ram loader transfers the intel hex format data sent by the external controller to the built-in ram. if the transfer is completed successfully, the tmp89fw20a calculates the checksum and returns the result. then, it jumps to the ram address specified by the first data record and starts to execute the user program. when security program is enabled, the ram loader command cannot be executed. in this case, execute chip erase beforehand by using the flash memory erase command. the tmp89fw20a per- forms password authentication before executing the ram loader command except when the product is blank. the ram loader command can only be executed after successful password authentication. 5. flash memory sum output command this command calculates the checksum of the entire flash memory (0x01000 through 0x1ffff) and re- turns the result. 6. product id code output command this is a code to output used to identify a product. the output code consists of information on the rom area and the ram area respectively. the external controller reads this code to identify the product to which data is to be written. 7. flash memory status output command the status of 0x1ffe0 through 0x1ffff and that of the security program are output. the external con- troller reads this code to identify the status of flash memory. 8. flash memory security setting command this command is used to prohibit reading from or writing to the flash memory in parallel mode and writ- ing to the flash memory in mcu mode. in serial prom mode, the flash memory write, ram loader and flash memory read commands are prohibited. to disable security program, execute chip erase by us- ing the flash memory erase command. 9. clock change command this command is used to change the system clock and baud rate clock. the system clock can be selec- ted from the internal high-frequency clock and external high-frequency clock. after the system clock is changed, the baud rate can automatically be set by inputting the reference clock from an external source. tmp89fw20a 26. serial prom mode 26.8 operation commands page 456 2012/5/18 ra000
26.8.1 flash memory erase command (0xf0) table 26-6 shows the flash memory erase command. table 26-6 flash memory erase command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1(0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xf0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xf0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 t0 08 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : mth byte password string - baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted (n-2)th byte erase area specification baud rate after adjustment - (n-1)th byte - baud rate after adjustment ok: checksum (upper byte) (note 3) error: no data transmitted nth byte - baud rate after adjustment ok: checksum (lower byte) (note 3) error: no data transmitted (n+1)th byte (wait for the next operation command data) baud rate after adjustment - note 1: "0xyy 3" means that the device goes into an idle state after transmitting 3 bytes of 0xyy. note 2: for information on the erase area specification, refer to "26.8.1.1 specifying the erase area". for information on the checksum, refer to "26.10 checksum (sum)". for information on the password, refer to "26.12.1 password". note 3: do not transmit a password string if the flash memory has "0xff" at address 0x1fffa or it is blank. (however, the pass- word count storage address and the password comparison start address must be transmitted.) note 4: when the flash memory has "0xff" at address 0x1fffa, sending a value less than 0x80 as the (n-2)th byte (i.e. exe- cuting sector erase) causes the tmp89fw20a to go into an idle state. note 5: when a password error occurs, the tmp89fw20a stops communication and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the reset pin and restart the serial prom mode. note 6: if a communication error occurs during the transfer of a password address or a password string, the tmp89fw20a stops communication and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the reset pin and restart the serial prom mode. tmp89fw20a page 457 2012/5/18 ra000
26.8.1.1 specifying the erase area the (n-2)th byte of the flash memory erase command specifies the area to be erased in the flash memory. the erasec register specifies the address range to be erased. if a value less than 0x80 is specified, sector erase (erasing in 32 or 28-kbyte units) is executed. howev- er, executing sector erase when the data at address 0x1fffa is "0xff" or when security program is ena- bled will cause the device to go into an infinite loop state. if a value equal to or larger than 0x80 is specified, chip erase (erasing the entire flash memory) is exe- cuted. this also clears security program. therefore, to disable security program, execute chip erase in- stead of sector erase. tmp89fw20a 26. serial prom mode 26.8 operation commands page 458 2012/5/18 ra000
erase range (data at [n-2]th byte) 7 6 5 4 3 2 1 0 erasec erasec erase range tmp89fw20a erase range actual address specified by an instruction flscr1 6th address 0x00 reserved 0x01 reserved 0x02 reserved 0x03 reserved 0x04 sector erase (partial erase) 0x01000 to 0x07fff (area d0) 0x01000 01 0x9000 ~ ~ ~ 0x1f 0x07c00 0xfc00 0x20 sector erase (partial erase) 0x08000 to 0x0ffff (area d1) 0x08000 00 0x8000 ~ ~ ~ 0x3f 0x0fc00 0xfc00 0x40 sector erase (partial erase) 0x10000 to 0x17fff (area c0) 0x10000 11 0x8000 ~ ~ ~ 0x5f 0x17c00 0xfc00 0x60 sector erase (partial erase) 0x18000 to 0x1ffff (area c1) 0x18000 10 0x8000 ~ ~ ~ 0x7f 0x1fc00 0xfc00 0x80 or larger chip erase (erasing the entire flash memory) (after the entire flash memory is erased, security program is cleared. ) note 1: if sector erase is performed on a non-existent area of the flash memory, the tmp89fw20a stops communica- tion and goes into an idle state. note 2: if a value indicated as reserved is transmitted, the tmp89fw20a stops communication and goes into an idle state. tmp89fw20a page 459 2012/5/18 ra000
26.8.2 flash memory write command (operation command: 0x30) table 26-7 shows the transfer format of the flash memory write command. table 26-7 transfer format of the flash memory write command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1(0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) : echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x30) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x30) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error:no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error:no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error:no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : mth byte password string (note) - baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted (m+1)th byte : (n-3)th byte intel hex format (binary) baud rate after adjustment - - (n-2)th byte - baud rate after adjustment ok: 0x55 overwrite detected: 0xaa (n-1)th byte - baud rate after adjustment ok: checksum (upper byte) (note 3) error: no data transmitted nth byte - baud rate after adjustment ok: checksum (lower byte) (note 3) error: no data transmitted (n+1)th byte (wait for the next operation command data) baud rate after adjustment - note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. for further information, re- fer to table 26-18. note 2: for information on the intel hex format, refer to "26.11 intel hex format (binary)". for information on the checksum, re- fer to "26.10 checksum (sum)". for information on the password, "26.12.1 password". note 3: if the area 0x1ffe0 through 0x1ffff is all 0xff, password authentication is not performed and, therefore, the pass- word string need not be transmitted. the password count storage address and password comparison start address, however, must be specified, even for a blank product. if the password count storage address and/or password compar- ison start address is/are incorrect, a password error occurs, the tmp89fw20a stops communication, and it goes in- tmp89fw20a 26. serial prom mode 26.8 operation commands page 460 2012/5/18 ra000
to an idle state. therefore, if a password error occurs, initialize the tmp89fw20a by using the reset pin, and re- start the serial prom mode. note 4: if security program is enabled in the flash memory or if a password error occurs, the tmp89fw20a stops communica- tion and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the re- set pin, and restart the serial prom mode. note 5: if a communication error occurs during the transfer of a password address or a password string, the tmp89fw20a stops communication and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. note 6: if the entire flash memory is programmed with the same value, do not write only to addresses 0x1ffe0 to 0x1ffff. if data is only written to these addresses, a password error occurs, and subsequent operations cannot be performed. note 7: the (n-2)th byte is a flag for detecting an overwrite. if addresses to be programmed contain data other than 0xff, the tmp89fw20a sends 0xaa as the (n-2)th byte. (in this case, no write operation is performed.) the checksum to be transmitted at the (n-1)th and nth bytes is calculated from all relevant addresses regardless of whether or not they have been written. therefore, if an overwrite is detected, the checksum of transmitted data does not match the check- sum at the (n-1)th and nth bytes. tmp89fw20a page 461 2012/5/18 ra000
26.8.3 flash memory read command (operation command: 0x40) table 26-10 shows the transfer format of the flash memory read command. table 26-8 transfer format of the flash memory read command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1(0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x40) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x40) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : mth byte password string - baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted (m+1)th byte (m+2)th byte read start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+3)th byte (m+4)th byte read start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+5)th byte (m+6)th byte read start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+7)th byte (m+8)th byte number of bytes to read 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+9)th byte (m+10)th byte number of bytes to read 15 to 08 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted tmp89fw20a 26. serial prom mode 26.8 operation commands page 462 2012/5/18 ra000
table 26-9 transfer format of the flash memory read command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom (m+11)th byte (m+12)th byte number of bytes to read 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+13)th byte : (n-2)th byte baud rate after adjustment baud rate after adjustment memory data memory data (n-1)th byte - baud rate after adjustment ok: checksum (upper byte) error: no data transmitted nth byte - baud rate after adjustment ok: checksum (lower byte) error: no data transmitted (n+1)th byte (wait for the next operation command data) baud rate after adjustment - note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. for further information, re- fer to table 26-18. note 2: for information on the checksum, refer to "26.10 checksum (sum)". for information on the password, refer to "26.12.1 password". note 3: if the area 0x1ffe0 through 0x1ffff is all 0xff, password authentication is not performed and, therefore, the pass- word string need not be transmitted. the password count storage address and password comparison start address, however, must be specified, even for a blank product. if the password count storage address and/or password compar- ison start address are/is incorrect, a password error occurs; the tmp89fw20a stops communication, and goes into an idle state. therefore, if a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. note 4: if security program is enabled in the flash memory or if a password error occurs, the tmp89fw20a stops communica- tion and goes into an idle state. therefore, if a password error occurs, initialize the tmp89fw20a by using the re- set pin, and start the serial prom mode. note 5: if a communication error occurs during the transfer of a password address or a password string, the tmp89fw20a stops communication and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. note 6: if the number of bytes received at the (m+7)th, (m+9)th and (m+11)th bytes is 0x000000 or exceeds the size of inter- nal memory, the tmp89fw20a stops communication and goes into an idle state. tmp89fw20a page 463 2012/5/18 ra000
26.8.4 ram loader command (operation command: 0x60) table 26-10 shows the transfer format of the ram loader command. table 26-10 transfer format of the ram loader command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x60) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x60) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : mth byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (m+1)th byte : (n-2)th byte intel hex format (binary) baud rate after adjustment baud rate after adjustment - - (n-1)th byte - baud rate after adjustment ok: checksum (upper byte) (note 3) error: no data transmitted nth byte - baud rate after adjustment ok: checksum (lower byte) (note 3) error: no data transmitted ram - the program jumps to the start address of ram in which the first transferred data is written, and executes itself. note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. for further information, re- fer to table 26-18. note 2: for information on the intel hex format, refer to "26.11 intel hex format (binary)". for information on the checksum, re- fer to "26.10 checksum (sum)". for information on the password, refer to "26.12.1 password". note 3: if the area 0x1ffe0 through 0x1ffff is all 0xff, password authentication is not performed and, therefore, the pass- word string need not be transmitted. the password count storage address and password comparison start address, however, must be specified, even for a blank product. if the password count storage address and/or password compar- ison start address are/is incorrect, a password error occurs; the tmp89fw20a stops communication and goes into an idle state. therefore, if a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. tmp89fw20a 26. serial prom mode 26.8 operation commands page 464 2012/5/18 ra000
note 4: after sending a password string, do not send the end record only. if the tmp89fw20a receives the end record after re- ceiving a password string, it may malfunction. note 5: if security program is enabled in the flash memory or if a password error occurs, the tmp89fw20a stops communica- tion and goes into an idle state. therefore, if a password error occurs, initialize thetmp89fw20a by using the re- set pin, and restart the serial prom mode. note 6: if a communication error occurs during the transfer of a password address or password string, the tmp89fw20a stops communication and goes into an idle state. therefore, when a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. tmp89fw20a page 465 2012/5/18 ra000
26.8.5 flash memory sum output command (operation command: 0x90) table 26-11 shows the transfer format of the flash memory sum command. table 26-11 transfer format of the flash memory sum output command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x90) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x90) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte - baud rate after adjustment 0x55 : ?| 0xaa: all data are 0xff. 8th byte - baud rate after adjustment ok: checksum (upper byte) (note 2) error: no data transmitted 9th byte - baud rate after adjustment ok: checksum (lower byte) (note 2) error: no data transmitted 10th byte (wait for the next operation command data) baud rate after adjustment - note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. for further information, re- fer to table 26-18. note 2: for information on the checksum, refer to "26.10 checksum (sum)". note 3: if data to be included in the checksum are all 0xff, the 7th byte becomes 0xaa. if data to be included in the check- sum contain any byte that is not 0xff, the 7th byte becomes 0x55. tmp89fw20a 26. serial prom mode 26.8 operation commands page 466 2012/5/18 ra000
26.8.6 product id code output command (operation command: 0xc0) table 26-12 shows the transfer format of the product id code output command. table 26-12 transfer format of the product id code output command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1(0x86 or 0x30) - automatic adjustment baud rate after adjustment -(automatic baud rate adjustment) ok:echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xc0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xc0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte baud rate after adjustment 0x3a start mark 8th byte baud rate after adjustment 0x13 number of transfer data (from 9th to 27th bytes) 9th byte baud rate after adjustment 0x03 length of address (3 bytes) 10th byte baud rate after adjustment 0xfc reserved 11th byte baud rate after adjustment 0x05 reserved 12th byte baud rate after adjustment 0x00 reserved 13th byte baud rate after adjustment 0x00 reserved 14th byte (note 3) 0xf8 rom size code 15th byte baud rate after adjustment 0x01 first block count (1 block) 16th byte (note 3) baud rate after adjustment 0x00 first address of rom (upper byte) 17th byte (note 3) baud rate after adjustment 0x10 first address of room (middle byte) 18th byte (note 3) baud rate after adjustment 0x00 first address of rom (lower byte) 19th byte (note 3) baud rate after adjustment 0x10 end address of rom (upper byte)) 20th byte (note 3) baud rate after adjustment 0xff end address of rom (middle byte) 21th byte (note 3) baud rate after adjustment 0xff end address of rom (lower byte) 22nd byte (note 3) baud rate after adjustment 0x00 first address of ram (upper byte) 23rd byte (note 4) baud rate after adjustment 0x00 first address of ram (middle byte) 24th byte (note 4) baud rate after adjustment 0x60 first address of ram (lower byte) 25th byte (note 4) baud rate after adjustment 0x00 end address of ram (upper byte) 26th byte (note 4) baud rate after adjustment 0x0c end address of ram (middle byte) 27th byte (note 4) baud rate after adjustment 0x3f end address of ram (lower byte) 28th byte baud rate after adjustment checksum of transfer data (complement of 2 of the sum total from 9th through 27th bytes) 29th byte (wait for the next operation command data) baud rate after adjustment - note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. for further information, re- fer to table 26-18. note 2: the rom size code at the 14th byte is shown in table 26-13. note 3: the 16th through 21st bytes show the range of addresses in flash memory where data can be written. note 4: the 22th through 27th bytes show the flash memory area and ram area that can be used by the ram loader. be- cause the range of addresses shown here does not include the work area used by bootrom, it is smaller than the size of a ram built into an actual product. tmp89fw20a page 467 2012/5/18 ra000
table 26-13 rom size code (14th byte) 7 6 5 4 3 2 1 0 romsize "0" "0" "0" tmp89fw20a?k?l(1111 1000) romsize flash memory size 00010 : 4 kbytes 00100 : 8 kbytes 01000 : 16 kbytes 10000 : 32 kbytes 11000 : 48 kbytes 11110 : 60 kbytes 10001 : 96 kbytes 11111 : 124 kbytes read only tmp89fw20a 26. serial prom mode 26.8 operation commands page 468 2012/5/18 ra000
26.8.7 flash memory status output command (0xc3) table 26-14 shows the transfer format of the flash memory status output command. table 26-14 flash memory status output command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1(0x86 or 0x30) - automatic adjustment baud rate after adjustment -(automatic baud rate adjustment) ok:echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xc3) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xc3) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte baud rate after adjustment 0x3a start mark 8th byte baud rate after adjustment 0x04 byte count (from 9th to 12 bytes) 9th byte baud rate after adjustment status code 1 10th byte baud rate after adjustment status code 2 11th byte baud rate after adjustment 0x00 reserved 12th byte baud rate after adjustment 0x00 reserved 13th byte baud rate after adjustment checksum (complement of 2 of the sum total from 9th through12th bytes) 14th byte (wait for the next operation command data) baud rate after adjustment - note 1: "0xyy 3" means that the device goes into an idle state after transmitting 3 bytes of 0xyy. note 2: for detailed information on status codes 1 and 2, refer to "26.8.7.1 flash memory status code". tmp89fw20a page 469 2012/5/18 ra000
26.8.7.1 flash memory status code the flash memory status code is 7-byte data. if shows the status of security program and the status of ad- dresses 0x1ffe0 through 0x1ffff. table 26-15 flash memory status code data description in the case of tmp89fw20a 1st start mark 0x3a 2nd number of transfer data (4 bytes from 3rd through 6th bytes) 0x04 3rd status code 1 see below. 4th status code 2 see below. 5th reserved 0x00 6th reserved 0x00 7th checksum of transfer data (complement of 2 of the sum total of 3rd through 6th bytes) if 3rd data is 0x00, then checksum is 0x00. if 3rd data is 0x01, then checksum is 0xff. if 3rd data is 0x02, then checksum is 0xfe. if 3rd data is 0x03, then checksum is 0xfd. status code 1 7 6 5 4 3 2 1 0 epfc dafc rpena blank initial value (**** ****) epfc password string evaluation when the flash memory erase command is executed (status of 0x1fffa) 0: 1: do not evaluate password string. (evaluate pnsa and pcsa on- ly.) evaluate password string, pnsa and pcsa. dafc security program check of the on- chip debugging function (ocd) (sta- tus of 0x1fffb) 0: 1: do not check security program when ocd is activated. check security program when ocd is activated. rpena status of security program in flash memory 0: 1: security program is disabled security program is enabled blank status of 0x1ffe0 through 0x1ffff 0: 1: addresses 0x1ffe0 through 0x1ffff all contain 0xff. addresses 0x1ffe0 through 0x1ffff contain any number of bytes that are not 0xff. status code 2 7 6 5 4 3 2 1 0 "1" "1" "1" "1" "1" sb2 sb1 sb0 initial value (1111 1***) sb2 status of sb2 0: 1: security program is enabled. security program is disabled. sb1 status of sb1 0: 1: security program is enabled. security program is disabled. sb0 status of sb0 0: 1: security program is enabled. security program is disabled. note 1: the value to be read as status code 2 directly reflects the value of product id (0xff7f). note 2: for the definition of each bit, refer to "26.12.2 security program". tmp89fw20a 26. serial prom mode 26.8 operation commands page 470 2012/5/18 ra000
restrictions are placed on the execution of some operation commands depending on the contents of the status code 1. detailed information on this is shown in the table below. when security program is ena- bled, the flash memory write, ram loader, and sector erase commands cannot be executed. before execut- ing these commands, you must perform chip erase. rpena blank epfc dafc flash memory write, flash memory read, and ram loader commands flash memory sum output, product id out- put, and status output commands flash memory erase command flash memory security setting command chip erase sector erase 0 0 0 0 yes yes yes no no 1 0 0 0 ? yes yes no no 0 1 0 * password yes yes no password 1 * password yes password password 1 1 0 * ? yes yes ? password 1 * ? yes password ? password note:yes: the command can be executed. password: password authentication is required for executing the command. no: the command cannot be executed. (after returning echo back to the command, the tmp89fw20a stops communication and goes into an idle state.) tmp89fw20a page 471 2012/5/18 ra000
26.8.8 flash memory security setting command (0xfa) table 26-16 shows the flash memory security command. table 26-16 flash memory security setting command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok:echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xfa) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xfa) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok:no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : mth byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted (n-8)th byte 0x07 baud rate after adjustment - (n-7)th byte 0x00 baud rate after adjustment - (n-6)th byte 0x80 baud rate after adjustment - (n-5)th byte 0x00 baud rate after adjustment - (n-4)th byte 0x00 baud rate after adjustment - (n-3)th byte 0x00 baud rate after adjustment - (n-2)th byte 0x80 baud rate after adjustment - (n-1)th byte security setting value baud rate after adjustment - nth byte checksum (complement of two of the sum total of (n-7) th to (n-1)th bytes) baud rate after adjustment - (n + 1)th byte - baud rate after adjustment ok: 0xfb (note 3) error: no data transmitted (n+2)th byte (wait for the next operation command data) baud rate after adjustment - note 1: "0xyy 3" means that the device goes into an idle state after transmitting 3 bytes of 0xyy. note 2: for information on the password, refer to "26.12.1 password". tmp89fw20a 26. serial prom mode 26.8 operation commands page 472 2012/5/18 ra000
note 3: if the flash memory security setting command is executed for a blank product or if a password error occurs for a non- blank product, the tmp89fw20a stops communication and goes into an idle state. therefore, if a password error oc- curs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. note 4: if a communication error occurs during the transfer of a password address or password string, the tmp89fw20a stops communication and goes into an idle state. therefore, if a password error occurs, initialize the tmp89fw20a by using the reset pin, and restart the serial prom mode. note 5: if security program is disabled in the flash memory, it becomes possible to read rom data freely in parallel prom mode. make sure that you enable security program in mass production. security setting value (nth byte) 7 6 5 4 3 2 1 0 "1" "1" "1" "1" "1" sb2 sb1 sb0 sb2 sb2 security control 0: 1: enable security program ?| (security program remains enabled.) sb1 sb1 security control 0: 1: enable security program ?| (security program remains enabled.) sb0 sb0 security control 0: 1: enable security program ?| (security program remains enabled.) note 1: bits 7 to 3 must be set to "1". note 2: a bit that has been set to "0" (i.e., security program is enabled) must not be set to "0" again. note 3: security program cannot be disabled by writing a "1" to a bit that has been set to "0" (i.e., security program is enabled). note 4: for the definition of each bit, refer to "26.12.2 security program". tmp89fw20a page 473 2012/5/18 ra000
26.8.9 clock change command (operation command: 0xa0) table 26-17 shows the transfer format of the clock change command. table 26-17 transfer format of the clock change command transfer byte transfer data from the external controller to tmp89fw20a baud rate transfer data from tmp89fw20a to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok:echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xa0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xa0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte 0x55 (internal high-frequency clock) 0xaa (external high-frequency clock) baud rate after adjustment baud rate after adjustment - - 0x55 : internal high-frequency clock 0xaa: external high-frequency clock 9th byte 10th byte 0x80 - baud rate after adjustment baud rate after adjustment ok: 0x80 error: no data transmitted 11th byte 12th byte 0xff baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte 0xff baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte - baud rate after adjustment ok: 0x55 error: no data transmitted 16th byte (wait for the next operation command data) baud rate after adjustment - note 1: 0xyy 3 means that the device goes into an idle state after transmitting 3 bytes of 0xyy. note 2: for information on the checksum, refer to "26.10 checksum (sum)". note 3: the 7th byte must be 0x55 or 0xaa. if the system clock is not to be changed, send the value corresponding to the cur- rent clock. the current clock status can be checked with the status code output command. tmp89fw20a 26. serial prom mode 26.8 operation commands page 474 2012/5/18 ra000
26.9 error codes table 26-18 shows the error codes that the tmp89fw20a transmits when it detects errors. table 26-18 error codes data transmitted meaning of error data 0x63, 0x63, 0x63 operation command error 0xa1, 0xa1, 0xa1 framing error in the received data 0xa3, 0xa3, 0xa3 overrun error in the received data note:if a password error occurs, the tmp89fw20a does not transmit an error code. tmp89fw20a page 475 2012/5/18 ra000
26.10 checksum (sum) for the following operation commands, a checksum is returned to verify the result of command execution: - flash memory erase command (0xf0) - flash memory write command (0x30) - flash memory sum output command (0x90) - flash memory read command (0x40) - ram loader command (0x60) - product id code output command (0xc0) - flash memory status output command (0xc3) 26.10.1 calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtained result is returned as a word. in other words, the data is read in byte units and the calculated result is returned in word units. example: 0xa1 for these four bytes, the checksum is calculated as follows: 0xb2 0xa1 + 0xb2 + 0xc3 + 0xd4 = 0x02ea sum (high)= 0x02 sum (low)= 0xea 0xc3 0xd4 in the case of the product id code output command and flash memory status output command, however, a different calculation method is used. for more information, refer to table 26-19. 26.10.2 calculation data table 26-19 shows the data to be included in checksum calculation. table 26-19 data to be included in checksum calculation operation command calculation data note flash memory erase command data in the entire area of flash memory flash memory write command data in the entire area of flash memory even if a part of the flash memory is written, the checksum of the entire flash memory area (0x01000 to 0x1ffff) is cal- culated. the data length, address, record type and check- sum in intel hex format are not included in the checksum. flash memory sum output command flash memory read command data in the read area of flash memory ram loader command ram data written in the first received ram address through the last received ram ad- dress the data length, address, record type and checksum in intel hex format are not included in the checksum. product id code output command 9th through 18th bytes of transferred data for details, refer to "26.8.6 product id code output command (operation command: 0xc0)". flash memory status output command 9th through 12th bytes of transferred data for details, refer to "table 26-14 flash memory status out- put command". tmp89fw20a 26. serial prom mode 26.10 checksum (sum) page 476 2012/5/18 ra000
26.11 intel hex format (binary) for the following two commands, the intel hex format is used in part of the transfer format: - flash memory write command (0x30) - ram loader command (0x60) for information on the definition of the intel hex format, refer to table 26-20. data is in binary form. the start mark ":" must be transmitted as binary data of 0x3a. 1. after receiving the checksum of each data record, the tmp89fw20a goes into a wait state and awaits the arrival of the start mark ":" (0x3a) of the next data record. if the external controller transmits data oth- er than 0x3a between records, the tmp89fw20a ignores such data when it is in this wait state. 2. if a receiving error or intel hex format error occurs, the tmp89fw20a goes into an idle state without re- turning an error code to the external controller. the intel hex format error occurs in the following cases: ? if the record type is other than 0x00, 0x01 or 0x02 ? if a checksum error of the intel hex format occurs ? if the data length of an extended record (record type = 0x02) is not 0x02 ? if the tmp89fw20a receives the data record after receiving an extended record (record type - 0x02) whose segment address is more than 0x2000 ? if the data length of the end record (record type = 0x01) is not 0x00 ? if the offset address of an extended record (record type = 0x02) is not 0x0000 the flash memory contained in the tmp89fw20a is comprised of 922 pages, each page containing 128 bytes. since the flash memory is written page by page (in 128-byte units), if the data to be written to a page is less than 128 kbytes, the page must be filled up with a given value such as 0xff. the data to be written to a page can be divided into multiple data records. however, the external controller must ob- serve the following rules when transferring data. any violation of these rules will cause the device to en- ter an idle state. ? the address specified in the first data record after the flash memory write command (0x30) is accep- ted must be the top address of each page. for example, to write data to page 1, the address speci- fied in the first data record must be 0x1080 (the top address of page 1). ? if the address corresponding to the last byte of the data record is in the middle of a page, the ad- dress to be specified in the next data record must be the last address incremented by one. ? if the address corresponding to the last byte of the data record is the last address of a page, the next record must be an end record or the address to be specified in the next data record must be the top ad- dress of a page. ? the address corresponding to the last byte of the data record immediately before the end record must be the last address of each page. 3. the external controller must be provisioned so that after it transmits the checksum of end record, it goes in- to a wait state and does not transmit any data until the arrival of 3-byte data (overwrite detection, upper and lower bytes of the checksum) in the case of the flash memory write command. (in the case of the ram loader command, the external controller awaits the arrival of 2-byte data, upper and lower bytes of the checksum.) tmp89fw20a page 477 2012/5/18 ra000
table 26-20 definition of the intel hex format (1) (2) (3) (4) (5) (6) start mark data length (1 byte) offset address (2 bytes) record type (1 byte) data checksum (1 byte) data record (record type =00) 3a number of bytes in the data field starting byte stor- age address *specified using big-endian 00 data (1 to 255 bytes) complement of 2 of the sum total of: (2) data length (3) offset address (4) record type (5) data end record (record type = 01) 3a 00 00 00 01 none complement of 2 of the sum total of: (2) data length (3) offset address (4) record type extended record (record type =02) 3a 02 00 00 02 segment address (2 bytes) *specified using big-endian complement of 2 of the sum total of: (3) offset address (4) record type (5) segment address tmp89fw20a 26. serial prom mode 26.11 intel hex format (binary) page 478 2012/5/18 ra000
26.12 security in serial prom mode, two security functions are provided to prohibit illegal memory access attempts by a third party: password authentication and security program. 26.12.1 password password authentication can be performed in serial prom mode and when the on-chip debug (ocd) func- tion is used. arbitrary data in the flash memory (part of user memory) can be specified as a password. when password authentication is enabled in serial prom mode, the operation commands, such as flash memory write and read, cannot be executed without a valid password. when using the ocd function, password authen- tication is required. in parallel prom mode, password authentication is not supported. to apply access restrictions both in seri- al prom and parallel prom modes, you must also use security program. 26.12.1.1 how a password can be specified the tmp89fw20a allows any piece of data in the flash memory (8 or more consecutive bytes) to be specified as a password. password authentication is performed by comparing a password string sent from the external controller with the data string in the flash memory specified as a password. data at addresses 0x01000 through 0x1feff in the flash memory can be specified as a password. 26.12.1.2 password structure a password consists of three components: pnsa, pcsa, and a password string. figure 26-4 shows an ex- ample of how a password is transmitted. ? pnsa (password count storage address) a 3-byte address is specified in the area 0x01000 through 0x1feff. the data at the speci- fied address indicates the number of bytes in the password string. if the data is 0x07 or less or the address is outside the designated range, a password error occurs. the data at the specified address is defined as n here. ? pcsa (password comparison start address) a 3-byte address is specified in the area 0x01000 through (0x1feff - n). this address indi- cates the memory location from where the password string to be compared with a user-entered password. if an address outside the designated range is specified, a password error occurs. ? password string the password string can contain 8 to 255 bytes. a password string sent from the external con- troller is compared with the password string in the flash memory that is located starting from pcsa and contains the number of bytes (n) specified by pnsa. if the comparison result indi- cates no match, or if the password string contains three or more consecutive bytes of the same value, a password error occurs and the tmp89fw20a goes into an idle state. in this idle state, external devices cannot communicate with the tmp89fw20a. to resume communica- tion, the tmp89fw20a must be restarted in serial prom mode by using the reset pin. tmp89fw20a page 479 2012/5/18 ra000
figure 26-4 example of how a password is transmitted tmp89fw20a 26. serial prom mode 26.12 security page 480 2012/5/18 ra000 0x08 0x01 0x02 0x03 0x04 0x05 0x08 0x0f012 0x0f107 0x0f108 flash memory 0x0f109 0x0f10a 0x0f10b 0x0f10c 0x00 0xf0 0x12 0xf1 0x00 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 pnsa pcsa password string 0x06 0x07 0x0f10d 0x0f10e 0x08 is the number of passwords. 8 bytes compare example: pnsa = 0x0f012 pcsa = 0x0f107 0x01,0x02,0x03,0x04,0x05, 0x06,0x07 and 0x08 are assumed. rxd/si pin mcu
26.12.1.3 password setting, clearance and authentication ? password setting since part of a user program is used as a password, no special processing is required in set- ting up the device password. the password is automatically set when a user program is writ- ten to the flash memory. ? password clearance to clear the password, the entire flash memory must be erased by chip erase. when the en- tire flash memory is initialized to 0xff, the password is also cleared. ? password authentication if addresses 0x1ffe0 through 0x1ffff of the tmp89fw20a contain even a single byte of data that is not "0xff", it is determined to be a non-blank product, and password authentica- tion is required to execute operation commands. password authentication is performed by us- ing pnsa, pcsa and a password string. operation commands can be executed only after a val- id password is entered. if password authentication fails, the tmp89fw20a goes into an idle state. if all the bytes at addresses 0x1ffe0 through 0x1ffff are "0xff", the tmp89fw20a is de- termined to be a blank product, and no password authentication is performed. however, pnsa and pcsa (not a password string) are required to execute particular operation com- mands. in this case, pnsa and pcsa must be set in the range shown in table 26-21. whether or not the tmp89fw20a is blank can be checked by executing the status output com- mand. the operation commands that require pnsa and pcsa (and a password string) for them to be executed are as follows: - flash memory erase command (0xf0) - flash memory write command (0x30) - flash memory read command (0x40) - ram loader command (0x60) - flash memory security setting command (0xfa) 26.12.1.4 password values and setting range a password must be set in accordance with the conditions shown in table 26-21. if a password created without meeting these conditions is used, a password error occurs. in this cae, the tmp89fw20a does not transmit any data and goes into an idle state. table 26-21 password values and setting range password blank product (note 1) non-blank product pnsa (password count storage address) 0x01000 pnsa 0x1feff 0x01000 pnsa 0x1feff pcsa (password comparison start ad- dress) 0x01000 pcsa 0x1feff 0x01000 pcsa 0x1ff00 - n n (password count) * 8 n password string not required (notes 4 and 5) required (note 3) note 1: *: dont care. note 2: when addresses from 0x1ffe0 through 0x1ffff are filled with "0sff", the product is recognized as a blank product. tmp89fw20a page 481 2012/5/18 ra000
note 3: a password string must not include three or more consecutive bytes of the same value. (a password error occurs dur- ing password authentication. the tmp89fw20a does not transmit any data and goes into a idle state.) note 4: when the flash memory write command or ram loader command is executed on a blank product, the tmp89fw20a receives intel hex format data immediately after pcsa without receiving any password string. even if the external con- troller sends a dummy password string, the tmp89fw20a ignores received data until the start mark 0x3a (":") of the intel hex format arrives. therefore, the subsequent processing is performed properly. however, if the dummy pass- word string contains "0x3a", it is detected as the start mark erroneously, and the tmp89fw20a goes into an idle state. if this causes any problem, do not transmit a dummy password string. note 5: in executing the flash memory erase command, do not transmit a password string to a blank product. tmp89fw20a 26. serial prom mode 26.12 security page 482 2012/5/18 ra000
26.12.2 security program security program can be used in parallel prom and serial prom modes and with the ocd function. this protection feature is realized by dedicated memory, and a special command is required to enable it. when sb1 and sb0 of security program are enabled, the flash memory cannot be read or written in parallel prom mode. when sb2 is enabled, the execution of the page program command sequence is prohibited in mcu mode. in serial prom mode, enabling any one of sb2 to sb0 prohibits the execution of the flash mem- ory write, ram loader, and flash memory read commands. when the ocd function is used, enabling any one of sb2 to sb0 allows you to select whether to prohibit starting up of the system by an option code or to perform password authentication before starting up the system. 26.12.2.1 how security program works the tmp89fw20a allows read protection to be applied to the flash memory by writing protect informa- tion to the dedicated memory locations (sb2 to sb0). since the dedicated memory locations are provided for security program, no user resources are required. 26.12.2.2 enabling or disabling security program ? enabling security program to enable security program, execute the flash memory security setting command. ? disabling security program to disable security program, execute chip erase by the flash memory erase command. tmp89fw20a page 483 2012/5/18 ra000
26.12.3 option codes the following two option codes can be placed at the designated address in the interrupt vector area to ena- ble or disable password authentication for executing the flash memory erase command and to skip security pro- gram check when the ocd system is started. - erase password free code epfc_op (0x1fffa) the tmp89fw20a allows password authentication to be performed before the flash memory erase command is executed to prevent illegal memory erasure by third parties. by setting the erase password free code (epfc_op), you can enable password authentication for executing the flash mem- ory erase command (0xf0). epfc_op is located to address 0x1fffa in the vector area. to enable password authentication, set epfc_op to a value other than 0xff (typically 0xf0). it is recommen- ded to enable password authentication in mass production. in software development, there is a possibility that a password may get lost due to frequent changes to a program. if this happens, you can execute the flash memory erase command (0xf0) with- out performing password authentication by setting the erase password free code (epfc_op) to 0xff. (even in this case, pnsa and pcsa must be authenticated.) to disable password authentica- tion for executing the flash memory erase command (0xf0), set epfc_op to 0xff. password authentication can be disabled only for chip erase. if sector erase is executed with epfc_op set to 0xff, the tmp89fw20a goes into an idle state. also note that password authenti- cation cannot be disabled for any other operation commands except the flash memory erase command. - ocd security program free code dafc_op (0x1fffb) the tmp89fw20a has the security program feature to prevent illegal memory accesses by third parties. security program, when enabled, blocks any attempts to execute operation commands involving memory access and the startup of the ocd. security program should normally be enabled at the time of shipment. if you want to use the ocd after shipment while preserving the memory contents, you can use the ocd security pro- gram free code (dafc_op) to start the ocd without checking whether or not security program is enabled. (password authentication is still required even in this case.) dafc_op is located at address 0x1fffb in the vector area. to start the ocd without checking the security program status, set dafc_op to 0xff. this enables you to start the ocd by perform- ing only password string authentication irrespective of whether or not security program is enabled. when dafc_op is set to a value other than 0xff, the ocd can only be used when security pro- gram is disabled. when security program is enabled, any attempt to start the ocd causes the tmp89fw20a to stop communication and go into an idle state. to use the ocd while security pro- gram is enabled, chip erase must be performed on the flash memory by executing the flash memo- ry erase command (0xf0).when security program is disabled, the ocd can be started by only per- forming password string authentication. table 26-22 option codes symbol function address set value epfc_op password string authentication when the flash memory erase command is executed 0x1fffa 0xff skip password string authentication (authenticate pnsa and pcsa only) other than 0xff authenticate password string, pnsa, and pcsa. dafc_op security program check when the ocd is started 0x1fffb 0xff skip security program check. other than 0xff perform security program check. tmp89fw20a 26. serial prom mode 26.12 security page 484 2012/5/18 ra000
example :disabling password authentication for the flash memory erase command and security program validation for starting the ocd vector section romdata abs = 0x1fffa db 0xff ; disable password authentication for the flash memory erase ; command (epfc_op code) db 0xff ; skip security program check when starting ocd (dafc_op code) tmp89fw20a page 485 2012/5/18 ra000
26.12.4 recommended settings table 26-23 and table 26-24 show the recommended security program and option code settings. table 26-23 recommended settings for security program device status mcu mode serial prom mode parallel prom mode security program page program command sequence flash memory read, flash memory write and ram loader commands (note 2) page program command sequence/ flash memory read sb2 sb1,sb0 (note 3) software development, debug disable can be executed password authentication is required. can be executed (note 1) enable disable cannot be executed cannot be executed mass production disable enable can be executed cannot be executed enable cannot be executed note 1: when security program is disabled (sb1, sb0=0), rom data can be freely read in parallel prom mode. in mass pro- duction, make sure that you always enable sb1 and sb0. sb1 and sb0 must be enabled. note 2: when a program is executed from ram by using the ram loader command, the page program command sequence cannot be executed as in the case of mcu mode. note 3: security program is enabled when either or both of sb1 and sb0 are set to "0". normally, both sb1 and sb0 should be set to "0". table 26-24 recommended settings for option codes device status serial prom mode parallel prom mode on-chip debug (ocd) option code flash memory erase command chip erase command se- quence sb2 to sb0 are all disa- bled any one of sb2 to sb0 is enabled 0x1fffa (epfc_op) 0x1fffb (dafc_op) software development, debug 0xff 0xff password string authenti- cation is required. can be executed (note 1) can be used can be used other than 0xff cannot be used mass production other than 0xff 0xff password string authenti- cation is required. can be used other than 0xff cannot be used note 1: in parallel prom mode, chip erase can be performed irrespective of the option code or security program setting. tmp89fw20a 26. serial prom mode 26.12 security page 486 2012/5/18 ra000
26.13 flowchart figure 26-5 flowchart tmp89fw20a page 487 2012/5/18 ra000 transmit data (0xa0) receive data change baud rate (automatically changed whether clock changed or not) oscillation begins warming-up receive data receive data (0x80 sampling) oscillation active oscillation stopping receive data=?0xa0? (clock change mode) current external oscillation status transmit data (0x55) transmit data (0x55 or 0xaa) transmit data (0x80) start setup receive data receive data receive data=?0x30? (flash memory write command) receive data=?0x90? (flash memory sum output command) sio mode uart mode uart transmit data (0x86) sio transmit data (0x30) uart transmit data (0x79) transmit data (0x30) transmit data (checksum of the entire area) transmit data (detect double writes) transmit data (detect all 0xff) transmit data (checksum of the entire area) transmit data (0xfb) transmit data (0xf0) transmit data (0x40) sio transmit data (0xcf) receive data =0x86 receive data =0x30 0x86 receive data =0x79 receive data receive data =0xcf 0xcf 0x79 execute a write calculate checksum closed loop security program check blank check password check ng ok 0x55 : there is no error. 0xaa : there is an error. (double writes are detected) 0x55 : - 0xaa : all data are 0xff. disabled non-blank product blank product enabled receive data=?0x60? (ram loader command) transmit data (0x60) jump to the user proguram in ram execute a write closed loop security program check blank check password check ng ok disabled non-blank product blank product enabled closed loop security program check blank check password check ng ok disabled non-blank product blank product enabled receive data=?0x40? (flash memory read command) blank check non-blank product blank product enables security program closed loop password check ng ok receive data=?0xfa? (security program enable command) transmit data (0xfa) transmit data (0x90) receive data=?0xc0? (product id code output command) transmit data (product id code) transmit data (checksum) transmit data (read data) transmit data (0xc0) receive data=?0xc3? (status output command) transmit data (status) transmit data (0xc3) security program check dafc-op, epfc-op check blank check transmit data (checksum of the erased area) receive data chip erase (erase the entire area) sector erase (erase in 32 (29) kb units) received data received data blank check non-blank product blank product closed loop security program check disabled enabled execute an erase closed loop epfc-op epfc-op password check ng ok 0x20 < 0x20 0xff 0xff perform password check not perform password check = 0xff = 0x55 = 0xaa = 0xff disable security program change clock to external high frequency clock change clock to internal high frequency clock receive data=?0xf0? (flash memory erase command)
26.14 ac characteristics (uart) table 26-25 shows the timing from when the mcu receives data from an external device to when the mcu trans- mits data in return. table 26-25 uart timing -1 parameter symbol time (s) min. typ. max. time from when mcu receives 0x86 to when it echoes back cmeb1 - 583 / fcgck - time when mcu receives 0x79 to when it echoes back cmeb2 - 526 / fcgck - time from when mcu receives an operation command to when it echoes back cmeb3 105 / fcgck - 241 / fcgck time required to calculate the checksum for the flash memory sum output command cmfsm - 5605040 / fcgck - time required to calculate the checksum for the flash memory write command cmfwr - 5456240 / fcgck - time required to perform erasure and calcu- late the checksum for the flash memory erase command chip erase cmfer - (5338530 / fcgck) + 500ms - sector erase - (5338365 / fcgck) + 100ms - time required to calculate the checksum for the ram loader com- mand cmrsm - 150 / fcgck - time from when mcu receives intel hex data to when it sends overwrite detection data cmwr 182 / fcgck - 32000 / fcgck + 1.25ms time from when mcu receives read byte count data to when it sends memory data cmrd - 382 / fcgck - time required to set security by the flash memory security set- ting command (i =number of bits to be set) cmrp - (857 / fcgck ) + (193 x i ) / fcgck + (1.25ms x i ) - time from when mcu re- ceives clock setting data to when it echoes back internal high- frequency external high- frequency external high- frequency oscil- lator stopped cmck1 - 80531 / fcgck (note 3) - external high- frequency oscil- lator active - 93 / fcgck - external high- frequency internal high- frequency internal high- frequency oscil- lator active - 109 / fcgck - time from when mcu receives 0x80 to when it echoes back cmck3 - 570 / fcgck - time from when mcu receives 0xff to when it echoes back cmck5 - 92 / fcgck - note 1: the security setting time (cmrp) varies with the number of bits to be programmed (i = 1 to 3). note 2: the above values indicate the software processing time of the bootrom and may include some errors. note 3: the above values include the warm-up time until oscillation stabilizes and may vary greatly depending on the character- istics of the oscillator to be used. tmp89fw20a 26. serial prom mode 26.14 ac characteristics (uart) page 488 2012/5/18 ra000
table 26-26 shows the time required for the mcu to the acceptance of data. table 26-26 uart timing -2 parameter symbol time (s) min. typ. max. time to hold mode and reset pins low after power-on rssup 10 ms - - time from when mode and reset pins go high to the acceptance of rxd rxsup 20 ms - - time from when mcu echoes back 0x86 to the acceptance of rxd cmtr1 1 / baud - - time from when mcu echoes back 0x79 to the acceptance of rxd cmtr2 (49 / fcgck) + (1 / baud) - - time from when mcu echoes back an operation command to the accept- ance of rxd cmtr3 1 / baud - - time from when the execution of a current command is completed to the ac- ceptance of the next operation command cmnx (751 / fcgck) + (1 / baud) - - time from when mcu echoes back clock setting data to the acceptance of rxd cmck2 (181 / fcgck) + (1 / baud) - - time from when mcu transmits 0x80 to the acceptance of rxd cmck4 (35 / fcgck) + (1 / baud) - - note 1: "1 / baud" indicates the per-bit time of the communication baud rate. note 2: when data is transmitted from an external controller to the mcu, make sure a sufficient margin is secured for each of the timing parameters shown above. tmp89fw20a page 489 2012/5/18 ra000
26.14.1 reset timing figure 26-6 reset timing 26.14.2 flash memory erase command (0xf0) figure 26-7 flash memory erase command tmp89fw20a 26. serial prom mode 26.14 ac characteristics (uart) page 490 2012/5/18 ra000 rxd (0x86) rxsup rssup cmeb1 cmtr1 (0x79) txd reset mode vdd (0x86) (0x79) cmeb2 cmeb3 operation command cmtr2 cmtr3 [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0xf0) cmtr3 [23:16] [15:8] pcsa password string area to be erased checksum [7:0] rxd txd cmnx cmfer next command
26.14.3 flash memory write command (0x30) figure 26-8 flash memory write command 26.14.4 flash memory read command (0x40) figure 26-9 flash memory read command tmp89fw20a page 491 2012/5/18 ra000 [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x30) cmtr3 [23:16] [15:8] pcsa password string intelhex checksum overwrite detection intelhex(end record) [7:0] (0x3a) rxd txd cmwr cmnx cmfwr next command (0x00) (0x00) (0x01) (0xff) (0x55) or (0xaa) [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x40) cmtr3 [23:16] [15:8] pcsa password string read start address checksum memory data [7:0] [23:16] [15:8] [7:0] number of read bytes [23:16] [15:8] [7:0] rxd txd cmnx cmrd next command
26.14.5 ram loader command (0x60) figure 26-10 ram loader command 26.14.6 flash memory sum output command (0x90) figure 26-11 flash memory sum output command 26.14.7 product id code output command (0xc0) figure 26-12 product id code output command tmp89fw20a 26. serial prom mode 26.14 ac characteristics (uart) page 492 2012/5/18 ra000 [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x60) cmtr3 [23:16] [15:8] pcsa password string intelhex checksum intelhex(end record) [7:0] (0x3a) rxd txd execute ram program cmrsm (0x00) (0x00) (0x01) (0xff) cmfsm rxd txd (0x90) (0x55) or (0xaa) check ?ff? checksum cmnx [15:8] [7:0] next command rxd txd (0xc0) product id code cmnx next command
26.14.8 flash memory status output command (0xc3) figure 26-13 flash memory status output command 26.14.9 flash memory security setting command (0xfa) figure 26-14 flash memory security setting command 26.14.10 clock change command (0xa0) figure 26-15 clock change command tmp89fw20a page 493 2012/5/18 ra000 rxd txd (0xc3) status code cmnx next command [23:16] [15:8] pnsa [7:0] fbh rxd txd (fah) cmtr3 [23:16] [15:8] [23:16] [15:8] pcsa password string start address start address increased address echo back [7:0] [23:16] [15:8] [7:0] [7:0] security setting value checksum rxd txd cmnx cmrp next command number of bytes 0x55 or 0xaa 0x55 or 0xaa 0x80 0x80 0x55 rxd txd (0xa0) cmtr3 cmck1 cmck2 cmck3 cmck4 cmnx cmck5 next command new baud rate 0xff 0xff
26.15 ac characteristics (sio) table 26-27 sio timing -1 parameter symbol time (s) min. typ. max. time from when mcu transmits 0xcf to when so0 goes low (busy) cstr2 - 15 / fcgck - time from when mcu echoes back an operation command to when sc0 goes low (busy) cstr3 - 15 / fcgck - time required to calculate the checksum for the flash memory sum output command csfsm - 5609760 / fcgck - time required to calculate the checksum for the flash memory write command csfwr - 5718880 / fcgck - time required to perform erasure and calculate the checksum for the flash memory erase command chip erase csfer - 5365232 / fcgck + 1501 / fcgck + 400ms + 100ms - sector erase - 5616208 / fcgck + 1362 / fcgck + 100ms - time required to set security by the flash memory security setting com- mand (i = number of bits to be set) csfrp - 801 / fcgck + (187 x i ) / fcgck + (100ms x i ) - note 1: the security setting time (csfsc) varies with the number of bits to be programmed (i = 1 to 3). note 2: the above values include the warm-up time until oscillation stabilizes and may vary greatly depending on the character- istics of the oscillator to be used. tmp89fw20a 26. serial prom mode 26.15 ac characteristics (sio) page 494 2012/5/18 ra000
table 26-28 sio timing -2 parameter symbol time (s) min. typ. max. time to hold mode and reset pins low after power-on rssup - 10 ms - time from when si0 pin goes high to the acceptance of si0 rxsup - 20 ms - time from when mcu completes receiving 0x30 to when so0 goes low (busy) cseb1 - 81 / fcgck - time from when mcu completes receiving 0xcf to when so0 goes low (busy) cseb2 - 44 / fcgck - time from when mcu completes receiving an operation command to when sc0 goes low (busy) cseb3 - 41 / fcgck - time from when mcu starts receiving erase range data of the flash memory erase command to when sc0 goes low (busy) ceeb1 - 107 / fcgck - time from when mcu completes receiving intel-hex data of the flash memory write command to when sc0 goes low (busy) cweb1 - 79 / fcgck - time from when mcu completes receiving the checksum of the secur- ity setting command to when sc0 goes low (busy) cpeb1 - 63 / fcgck - time from when mcu completes receiving intel-hex data of the ram loader command to when sc0 goes low (busy) cleb1 - 65 / fcgck - time from when mcu starts receiving the lower 8 bits of the read byte count of the flash memory read command to when sc0 goes low (busy) creb1 - 75 / fcgck - table 26-29 sio timing -3 parameter symbol time (s) min. typ. max. transfer clock width (1 bit) csbit 40 / fcgck - - transfer cock width (8 bits) csbyte 320 / fcgck - - tmp89fw20a page 495 2012/5/18 ra000
26.15.1 sio transfer timing figure 26-16 sio transfer timing 26.15.2 reset timing figure 26-17 reset timing tmp89fw20a 26. serial prom mode 26.15 ac characteristics (sio) page 496 2012/5/18 ra000 csbit csbyte si0 (0x30) rxsup rssup cseb1 be sure to confirm so is high level, before input the sclk, (0xcf) so0 sclk0 reset mode v dd (0x30) (0xcf) cseb2 cseb3 operation command cstr2 cstr3
26.15.3 flash memory erase command (0xf0) figure 26-18 flash memory erase command tmp89fw20a page 497 2012/5/18 ra000 si0 (0xf0) cseb3 so0 set to be high level during mcu recives password string. so0 sclk0 si0 so0 sclk0 (0xf0) cstr3 cstr3 cstr3 [23:16] [15:8] pnsa [7:0] [23:16] [15:8] pcsa password string area to be erased [7:0] [15:8] [7:0] checksum ceeb1 cmfer next command
26.15.4 flash memory write command (0x30) figure 26-19 flash memory write command tmp89fw20a 26. serial prom mode 26.15 ac characteristics (sio) page 498 2012/5/18 ra000 si0 (0x30) cseb3 cweb1 cstr3 cstr3 cstr3 so0 sclk0 si0 so0 sclk0 (0x30) [23:16] [15:8] pnsa [7:0] [23:16] [15:8] pcsa password string [7:0] intelhex (data record) intelhex (data record) intelhex (data record) (0x3a) (0x3a) si0 so0 sclk0 intelhex (end record) (0x3a)(0x00) (0x00) (0x00) (0x00) (0x00) (0x01) (0xff) (0x55) or (0xaa) csfwr overwrite detection next command si0 so0 sclk0 [15:8] [7:0] checksum
26.15.5 flash memory read command (0x40) figure 26-20 flash memory read command tmp89fw20a page 499 2012/5/18 ra000 si0 (0x40) cseb3 creb1 cstr3 cstr3 cstr3 cstr3 cstr3 so0 sclk0 si0 so0 sclk0 (0x40) [23:16] [15:8] pnsa [7:0] [23:16] [15:8] number of read bytes [7:0] read data [23:16] [15:8] [23:16] [15:8] pcsa password string [7:0] [7:0] next command read start address [15:8] [7:0] checksum
26.15.6 ram loader command (0x60) figure 26-21 ram loader command tmp89fw20a 26. serial prom mode 26.15 ac characteristics (sio) page 500 2012/5/18 ra000 si0 (0x60) cseb3 cleb1 cstr3 cstr3 so0 sclk0 si0 so0 sclk0 (0x60) [23:16] [15:8] pnsa [7:0] [23:16] [15:8] pcsa password string [7:0] intelhex (data record) intelhex (data record) intelhex (data record) (0x3a) (0x3a) si0 so0 sclk0 intelhex (end record) execute ram program (0x3a)(0x00) (0x00) (0x00) (0x00) (0x00) (0x01) (0xff) csrsm [15:8] [7:0] checksum
26.15.7 flash memory sum output command (0x90) figure 26-22 flash memory sum output command 26.15.8 product id code output command (0xc0) figure 26-23 product id code output command 26.15.9 flash memory status output command (0xc3) figure 26-24 flash memory status output command tmp89fw20a page 501 2012/5/18 ra000 si0 (0x90) cseb3 so0 sclk0 (0x90) cstr3 cstr3 cstr3 cstr3 next command (0x55) or (0xaa) [15:8] [7:0] checksum check ?ff? csfsm si0 (0xc0) cseb3 so0 sclk0 (0xc0) cstr3 cstr3 cstr3 cstr3 cstr3 cstr3 next command product id code si0 (0xc3) cseb3 so0 sclk0 (0xc3) cstr3 cstr3 cstr3 cstr3 cstr3 cstr3 next command status code
26.15.10 flash memory security setting command (0xfa) figure 26-25 flash memory security setting command tmp89fw20a 26. serial prom mode 26.15 ac characteristics (sio) page 502 2012/5/18 ra000 si0 (0xfa) cseb3 cstr3 cstr3 cpeb1 so0 sclk0 si0 so0 sclk0 (0xfa) [23:16] [15:8] pnsa [7:0] [23:16] [15:8] pcsa password string [7:0] increased address number of transfer data next command cmfrp (0xfb) (0x07) security setting value checksum (0x80) (0x00) (0x00) (0x00) (0x80) start address (0x00) echo back
27. on-chip debug function (ocd) the tmp89fw20a has an on-chip debug function. using a combination of this function and the toshiba on- chip debug emulator rte870/c1, the user is able to perform software debugging in the on-board environment. this emulator can be operated from a debugger installed on a pc so that the emulation and debugging functions of an application program can be used to modify a program or for other purposes. this chapter describes the control pins needed to use the on-chip debug function and how a target system is con- nected to the on-chip debug function. for more detailed information on how to use the on-chip debug emulator rte870/c1, refer to the emulator operating manual. 27.1 features the on-chip debug function of the tmp89fw20a has the following features: ? debugging can be performed in much the same way as when a microcontroller packaged with the mcu is used. ? the debugging function can be realized using two communication control pins. ? useful on-chip debug functions include the following: - 8 breaks function are provided (one of which can also be used as an event function). - a trace function that allows the newest two branch instructions to be stored in real time is provided. - functions to display active memory and to overwrite active memory are provided. ? built-in flash memory can be erased and written. 27.2 control pins the on-chip debug function uses two pins for communication and four pins for power supply, reset and mode con- trol. the pins used for the on-chip debug function are shown in table 27-1. ports p20 and p21 are used as communication control pins of the on-chip debug function. if the rte870/c1 on- chip debug emulator is used, therefore, ports p20 and p21 cannot be debugged as port pins or lcd segment out- put, uart0 and sio0 pins. however, because the uart0 and sio0 functions can be assigned to other ports by us- ing sersel, these communication functions can also be used during on-chip debug operation. for de- tails, refer to the section of i/o ports. table 27-1 pins used for the on-chip debug function pin name (during on-chip debugging) input/out- put function pin name (in mcu mode) ocdck input communication control pin (clock control) (note 1) p20 / txd0 / so0 / seg29 ocdio i/o communication control pin (data control) p21 / rxd0 / si0 / seg28 reset input reset control pin reset mode input mode control pin mode vdd power supply 2.7 v to 5.5 v (note 1) vss power supply 0 v input and output ports other than p20 and p21 i/o can be used for an application in a target system xin input to be connected to an oscillator to put these pins in a state of self-oscillation xout output tmp89fw20a page 503 2012/5/18 ra000
note 1: to use all on-chip debug functions, the power supply voltage must be within the range 2.7 v to 5.5 v. if it is within the range 2.2 v to 2.7 v, functional limitations occur with some of the debug functions. for more detailed informa- tion, refer to the emulator operating manual. tmp89fw20a 27. on-chip debug function (ocd) 27.2 control pins page 504 2012/5/18 ra000
27.3 how to connect the on-chip debug emulator to a target system to use the on-chip debug function, the specific pins on a target system must be connected to an external debug- ging system. the on-chip debug emulator rte870/c1 can be connected to a target system via an interface control cable. tosh- iba provides a connector for this interface control cable as an accessory tool. mounting this connector on a tar- get system will make it easier to use the on-chip debug function. the connection between the on-chip debug emulator rte870/c1 and a target system is shown in figure 27-1. figure 27-1 how the on-chip debug emulator rte870/c1 is connected to a target system note 1: ports p20 and p21 are used as communication control pins of the on-chip debug function. if the on-chip debug emula- tor rte870/c1 is used, therefore, the port functions and the functions of uart0 and sio0, which are also used as ports, cannot be debugged. if the emulator is disconnected to be used as a single mcu, the functions of ports p20 and p21 can be used. to use the on-chip debug function, however, p20 and p21 should be disconnected using a jump- er, switch, etc. if there is the possibility of other parts affecting the communication control. note 2: if the reset control circuit on an application board affects the control of the on-chip debug function, it must be disconnec- ted using a jumper, switch, etc. note 3: the power supply voltage vdd must be provided by a target system. the vdd pin is connected to the emulator so that the level of voltage appropriate for driving communication pins can be obtained by using the power supply of a tar- get system. the connection of the vdd pin is for receiving the power supply voltage, not for supplying it from the emu- lator side to a target system. 27.4 security the tmp89fw20a provides two security functions to prevent the on-chip debug function from being used through illegal memory access attempted by a third person: a password function and a security program function. if a password is set on the tmp89fw20a, it is necessary to authenticate the password for using the on-chip de- bug function. by setting both a password and the security program on the tmp89fw20a, it is possible to prohib- it the use of all on-chip debug functions. furthermore, by using the option code, the on-chip debug function only can be used even if the security program is enabled. however, to use the on-chip debug function in this setting, a password authentication process is required. for information on how to set a password and to enable the read protection and option code, refer to "serial prom mode". tmp89fw20a page 505 2012/5/18 ra000 during on-chip debugging mcu mode vdd mode ocdck (p20) ocdio (p21) reset usb connection xin xout vss on-chip debug emulator rte870/c1 interface control cable connectors pc (host system) target system reset control other parts (note 1) (note 2) (note 3) vdd (note 3) level shifter (provided power supply by target system) control circuit (provided power supply by bus power) tmp89fw20a
tmp89fw20a 27. on-chip debug function (ocd) 27.4 security page 506 2012/5/18 ra000
28. input/output circuit 28.1 control pins the input/output circuitries of the tmp89fw20a control pins are shown below. control pin i/o circuitry remarks xin xout input output refer to the p0 ports in the chapter of input/output ports. xtin xtout input output refer to the p0 ports in the chapter of input/output ports. reset input refer to the p1 ports in the chapter of input/output ports. mode input r = 100 (typ.) hysteresis input tmp89fw20a page 507 2012/5/18 ra000 r
tmp89fw20a 28. input/output circuit 28.1 control pins page 508 2012/5/18 ra000
29. electrical characteristics 29.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operation, even for an in- stant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ev- er be exceeded. (vss = 0 v) parameter symbol pins ratings unit supply voltage v dd ?0.3 to 6.0 v input voltage v in1 p0, p1, p2, p4, p5, p6, p7, p9 (three state port) ?0.3 to v dd + 0.3 v v in2 ain0 to ain7 (analog input voltage) ?0.3 to a vdd + 0.3 output voltage v out1 ?0.3 to v dd + 0.3 v output current (per pin) i out1 p0, p1, p2, p4, p5 (include three state port and pull-up resistor) -10 ma i out2 p6, p7, p9 (include three state port and pull-up resistor) -10 i out3 p0, p1, p2, p4, p5 (include three state port and pull-down resistor) 20 i out4 p6, p7, p9 (include three state port and pull-down resistor) 20 output current (total) i out1 p0, p1, p2, p4, p5 (include three state port and pull-up resistor) -25 i out2 p6, p7, p9 (include three state port and pull-up resistor) -25 i out3 p0, p1, p2, p4, p5 (include three state port, pull-down resistor) 40 i out4 p6, p7, p9 (include three state port and pull-down ) 40 power dissipation (topr = 85 c) p d 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ?55 to 125 operating temperature topr ?40 to 85 tmp89fw20a page 509 2012/5/18 ra000
29.2 operating conditions the operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the operating conditions (sup- ply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when design- ing products which include this device, ensure that the operating conditions for the device are always adhered to. 29.2.1 mcu mode (flash programming or erasing) (v ss = 0 v, topr = ?10 to 40c) parameter symbol pins condition min typ max unit supply voltage v dd normal1, 2 modes 2.7 ? 5.5 v input high level v ih1 mode pin v dd 4.5 v v dd 0.70 ? v dd v ih2 hysteresis input v dd 0.75 ? v ih3 v dd < 4.5 v v dd 0.90 ? input low level v il1 mode pin v dd 4.5 v 0 ? v dd 0.30 v il2 hysteresis input ? v dd 0.25 v il3 v dd < 4.5 v ? v dd 0.10 clock frequency fc xin, xout v dd 2.7 v 1.0 ? 16.0 mhz fosc internal high-frequency clock 9.5 10.0 10.5 fcgck 0.25 ? 16.0 figure 29-1 clock gear (fcgck) and external high-frequency clock (fc) tmp89fw20a 29. electrical characteristics 29.2 operating conditions page 510 2012/5/18 ra000 1 [mhz] [v] 5.5 2.7 [mhz] high-frequency clock(fc) frequency range [v] 1.8 8 16 0.25 5.5 2.7 1.8 8 16 gear clock(fcgck) frequency range
29.2.2 mcu mode (except flash programming or erasing) (v ss = 0 v, topr = ?40 to 85c) parameter symbol pins condition min typ max unit supply voltage v dd fc = 16.0 mhz normal1, 2 modes idle0, 1, 2 modes 2.7 ? 5.5 v fc = 8.0 mhz 1.8 ? fs = 32.768 khz slow1, 2 modes sleep0, 1 modes stop mode input high leve v ih1 mode pin v dd 4.5 v v dd 0.70 ? v dd v v ih2 hysteresis input v dd 0.75 ? v ih3 v dd < 4.5 v v dd 0.90 ? input low leve v il1 mode pin v dd 4.5 v 0 ? v dd 0.30 v il2 hysteresis input ? v dd 0.25 v il3 v dd < 4.5 v ? v dd 0.10 clock frequency fc xin, xout v dd = 2.7 to 5.5 v 1.0 ? 16.0 mhz v dd = 1.8 to 5.5 v ? 8.0 fosc internal high-frequency clock v dd = 1.8 to 5.5 v 9.5 10.0 10.5 fcgck v dd = 2.7 to 5.5 v 0.25 ? 16.0 v dd = 1.8 to 5.5 v ? 8.0 fs xtin, xtout v dd = 1.8 to 5.5 v 30.0 ? 34.0 khz figure 29-2 clock gear (fcgck) and external high-frequency clock (fc) tmp89fw20a page 511 2012/5/18 ra000 1 [mhz] [v] 5.5 2.7 [mhz] high-frequency clock(fc) frequency range [v] 1.8 8 16 0.25 5.5 2.7 1.8 8 16 gear clock(fcgck) frequency range
29.2.3 serial prom mode (v ss = 0 v, topr = ?10 to 40c) parameter symbol pins condition min typ max unit supply voltage v dd normal1, 2 modes 2.7 ? 5.5 v input high level v ih1 mode pin v dd 4.5 v v dd 0.70 ? v dd v ih2 hysteresis input v dd 0.75 ? v ih3 v dd < 4.5 v v dd 0.90 ? input low leve v il1 mode pin v dd 4.5 v 0 ? v dd 0.30 v il2 hysteresis input ? v dd 0.25 v il3 v dd < 4.5 v ? v dd 0.10 clock frequency fc xin, xout v dd 2.7 v 1.0 ? 16.0 mhz fosc internal high-frequency clock 9.5 10.0 10.5 fcgck 0.25 ? 16.0 figure 29-3 clock gear(fcgck) and external high-frequency clock (fc) tmp89fw20a 29. electrical characteristics 29.2 operating conditions page 512 2012/5/18 ra000 1 [mhz] [v] 5.5 2.7 [mhz] high-frequency clock(fc) frequency range [v] 1.8 8 16 0.25 5.5 2.7 1.8 8 16 gear clock(fcgck) frequency range
29.3 dc characteristics (v ss = 0 v, topr = ?40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 5.5 v v in = 5.5 v/0 v ? 0.9 ? v input current i in1 mode ? ? 2 a i in2 p0, p1, p2, p4, p5, p7, p9, pb i in3 reset, stop input resistance r in2 reset pull-up v dd = 5.5 v, v in = 0 v 100 220 500 k r in3 p0, p1, p2, p8 30 50 100 output leakage current i lo2 p0, p1, p2, p4, p5, p6, p7, p9 v dd = 5.5 v, v out = 5.5 v/0 v ? ? 2 a output high voltage v oh p0, p1, p2, p4, p5, p6, p7, p9 ( except xout, xtout) v dd = 4.5 v, i oh = ?0.7ma 4.1 ? ? v output low voltage v ol p0, p1, p2, p4, p5, p6, p7, p9 ( except xout, xtout) v dd = 4.5 v, i ol = 1.6 ma ? ? 0.4 v output low current i ol p9, p84 to p87 v dd = 4.5 v, v ol = 1.0 v ? 10 ? ma note 1: typical values show those at topr = 25c and v dd = 5.0 v. note 2: input current i in3 : the current through pull-up resistor is not included. (v ss = 0 v, topr = ?40 to 85 c) parameter symbol pins condition min typ. max unit supply current in normal 1, 2 modes i dd v dd = 5.5 v v in = 5.3 v/0.2v fcgck = 16.0 mhz fs = 32.768 khz (when external high frequency clock operation.) sdwcr1="0" (when a pro- gram operates on flash memory) ? 4.4 7.0 ma sdwcr1="1" (when a program operates on ram) ? 3.5 5.6 supply current in idle1, 2 modes sdwcr1="0" ? 3.6 6.0 sdwcr1="1" ? 3.0 5.2 supply current in idle0 modes sdwcr1="0" ? 2.4 4.6 sdwcr1="1" ? 1.8 3.9 supply current in normal1, 2 modes v dd = 5.5 v v in = 5.3 v/0.2v fcgck = 10.0 mhz fs = 32.768 khz (when internal high frequency clock operation.) sdwcr1="0" (when a pro- gram operates on flash memory) ? 3.3 3.8 sdwcr1="1" (when a pro- gram operates on ram) ? 2.5 2.8 supply current in idle1, 2 modes sdwcr1="0" ? 2.7 3.2 sdwcr1="1" ? 1.8 2.0 supply current in idle0 modes sdwcr1="0" ? 1.8 2.3 sdwcr1="1" ? 1.4 1.6 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz sdwcr1="0" (when a pro- gram operates on flash memory) ? 550 850 a sdwcr1="1" vltd enable topr=25c ? 9 12 topr=85c ? ? 60 sdwcr1="1" vltd disable topr=25c ? 8 11 topr=85c ? ? 60 supply current in sleep1 mode sdwcr1="0" ? 490 630 sdwcr1="1" ? 8 60 supply current in sleep0 mode sdwcr1="0" ? 490 620 sdwcr1="1" ? 8 60 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v vltd enable ? 10 50 vltd disable ? 8 50 tmp89fw20a page 513 2012/5/18 ra000
(v ss = 0 v, topr = ?40 to 85 c) parameter symbol pins condition min typ. max unit current for writing to flash memory, erasing and security program i ddew v dd = 5.5 v v in = 5.3 v/0.2 v ? 4.2 ? ma note 1: typical values shown are topr = 25c and v dd = 5.0 v, unless otherwise specified. note 2: i dd does not include i ref . it is the electrical current in the state in which the peripheral circuitry has been operated. note 3: each supply current in slow2 mode is equivalent to that in idle0, idle1 and idle2 modes. note 4: vltd (voltage detection circuit) tmp89fw20a 29. electrical characteristics 29.3 dc characteristics page 514 2012/5/18 ra000
29.4 ad conversion characteristics (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ?40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref avdd-1.0 ? a vdd v power supply voltage of analog con- trol circuit a vdd v dd analog reference voltage range (note4) v aref 3.5 ? ? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ? 0.60 0.76 ma non-linearity error v dd = a vdd = 5.0 v, v ss = a vss = 0.0 v v aref = 5.0 v ? ? 2 lsb zero point error ? ? 2 full scale error ? ? 2 total error ? ? 2 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ?40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref avdd-1.0 ? a vdd v power supply voltage of analog con- trol circuit a vdd v dd analog reference voltage range (note4) v aref 2.5 ? ? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 4.5 v v ss = a vss = 0.0 v ? 0.49 0.62 ma non-linearity error v dd = a vdd = 2.7 v v ss = a vss = 0.0 v v aref = 2.7 v ? ? 2 lsb zero point error ? ? 2 full scale error ? ? 2 total error ? ? 2 (v ss = 0.0 v, 2.2 v v dd < 2.7 v, topr = ?40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref avdd-0.5 ? a vdd v power supply voltage of analog con- trol circuit a vdd v dd analog reference voltage range (note4) v aref 2.5 ? ? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 2.7 v v ss = a vss = 0.0 v ? 0.29 0.37 ma non-linearity error v dd = a vdd = 2.2 v v ss = a vss = 0.0 v v aref = 2.2 v ? ? 4 lsb zero point error ? ? 4 full scale error ? ? 4 total error ? ? 4 note 1: the total error includes all errors except a quantization error, and is defined as the maximum deviation from the ideal conversion line. note 2: conversion times differ with variation in the power supply voltage. note 3: the voltage to be input to the ain input pin must be within the range v aref to v ss . if a voltage outside this range is in- put, converted values will become indeterminate, and converted values of other channels will be affected. note 4: analog reference voltage range: v aref = v aref ? v ss note 5: if the ad converter is not used, fix the a vdd pins to the v dd level. tmp89fw20a page 515 2012/5/18 ra000
29.5 power-on reset circuit characteristics figure 29-4 power-on reset operation timing note: care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (v dd ). (v ss = 0 v, topr = ?40 to 85c) symbol parameter min. typ. max. unit v proff power-on reset releasing voltage ? 1.5 ? v t pwup warming-up time after a reset is cleared ? 102 x 2 9 /fosc ? s t cpy shadow ram copying time ? 3072/(fcgck x 4) ? s t vdd power supply rise time ? ? 5 ms note 1: a clock output by an oscillating circuit is used as the input clock for a warming-up counter. because the oscillation fre- quency does not stabilize until an oscillating circuit stabilizes, some errors may be included in the warming-up time. note 2: boost the power supply voltage such that t vdd becomes smaller that t pwup . tmp89fw20a 29. electrical characteristics 29.5 power-on reset circuit characteristics page 516 2012/5/18 ra000 operating voltage warm-up counter start shadow ram copy start ? t pwup t vdd v proff power supply voltage(v dd ) t cpy power-on reset signal warm-up counter clock cpu and peripheral circuit reset signal
29.6 voltage detecting circuit characteristics figure 29-5 operation timing of the voltage detecting circuit note: care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (v dd ). (v ss = 0 v, topr = ?40 to 85c) symbol parameter min. typ. max. unit t vltoff voltage detection releasing response time ? 150 300 us t vlton voltage detecting detection response time ? 40 60 t vltpw voltage detecting minimum pulse width 10 ? ? tmp89fw20a page 517 2012/5/18 ra000 level of detected voltage operating voltage signal to request the voltage detection interrupt voltage detection request signal t vltoff t vltopw t vlton power supply voltage(v dd )
29.7 16-bit timer counter(tcb) characteristics (v ss = 0 v, topr = ?40 to 85c) parameter symbol condition min typ. max unit tcb0 pin input pulse width t tcb0 normal1,2 modes idle1, 2 modes 2 / fcgck ? ? s slow1, 2 modes sleep1 modes 2 / fs ? ? 29.8 lcd characteristics (v ss = 0 v, topr = ?40 to 85c) parameter symbol pins condition min typ. max unit supply voltage v dd 1.8 - 5.5 v power supply for lcd driver v lc vlc lcd driver is enable 2.2 - v dd v lcd driver is not enable 1.8 - v dd v internal bleeder re- sistance r h1 375 500 625 k r h2 150 200 250 r l 15 20 25 note 1: lcd driver should be disabled when the power supply for lcd driver (v lc ) falls to or below the 2.2v. note 2: r h1 ,r h2 :high resistance note 3: r l :low resistance tmp89fw20a 29. electrical characteristics 29.7 16-bit timer counter(tcb) characteristics page 518 2012/5/18 ra000
29.9 ac characteristics 29.9.1 mcu mode (flash programming or erasing) (v ss = 0 v, v dd = 2.7 v to 5.5 v, topr = ?10 to 40c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.0625 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external high-frequency clock operation (xin input). fc = 16.0mhz ? 31.25 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external low-frequency clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl 29.9.2 mcu mode (except flash programming or erasing) (v ss = 0 v, v dd = 2.7 v to 5.5 v, topr = ?40 to 85c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.0625 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external high-frequency clock operation (xin input). fc = 16.0mhz ? 31.25 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external low-frequency clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, v dd = 1.8 v to 5.5 v, topr = ?40 to 85c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.125 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external high-frequency clock operation (xin input). fc = 8.0 mhz ? 62.5 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external low-frequency clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl tmp89fw20a page 519 2012/5/18 ra000
29.9.3 serial prom mode (v ss = 0 v, v dd = 2.7 v to 5.5 v, topr = ?10 to 40c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.0625 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external high-frequency clock operation (xin input). fc = 16.0mhz ? 31.25 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external low-frequency clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl 29.10 flash characteristics 29.10.1 write characteristics (v ss = 0 v, topr = ?10 to 40c) parameter condition min typ. max. unit number of guaranteed writes to flash memory ? ? 100 times flash memory write time per 1 page (128 bytes) ? 1.25 3 ms flash memory erase time chip erase ? 400 1000 sector erase ? 100 250 tmp89fw20a 29. electrical characteristics 29.10 flash characteristics page 520 2012/5/18 ra000
29.11 recommended oscillating condition note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these fac- tors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the de- vice will actually be mounted. note 2: the product numbers and specifications of the resonators supplied by murata manufacturing co., ltd. are subject to change. for up to date information, please refer to the following http://www.murata.com tmp89fw20a page 521 2012/5/18 ra000 (2) low-frequency oscillation (1) high-frequency oscillation xin xout c 2 c 1 xtin xtout c 2 c 1
29.12 handling precaution - the solderability test conditions are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245c dipping time = 5 seconds number of times = once r-type flux used the pass criteron of the above test is as follows: solderability rate until forming 95% - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. tmp89fw20a 29. electrical characteristics 29.12 handling precaution page 522 2012/5/18 ra000
30. package dimensions tmp89fw20a page 523 2012/5/18 ra000 lqfp64-p-1010-0.50e unit: mm
tmp89fw20a 30. package dimensions page 524 2012/5/18 ra000
tmp89fw20a page 525 2012/5/18 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the in forma- tion in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human lif e, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs includ ing the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the lates t ver- sions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and appli- cation notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and ( b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this p roduct in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all oper- ating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications . ? product is neither intended nor warranted for use in equipments or systems that require extraor- dinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage and/or serious public impact ("unintended use"). except for specific applications as expressly stated in this document, unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used f or automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or expl o- sions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related field s. if you use product for unintended use, toshiba assumes no liability for product. for details, please contact your toshiba sales representative. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchant- ability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limita- tion, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile tec hnol- ogy products (mass destruction weapons). product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the japanese foreign exchange and foreign trade law and the u.s. export administration regulations. export and re-export of product or related software or technology are strictly prohibited ex cept in compliance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro d- uct. please use product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled sub- stances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.
tmp89fw20a 31. page 526 2012/5/18


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